JPS6293250U - - Google Patents
Info
- Publication number
- JPS6293250U JPS6293250U JP17849886U JP17849886U JPS6293250U JP S6293250 U JPS6293250 U JP S6293250U JP 17849886 U JP17849886 U JP 17849886U JP 17849886 U JP17849886 U JP 17849886U JP S6293250 U JPS6293250 U JP S6293250U
- Authority
- JP
- Japan
- Prior art keywords
- buffer memory
- invalidate
- row
- blocks
- column
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は、アドレスアレイ、バツフアメモリ、
主記憶装置との関係を示す図、第２図は、本考案
の実施例ブロツク図、第３図は、本考案動作タイ
ムチヤートを示す図である。
図において、１は実効アドレスレジスタ、３は
アドレスアレイ、６はバツフアメモリ。
Figure 1 shows address array, buffer memory,
FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a diagram showing an operation time chart of the present invention. In the figure, 1 is an effective address register, 3 is an address array, and 6 is a buffer memory.
Claims (1)
し、該バツフアメモリと主記憶装置間の情報伝送
がＳＷＡＰ方式で実行されるバツフア制御方法に
おいて、ｍ行ｎ列で構成されるバツフアメモリの
無効化の際に、ｍｉ行に対応するｎ列全てのブロ
ツクを無効化すると共に、ｍｉ＋１行に対応する
ｎ列全てのブロツクを無効とするように動作を行
うことを特徴とするバツフア制御回路。 In a buffer control method that has a set associative buffer memory and in which information transmission between the buffer memory and the main storage device is executed by the SWAP method, when the buffer memory configured with m rows and n columns is invalidated, 1. A buffer control circuit that operates to invalidate all blocks in column n corresponding to row mi+1 and invalidate all blocks in column n corresponding to row mi+1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986178498U JPH0215150Y2 (en) | 1986-11-20 | 1986-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986178498U JPH0215150Y2 (en) | 1986-11-20 | 1986-11-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6293250U true JPS6293250U (en) | 1987-06-15 |
| JPH0215150Y2 JPH0215150Y2 (en) | 1990-04-24 |
Family
ID=31120684
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986178498U Expired JPH0215150Y2 (en) | 1986-11-20 | 1986-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0215150Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5577070A (en) * | 1978-12-01 | 1980-06-10 | Toshiba Corp | Cash memory control system |
-
1986
- 1986-11-20 JP JP1986178498U patent/JPH0215150Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5577070A (en) * | 1978-12-01 | 1980-06-10 | Toshiba Corp | Cash memory control system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0215150Y2 (en) | 1990-04-24 |
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