JPS5577070A - Cash memory control system - Google Patents
Cash memory control systemInfo
- Publication number
- JPS5577070A JPS5577070A JP14785278A JP14785278A JPS5577070A JP S5577070 A JPS5577070 A JP S5577070A JP 14785278 A JP14785278 A JP 14785278A JP 14785278 A JP14785278 A JP 14785278A JP S5577070 A JPS5577070 A JP S5577070A
- Authority
- JP
- Japan
- Prior art keywords
- cash
- flush
- arithmetic
- control circuit
- pass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To reduce the performance lowering of arithmetic control by small hardware, by operating an arithmetic controller even in case flush mode.
CONSTITUTION: Once a flush instruction is sent to a cash memory, flush FF is set to send its output to flush control circuit 21 and the cash memory starts flushing by a busy signal from cash control circuit 23. Then, the update of a counter and the resetting of V vits are sequentially carried out and when V bits at all positions are reset, FF20 is also reset. On the other hand, the output of FF20 and that of by- pass FF22 are OR-ed by OR circuit 25, whose output is supplied to control circuit 23, so that while FF20 is set, the cash by-pass mode will be in effect. Therefore, an arithmetic unit can be operated in the cash by-pass state during cash flush operation, so that the performance lowering of arithmetic control can be reduced by small hardware.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14785278A JPS5577070A (en) | 1978-12-01 | 1978-12-01 | Cash memory control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14785278A JPS5577070A (en) | 1978-12-01 | 1978-12-01 | Cash memory control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5577070A true JPS5577070A (en) | 1980-06-10 |
JPS5744991B2 JPS5744991B2 (en) | 1982-09-25 |
Family
ID=15439707
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14785278A Granted JPS5577070A (en) | 1978-12-01 | 1978-12-01 | Cash memory control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5577070A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS589275A (en) * | 1981-07-10 | 1983-01-19 | Fujitsu Ltd | Buffer controlling method |
JPS6293250U (en) * | 1986-11-20 | 1987-06-15 | ||
JPS6339058A (en) * | 1986-08-01 | 1988-02-19 | Nec Corp | Invalidating system for cache memory device |
JPH01169647A (en) * | 1987-12-25 | 1989-07-04 | Hitachi Ltd | Information processor |
EP0655689A2 (en) * | 1987-02-18 | 1995-05-31 | Nec Corporation | Cache memory control system |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5751180U (en) * | 1980-09-09 | 1982-03-24 |
-
1978
- 1978-12-01 JP JP14785278A patent/JPS5577070A/en active Granted
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS589275A (en) * | 1981-07-10 | 1983-01-19 | Fujitsu Ltd | Buffer controlling method |
JPS6339058A (en) * | 1986-08-01 | 1988-02-19 | Nec Corp | Invalidating system for cache memory device |
JPS6293250U (en) * | 1986-11-20 | 1987-06-15 | ||
JPH0215150Y2 (en) * | 1986-11-20 | 1990-04-24 | ||
EP0655689A2 (en) * | 1987-02-18 | 1995-05-31 | Nec Corporation | Cache memory control system |
EP0655689A3 (en) * | 1987-02-18 | 1995-10-11 | Nec Corp | Cache memory control system. |
JPH01169647A (en) * | 1987-12-25 | 1989-07-04 | Hitachi Ltd | Information processor |
Also Published As
Publication number | Publication date |
---|---|
JPS5744991B2 (en) | 1982-09-25 |
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