JPS61218149A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61218149A JPS61218149A JP60058331A JP5833185A JPS61218149A JP S61218149 A JPS61218149 A JP S61218149A JP 60058331 A JP60058331 A JP 60058331A JP 5833185 A JP5833185 A JP 5833185A JP S61218149 A JPS61218149 A JP S61218149A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- oxide film
- copper
- surface roughness
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 230000003746 surface roughness Effects 0.000 claims abstract description 8
- 239000004020 conductor Substances 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052802 copper Inorganic materials 0.000 abstract description 10
- 239000010949 copper Substances 0.000 abstract description 10
- 238000007747 plating Methods 0.000 abstract description 9
- 238000005498 polishing Methods 0.000 abstract description 9
- 229910000881 Cu alloy Inorganic materials 0.000 abstract description 8
- 239000010931 gold Substances 0.000 abstract description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 229910052709 silver Inorganic materials 0.000 abstract description 5
- 239000004332 silver Substances 0.000 abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 239000011347 resin Substances 0.000 abstract description 2
- 229920005989 resin Polymers 0.000 abstract description 2
- 239000000919 ceramic Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 235000013339 cereals Nutrition 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4835—Cleaning, e.g. removing of solder
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 本発明は、半導体集積回路などの半導体装置に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to semiconductor devices such as semiconductor integrated circuits.
特開昭５７−１０９３５１号「半導体装置」には、半導
体装置のフレームに銀層をメッキした場合に起り得る稲
々の弊害が開示されている。そして、上記弊害を解決す
る手段として、銀層をメッキせずに還元性雰囲気中で金
ワイヤーの一端をボンディングする旨の技術が開示され
ている。JP-A-57-109351 ``Semiconductor Device'' discloses the harmful effects of rice grains that can occur when the frame of a semiconductor device is plated with a silver layer. As a means to solve the above problems, a technique has been disclosed in which one end of a gold wire is bonded in a reducing atmosphere without plating a silver layer.
ところで、本発明者の検討によると、フレームに銅また
は銅合金を使用した場合、脱脂洗浄しただけでは良好な
ボンディングを行ない得ないことが判明した。そこで原
因究明を行ったのであるが、その結果フレームを製造す
る際に表面あらさを低減するためロール整形が行われ、
この際フレームの表面に酸化膜が形成され、更に酸化膜
の下層に加工歪層が形成され、これに起因して良好なボ
ンディングを行ない得ないのではないか、との結論に達
した。By the way, according to studies conducted by the present inventors, it has been found that when copper or copper alloy is used for the frame, good bonding cannot be achieved simply by degreasing and cleaning. Therefore, we investigated the cause and found that roll shaping was performed to reduce surface roughness when manufacturing the frame.
At this time, an oxide film was formed on the surface of the frame, and a strained layer was formed under the oxide film, and it was concluded that good bonding could not be performed due to this.
本発明の目的は、半導体装置のフレームにメッキを施こ
丁ことなく半導体チップとのボンディングを良好に行な
い、生産コストを大幅圧低減することのできろ半導体装
置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can be bonded well to a semiconductor chip without plating the frame of the semiconductor device, and can significantly reduce production costs.
本発明の上記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明の概要を簡単に述べれば、
下記のとおりである。A brief summary of the invention disclosed in this application is as follows:
It is as follows.
丁なわち、半導体集積回路の如き半導体装置にリード端
子として使用される銅、或いは銅合金の表面に形成され
ている酸化膜、加工歪層を除去するとともに、その表面
粗さを適度に形成し、金メッキや銀メッキ等を行うこと
な（低コストで良好なボンディングを行う、という本発
明の目的を達成するものである。In other words, it removes the oxide film and strained layer formed on the surface of copper or copper alloy used as lead terminals in semiconductor devices such as semiconductor integrated circuits, and also forms the surface roughness to an appropriate level. The object of the present invention is to perform good bonding at low cost without performing gold plating, silver plating, etc.
次Ｋ、第１図〜第７図を参照して本発明を適用した半導
体装置の一実施例を説明する。Next, one embodiment of a semiconductor device to which the present invention is applied will be described with reference to FIGS. 1 to 7.
本実施例の特徴は、銅や銅合金の表面酸化膜等を電解研
摩法、光沢化学研摩法、エツチング法などＫよって除去
し、メッキを施こすことなく良好なワイヤーボンディン
グを行えるようＫしたことにある。The feature of this example is that the surface oxide film of copper or copper alloy is removed by electrolytic polishing, bright chemical polishing, etching, etc., so that good wire bonding can be performed without plating. It is in.
第１図は半導体集積回路（以下においてＩＣという）Ｋ
使用されるフレームの一例を示すものであり、その表面
（斜線部分）の酸化膜等が後述する電解研摩法、化学研
摩法、エツチング法などにより除去されている。Figure 1 shows a semiconductor integrated circuit (hereinafter referred to as IC) K.
This shows an example of a frame used, and the oxide film and the like on its surface (hatched area) have been removed by electrolytic polishing, chemical polishing, etching, etc., which will be described later.
フレームｌは例えば銅をプレス加工して図示の形状に形
成したものであり、実際には同一形状のものがベルト状
になっている（業界ではフープと呼んでいる）が点線で
囲った部分がＩＣ１個に使用される。そして、中央部の
タブ２に半導体チップ（図示せず）が設けられ、半導体
チップのタブとインナーリードとの先端部分とがＡｕ線
により接続され、ダム３は切断される。The frame l is made by press-working copper into the shape shown in the figure, and in reality, the same shape is in the form of a belt (called a hoop in the industry), but the part surrounded by dotted lines is Used for one IC. Then, a semiconductor chip (not shown) is provided on the central tab 2, the tab of the semiconductor chip and the tip of the inner lead are connected by an Au wire, and the dam 3 is cut.
上記ボンディング工程終了後は、セラばツク。After the above bonding process is completed, it is sealed.
レジン等によりモールドされるのであるが、半完成の状
態では第２図に示すようにパッケージ４の周囲からアウ
ターリード（外部接続端子）５が突出したようになり、
各アウターリード５は第３図に示すように折り曲げられ
る。It is molded with resin or the like, and in the semi-finished state, the outer leads (external connection terminals) 5 protrude from the periphery of the package 4, as shown in FIG.
Each outer lead 5 is bent as shown in FIG.
第３図はプリント基板２１に実装されたＩＣの要部の断
面図であり、タブ２上に取付けられた半導体チップ１１
とリード５の先端（インナーリード）とはＡｕ線６によ
って接続されている。ところで、上記フレーム１の酸化
膜の除去は、電解研摩、化学研摩又は過硫酸アンモニュ
ーム、塩化第２鉄そして、上記処理を行うことにより、
フレーム１の表面は第５図〜第７図に示すように変化す
る。上記各種研摩を行うことにより、クレーム１の表面
は第５図〜第７図に示すように変化する。FIG. 3 is a sectional view of the main parts of the IC mounted on the printed circuit board 21, and the semiconductor chip 11 mounted on the tab 2.
and the tip of the lead 5 (inner lead) are connected by an Au wire 6. By the way, the oxide film of the frame 1 can be removed by electrolytic polishing, chemical polishing, ammonium persulfate, ferric chloride, and the above treatment.
The surface of the frame 1 changes as shown in FIGS. 5-7. By performing the above various polishing processes, the surface of Claim 1 changes as shown in FIGS. 5 to 7.
丁なわち、第５図は研摩を行う以前のフレーム１の断面
図であり、４１は酸化膜、４２は加工歪層、４３は銅あ
るいは銅合金本体である。そして、第５図に示すフレー
ム１を例えば電解研摩法にもとづいて研摩すると、第６
図に示すように酸化膜４１が除去され、次に第７図に示
すように加工歪層４２が除去される。この加工歪層４２
は、結晶粒がかだ（ボンディング時にＡｕｇがつきに（
いのであるが、加工歪層４２を除去することによりボン
ダビリティが向上する。That is, FIG. 5 is a cross-sectional view of the frame 1 before polishing, in which 41 is an oxide film, 42 is a strained layer, and 43 is a copper or copper alloy main body. When the frame 1 shown in FIG. 5 is polished based on, for example, an electrolytic polishing method, a sixth
The oxide film 41 is removed as shown in the figure, and then the strained layer 42 is removed as shown in FIG. This processed strain layer 42
, the crystal grains are attached (Aug is attached during bonding (
However, bondability is improved by removing the process-strained layer 42.
ここで注目すべきは、本発明によれば上記酸化膜４１．
加工歪層４２をたんに除去するのみでな（、銅あるいは
銅合金の表面粗さを適度に設け、ボンダビリティを更に
向上させたことにある。このように丁れば、表面の凹凸
にＡｕ１１ｊ！が浸み込むようになり、ボンダビリティ
が向上する。What should be noted here is that according to the present invention, the oxide film 41.
In addition to simply removing the process-strained layer 42, bondability is further improved by providing an appropriate surface roughness of the copper or copper alloy. ! will be absorbed, and bondability will improve.
従って、フレーム１に銀等のメッキを施こ丁ことなく、
Ａｕｉによるワイヤボンディングを行うことができる。Therefore, without plating the frame 1 with silver or the like,
Wire bonding can be performed using Au.
（１）゛フレームの表面に形成された酸化膜、加工歪層
を除去し、かつフレームの表面粗さをボンディングに好
適な粗さに仕上げることにより、特にメッキを施こ丁こ
となく、ボンダビリティを向上させるという効果が得ら
れる。(1) By removing the oxide film and strained layer formed on the surface of the frame and finishing the frame to a surface roughness suitable for bonding, bondability is achieved without the need for special plating. This has the effect of improving.
（２）上記（１）により、メッキ処理が不要になるので
生産コストを大幅に低減させることができる。(2) According to the above (1), since plating treatment is not necessary, production costs can be significantly reduced.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではな（、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples (although it is possible to make various changes without departing from the gist of the invention). Not even.
例えば、上記実施例では、デュアルインライン型のＩＣ
について述べたが、ＩＣ及びその形状に限定されるもの
ではな（、トランジスタの外部接続端子であってもよい
。For example, in the above embodiment, a dual inline type IC
However, the present invention is not limited to the IC and its shape (it may also be an external connection terminal of a transistor).
以上の説明では、主として本発明者によってなされた発
明をその背景となった利用分野である半導体装置につい
て説明したが、それに限定されるものではない、
例えば、フレーム材料が銅あるいは銅合金である半導体
装置全搬について利用することができる。In the above explanation, the invention made by the present inventor was mainly explained in terms of the field of application which is the background thereof, which is a semiconductor device, but the invention is not limited thereto. It can be used for transporting all equipment.
第１図は本発明の一実施例を示す半導体装置のフレーム
の要部の平面図を示し、
第２図は牛完成状態の半導体装置の平面図を示し、
第３図は上記半導体装置の要部の断面図を示し、第４図
はフレーム表面の酸化膜等の除去方法を示す概略図を示
し。
第５図はフレームとして使用される銅又は銅合金の要部
の断面図を示し、
第６図は酸化膜を除去した状態の断面図を示し。
第７図は表面粗さを所望の粗さにした状態の断面図を示
す。
ｌ・・・フレーム、２・・・タブ、３・・・ダム％ ４
・・・ケーシング、５・・・アウターリード、６・・・
ＡｕＩｍ、１１・・・半導体チップ％ ２１・・・プリ
ント基板、２２・・・配線パターン、２３・・・半田、
４１・・・酸化膜％ ４２・・・加工歪、４３・・・銅
。FIG. 1 shows a plan view of the main parts of a frame of a semiconductor device showing an embodiment of the present invention, FIG. 2 shows a plan view of the semiconductor device in a completed state, and FIG. 3 shows main parts of the semiconductor device. FIG. 4 is a schematic diagram showing a method for removing an oxide film, etc. on the surface of the frame. Fig. 5 shows a cross-sectional view of the main part of the copper or copper alloy used as the frame, and Fig. 6 shows a cross-sectional view with the oxide film removed. FIG. 7 shows a cross-sectional view with the surface roughness set to a desired level. l...Frame, 2...Tab, 3...Dam% 4
...Casing, 5...Outer lead, 6...
AuIm, 11... Semiconductor chip % 21... Printed circuit board, 22... Wiring pattern, 23... Solder,
41... Oxide film % 42... Processing strain, 43... Copper.
Claims (1)
し、かつ表面粗さを所望の粗さに形成した導体にて構成
したことを特徴とする半導体装置。1. A semiconductor device characterized in that a connection portion between a semiconductor chip and the outside is made of a conductor from which an oxide film or the like has been removed and whose surface roughness has been formed to a desired level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60058331A JPS61218149A (en) | 1985-03-25 | 1985-03-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60058331A JPS61218149A (en) | 1985-03-25 | 1985-03-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61218149A true JPS61218149A (en) | 1986-09-27 |
Family
ID=13081319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60058331A Pending JPS61218149A (en) | 1985-03-25 | 1985-03-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61218149A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01189947A (en) * | 1988-01-26 | 1989-07-31 | Mitsubishi Shindo Kk | Lead frame member composed of copper or copper alloy |
-
1985
- 1985-03-25 JP JP60058331A patent/JPS61218149A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01189947A (en) * | 1988-01-26 | 1989-07-31 | Mitsubishi Shindo Kk | Lead frame member composed of copper or copper alloy |
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