JPS61217816A - Microcomputer - Google Patents
MicrocomputerInfo
- Publication number
- JPS61217816A JPS61217816A JP60057807A JP5780785A JPS61217816A JP S61217816 A JPS61217816 A JP S61217816A JP 60057807 A JP60057807 A JP 60057807A JP 5780785 A JP5780785 A JP 5780785A JP S61217816 A JPS61217816 A JP S61217816A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- voltage
- cpu
- circuit
- halt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Power Sources (AREA)
- Microcomputers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はマイクロ・コンビエータ、特にｃｐｖ（セント
ツル０プロセング・ユニット、中央処理装置）の動体を
停止したホールト時の消費電力を低減したマイクロ・コ
ンビ二一夕にＸｆる。[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a micro combinator, particularly a micro combinator which reduces power consumption during halt when the moving body of a cpv (center processing unit, central processing unit) is stopped. I'm going to have Xf on the 21st night.
従来より０ＭＯ８のマイクロ・コンビエータでは、クロ
ック停止時には電流が流れないというその低消費電力の
特長を生かすため、ホールト命令を設けてそのホールト
命令の実行により、発振器、タイマー等一部の回路を除
いて大部分の回路の動作を停止するというホールト状態
に設定し、消費電力を低減させ、再び起動をかけるとき
は、タイツ−・キャリー等の内部割り込みか、入力端子
からの外部割り込みによりホールト解除にされ、回路全
体の動作を再開するものがある。Conventionally, in 0MO8 micro combinators, in order to take advantage of the feature of low power consumption in which no current flows when the clock is stopped, a halt instruction is provided, and by executing the halt instruction, the oscillator, timer, and other circuits are To reduce power consumption by setting a halt state in which most of the circuits stop operating, and then restarting the circuit, the halt state must be released by an internal interrupt such as tights-carry or by an external interrupt from the input terminal. , some restart the operation of the entire circuit.
しかし、上述した従来のマイクロ・コンビエータでは発
振器、タイ！−等ホールト状態でも動いている部分の消
費電力は、ＣＰＵが動作している時と変らないため、十
分な低消費電力化ができないという欠点がある。However, in the conventional micro combinator mentioned above, the oscillator, tie! - The power consumption of the operating parts even in the halt state is the same as when the CPU is operating, so there is a drawback that it is not possible to reduce the power consumption sufficiently.
なお、低消費電力化するためには、電源電圧を低くすれ
ばよいことはよく知られているが、電源電圧を低くする
ことにより、ＣＰＵ動作時の最大動作速度も遅くなって
しまうので、好ましくない。It is well known that lowering the power supply voltage is a good way to reduce power consumption, but lowering the power supply voltage also slows down the maximum operating speed of the CPU, so it is not recommended. do not have.
本発明の目的は、ＣＰＵの動作時の電源電圧に比べて、
ＣＰＵのホールト時には低い電源電圧を内部回路に供給
する電源回路を設けることにより、ＣＰＵの動作時には
高速な動作が可能であり、ＣＰＵの停止時にはより低消
費電力のマイクロ・コンピュータを実現することにある
。The purpose of the present invention is to
By providing a power supply circuit that supplies a low power supply voltage to internal circuits when the CPU is halted, the aim is to realize a microcomputer that can operate at high speed when the CPU is operating, and consumes less power when the CPU is stopped. .
本発明のマイクロ・コンビエータは、中央処理装置の動
作時には高い電圧を停止時には低い電圧を内部回路に供
給する電源回路を含んで構成される。The micro combinator of the present invention is configured to include a power supply circuit that supplies a high voltage to the internal circuit when the central processing unit is in operation and a low voltage when the central processing unit is stopped.
次に゛、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示すブロック図である。−
次電源１はマイクロ・コンピュータ全体の電源として機
能し、ＶＤＤ電源供給端子２は電源回路４１発振器６．
タイマー９．ＲＯＭ１２゜ＣＰＵ１４．ＲＡＭ１５．入
出力回路１７に接続される。また、ＶＳＳ電源供給端子
３は電源回路４゜入出力回路１７に接続される。電源回
路４のＶｒｅｇ電源供給端子５は発振器６．タイマーｇ
、 ＲＯＭ１２゜ＣＰＵ１４．ＲＯＭ１５．入出力回
路１７に接続される。発振器６の出力であるタイマー・
クロック信号７はタイマー９へ接続され、システム・ク
ロック信号１０はＣＰＵ１４へ接続される。FIG. 1 is a block diagram showing one embodiment of the present invention. −
The secondary power supply 1 functions as a power supply for the entire microcomputer, and the VDD power supply terminal 2 is connected to the power supply circuit 41 oscillator 6.
Timer 9. ROM12°CPU14. RAM15. It is connected to the input/output circuit 17. Further, the VSS power supply terminal 3 is connected to the power supply circuit 4° input/output circuit 17. The Vreg power supply terminal 5 of the power supply circuit 4 is connected to an oscillator 6. timer g
, ROM12°CPU14. ROM15. It is connected to the input/output circuit 17. The timer which is the output of oscillator 6
Clock signal 7 is connected to timer 9 and system clock signal 10 is connected to CPU 14.
通常、ＣＰＵ１４がホールト状態になく、動作状態にも
るときは、ＣＰＵ１４はＲＯＭ１２から読み出されたプ
ログラムに従ってＲＯＭ１５．入出力回路１７との間で
演算、入出力処理を行なう。このＣＰＵ１４．が動作状
態にあるときは電源回路４はＶｒｅｇ電源供給端子５に
ｖＳＳ電源供給端子３０′出力電圧にはぼ等しい電圧を
出力する。Normally, when the CPU 14 is not in the halt state and is in the operating state, the CPU 14 reads the program from the ROM 15. Arithmetic operations and input/output processing are performed with the input/output circuit 17. This CPU14. When the power supply circuit 4 is in an operating state, the power supply circuit 4 outputs a voltage approximately equal to the output voltage of the vSS power supply terminal 30' to the Vreg power supply terminal 5.
次）Ｃ，ＣＰＵ１４はＲＯＭ１２からホールト命令を呼
び出すとホールト状態となる。ホールト状態になるとＲ
ＯＭ１２．ＣＰＵ１４．ＲＡＭ１５の動作は完全に停止
し、入出力回路１７は外部より割り込み信号があった場
合のみ動作する。このときでも、発振なりホールト信号
８がセットされると電源回路４は■ＳＳ電源供給端子３
より供給された電圧を降圧してＶＤＤ電源供給端子２の
出力電圧との電位差がより小さい電圧をＶｒｅｇ電源供
給端子５より出力する。ホールト状態はタイマー９が２
イマー・クロック信号７によりオーバー・フローしてタ
イマーキャーリー信号１１がＣＰＵ１４に入力されるか
、外部より入出力回路１７１Ｃ’割り込みがかかって外
部割り込み信号１６が入出力回路１７よりＣＰＵ１４に
入力されるとホールト状態は解除され、ホールト信号８
もリセットされ、電源回路４は降圧動作を止め、再びＶ
ｒｅｇ電源供給端子５に、Ｖ８８電源供給端子３の出力
電圧にほぼ等しい電圧を出力する。ＲＯＭ１２．ＣＰＵ
１４．ＲＡＭ１５．入出力回路１７のＶｒｅｇ電源が安
定した所でＣＰＵ１４は再び動き始める。Next) When the CPU 14 calls a halt command from the ROM 12, it enters a halt state. R when in halt state
OM12. CPU14. The operation of the RAM 15 is completely stopped, and the input/output circuit 17 operates only when an interrupt signal is received from the outside. Even at this time, if the oscillation or halt signal 8 is set, the power supply circuit 4 is connected to the SS power supply terminal 3.
The Vreg power supply terminal 5 outputs a voltage having a smaller potential difference with the output voltage of the VDD power supply terminal 2 by stepping down the voltage supplied from the Vreg power supply terminal 5 . In the halt state, timer 9 is 2
Either the timer clock signal 7 overflows and the timer carry signal 11 is input to the CPU 14, or the input/output circuit 171C' is interrupted from the outside and the external interrupt signal 16 is input to the CPU 14 from the input/output circuit 17. The halt state is released and the halt signal 8 is released.
is also reset, the power supply circuit 4 stops step-down operation, and V
A voltage approximately equal to the output voltage of the V88 power supply terminal 3 is output to the reg power supply terminal 5. ROM12. CPU
14. RAM15. When the Vreg power supply of the input/output circuit 17 becomes stable, the CPU 14 starts operating again.
なお入出力回路１７がＶｒｅｇ電源供給端子５及びＶｓ
ｓ電源供給端子３の両方から電源を供給されているのは
、外部との信号の授受を■ＳＳ電源系で行ない、ＣＰＵ
１２との信号の授受をＶｒｅｇ電源系で行なうためであ
る。Note that the input/output circuit 17 is connected to the Vreg power supply terminal 5 and the Vs
The power is supplied from both of the s power supply terminals 3. The SS power system sends and receives signals to and from the outside, and the CPU
This is because signals are exchanged with 12 using the Vreg power supply system.
第２図は電源回路４の内部回路の構成の一例を示す回路
図である。抵抗２１の抵抗値を適当に選べば、差動増幅
器２４の非反転入力端子２２にはＰチャネル・トランジ
スタ１９とＮチャネル・トランジスタ２０の閾値電圧の
和より少し大きめの電位差をＶＤＤ電源１８との間に持
つ電圧が入力される。ホールト時にはＮチャネル・トラ
ンジスタ２６はオフし、非反転入力端子２２０入力電圧
にほぼ等しい電圧が差動増幅器２４の出力として、すな
わちＶｒｅｇ ｇｌ源供給端子５に出力される。またＣ
ＰＵ１２の動作時には、差動増幅器２４の出力はハイ・
インピーダンス状態となり、Ｎチャネル・トランジスタ
２６がオン状態になるのでこの電源回路の出力電圧とし
て、Ｖｒｅｇ電源供給端子５にほぼＶｓｓ電源２５の電
圧に等しい電圧が出力される。FIG. 2 is a circuit diagram showing an example of the configuration of the internal circuit of the power supply circuit 4. As shown in FIG. If the resistance value of the resistor 21 is appropriately selected, a potential difference slightly larger than the sum of the threshold voltages of the P-channel transistor 19 and the N-channel transistor 20 will be applied to the non-inverting input terminal 22 of the differential amplifier 24 with respect to the VDD power supply 18. The voltage between them is input. During halt, the N-channel transistor 26 is turned off and a voltage approximately equal to the input voltage at the non-inverting input terminal 220 is output as the output of the differential amplifier 24, ie to the Vreg gl source supply terminal 5. Also C
When the PU 12 is operating, the output of the differential amplifier 24 is high.
Since the impedance state is established and the N-channel transistor 26 is turned on, a voltage approximately equal to the voltage of the Vss power supply 25 is outputted to the Vreg power supply terminal 5 as the output voltage of this power supply circuit.
以上説明した様に本発明は発振器及びタイマーはそれほ
ど高速性を要求されないで、発振器、タイマーが動いて
いるホールト時に内部回路の電圧を下げることにより、
ホールト時の消費電力を減らすことができ、ＣＰＵの動
作時には内部回路の電圧を上げ、高速な処理をすること
ができる効果がある。As explained above, in the present invention, the oscillator and timer are not required to be very high speed, and by lowering the voltage of the internal circuit during the halt when the oscillator and timer are operating,
This has the effect of reducing power consumption during halt, increasing the voltage of the internal circuit when the CPU is operating, and enabling high-speed processing.
第１図は本発明の一実施例を示すブロック図、第２図は
第１図に示す電源回路４の回路図である。
１・・・・・・−次電源、２・・・・・・ＶＤＤ ［源
供給端子、３・・・・・・Ｖａｓ電源供給端子、４・・
・・・・電源回路、５・・・・・・Ｖｒｅｇ電源供給端
子、６・・・・・・発振器、７・・・・・・タイマー・
クロック信号、８・・・・・・ホールト信号、９・・・
・・・タイマー、１０・・・・・・システム・クロック
信号。
１２・・・・・・ＲＯＭ、１３・・・・・・データ信号
、１４・・・・・・ＣＰＵ、１５・・・・・・ＲＡＭ、
１６・・・・・・外部割り込み信号、１７・・・・・・
入出力回路、１８・・・・・・ＶＤＤ電源、１９・・・
・・・Ｐチャネル・トランジスタ、２０．２６・・・Ｎ
チャネル・トランジスタ、２１・・・・・・抵抗、２２
・・・・・・非反転入力、２３・・・・・・反転入力、
２４・・・・・・差動増幅器、２５・・・・・・Ｖｓｓ
電源、２７・・・・・・インバータ。FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of the power supply circuit 4 shown in FIG. 1...-Next power supply, 2...VDD [source supply terminal, 3...Vas power supply terminal, 4...
...Power supply circuit, 5...Vreg power supply terminal, 6...Oscillator, 7...Timer.
Clock signal, 8... Halt signal, 9...
...Timer, 10...System clock signal. 12...ROM, 13...data signal, 14...CPU, 15...RAM,
16...External interrupt signal, 17...
Input/output circuit, 18...VDD power supply, 19...
...P-channel transistor, 20.26...N
Channel transistor, 21... Resistor, 22
...Non-inverting input, 23...Inverting input,
24...Differential amplifier, 25...Vss
Power supply, 27... Inverter.
Claims (1)
圧を内部回路に供給する電源回路を含むことを特徴とす
るマイクロ・コンピュータ。A microcomputer comprising a power supply circuit that supplies a high voltage when the central processing unit is in operation and a low voltage to the internal circuit when the central processing unit is stopped.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60057807A JPS61217816A (en) | 1985-03-22 | 1985-03-22 | Microcomputer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60057807A JPS61217816A (en) | 1985-03-22 | 1985-03-22 | Microcomputer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61217816A true JPS61217816A (en) | 1986-09-27 |
Family
ID=13066191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60057807A Pending JPS61217816A (en) | 1985-03-22 | 1985-03-22 | Microcomputer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61217816A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01206422A (en) * | 1988-02-12 | 1989-08-18 | Seiko Instr & Electron Ltd | Portable information unit with low power consumption |
| JP2005528664A (en) * | 2001-09-19 | 2005-09-22 | フリースケール セミコンダクター インコーポレイテッド | CPU power-down method and apparatus therefor |
| US7376848B2 (en) | 1997-06-27 | 2008-05-20 | Broadcom Corporation | Battery powered device with dynamic power and performance management |
-
1985
- 1985-03-22 JP JP60057807A patent/JPS61217816A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01206422A (en) * | 1988-02-12 | 1989-08-18 | Seiko Instr & Electron Ltd | Portable information unit with low power consumption |
| US7376848B2 (en) | 1997-06-27 | 2008-05-20 | Broadcom Corporation | Battery powered device with dynamic power and performance management |
| US7900067B2 (en) | 1997-06-27 | 2011-03-01 | Broadcom Corporation | Battery powered device with dynamic and performance management |
| US8504852B2 (en) | 1997-06-27 | 2013-08-06 | Broadcom Corporation | Battery powered device with dynamic power and performance management |
| JP2005528664A (en) * | 2001-09-19 | 2005-09-22 | フリースケール セミコンダクター インコーポレイテッド | CPU power-down method and apparatus therefor |
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