JPS6121530A - Information processor - Google Patents

Abstract

PURPOSE:To speed up a succeeding instruction when a processing mode is not changed by processing a connection instruction with the assmption that the processing mode is changed with the execution of an instruction and trying again the advance control if the processing mode is changed. CONSTITUTION:When an instruction renewing the mode is set to an instruction register 10, it is decoded by an instruction decoder 60 and informed to a request control circuit 80 and a restart address decision circuit 90. The restart address after the execution of the instruction is decided by a restart address after the execution of the instruction according to the instruction and set to a saving register 30. Then a preceding control unit continues to process a succeeding instruction normally. When the processing mode information to be renewed is transmitted from the operation unit through a signal line 210, it is compared with an output of a processing mode register 70 at a comparator 75, and when dissidence is detected, a request control circuit 80 transmits a cancel signal and stops the preceding processing. Then the advance processing after the change of processing mode is started by using the restart address of the save register 30 saved before.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an information processing device that includes a storage device and an instruction register and performs advance control of instructions.

[Prior art]

Generally, various processing modes are defined for an information processing device, and information on these processing modes is stored in a register or the like within the information processing device and indicates the processing mode of the information processing device. Among these processing modes, those that require changes in the program can be set by software instructions.

When processing this type of software instruction, especially in an information processing device that employs advance control of the instruction, it is impossible to predict the processing mode after the instruction is executed, so It was necessary to suppress advance control of subsequent instructions until a new processing mode was determined. For this reason,
In practice, this had the disadvantage of causing the instruction to be executed.

[Purpose of the invention]

Therefore, an object of the present invention is to provide an information processing apparatus that prevents deterioration in processing of subsequent instructions when the processing mode is not changed.

[Structure of the invention]

In the present invention, when processing an instruction that can set a processing mode,
The subsequent instructions are processed assuming that the processing mode will not be changed by the execution of the instruction, and if the processing mode is changed, the preceding control is redone from the instruction following the instruction that changed the processing mode. an instruction counter that holds the address of an instruction word retrieved from the storage device; an instruction decoder that decodes the instruction in the instruction register; an address adder for generating, a processing mode register for reading processing mode information, a comparing means for comparing processing mode information stored in the processing mode register with newly set processing mode information, and the instruction counter. and restart address determining means for determining a restart address after execution of the instruction when the instruction decoding means detects an instruction capable of updating the contents of the processing mode storage means from the output of the address adder; The advance control is stopped in response to the output of the comparison means when the contents of the save register to which the resume address determined by the address determination means is updated and the contents of the processing mode register are updated; It has means for starting processing after changing the processing mode using the saved restart address.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

The information processing device of this embodiment includes a preceding control unit 1, an arithmetic unit 2, a storage control unit 3, and a main storage device 4.

The second diagram is a detailed circuit diagram of the advance control unit 1 shown in FIG. The instruction register 1o receives instruction words successively outputted from the main memory 4 by the storage control unit 3 via a signal line 310.
It goes through a process of deterioration and is retained.

The instruction decoder 60 is held in the instruction register 1o, and forms an instruction counter together with the instruction address adder 35. Processing mode register 7° contains arithmetic unit 2.
The processing mode information sent through the signal line 210 is held. Address adder 50 is instruction register 1o
The address obtained by modifying the address with the data of the register file 20 is output. Comparator 75 compares the processing mode held in processing mode register 70 and the newly set processing mode, and outputs a signal if they do not match. The restart address determining circuit 9o is connected to the output of 1, and the instruction decoder 6o detects that the instruction held in the instruction register 10 is an instruction that can update the processing mode held in the processing mode register 70. At C2, the restart address after execution of this instruction (the next address currently being processed or the branch destination address if this instruction is a branch instruction) is determined according to the type of this instruction.

A restart address determined by the restart address determining circuit 9° is set in the save register 60. In response to the output of the comparator 75 when the contents of the processing mode register 7o are updated, the request control circuit 80 sends a cancel signal to a control 81 (not shown) to stop the advance control, and then The restart address saved in the save register 60 is used to start the process after changing the process mode.

Note that 900, 901, and 902 are selectors for switching addresses.

Next, the operation of this embodiment will be explained. Normally, the output of the instruction address register 40 is selected by the selector 902, a request is output to the storage control unit 6 via the signal line 160, and the instruction word retrieved via the signal line 6''10 is set in the instruction register 10. Assume now that an instruction that can update the mode is set in the instruction register 10.This instruction is decoded by the instruction decoder 60 and notified to the request control circuit 80 and restart address determination circuit 90. Here, the restart address after execution of this instruction is determined by the restart address determining circuit 90 according to the type of the instruction, and is set in the save register 30.

Thereafter, the advance control unit 1 continues to normally process the subsequent instruction (the instruction at the next address, or the branch destination instruction if the instruction for updating the mode is a branch instruction). An instruction that can update the mode is executed by the arithmetic unit 2, and processing mode information to be updated is sent from the arithmetic unit 2 through the signal line 210.

This processing mode information is compared with the output of the processing mode register 70 by a comparator 75, and if a mismatch is detected, the request control circuit 80 sends a cancel signal to the control section (not shown) of the advance control unit 1 to cancel the advance processing. make it stop. Thereafter, the request control circuit 80 switches the selector 902 to start the preceding processing after changing the processing mode using the restart address of the save register 60 saved previously.

〔Effect of the invention〕

As described above, the present invention determines whether or not the processing mode has actually been changed, so that it is possible to speed up subsequent instruction processing when the processing mode has not been changed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a detailed circuit diagram of the advance control unit shown in FIG. DESCRIPTION OF SYMBOLS 10... Instruction register, 20... Register file, 60... Save register, 65... Instruction address adder, 40... Instruction address register, 50... Address adder, 60... Command decoder, 7
0... Processing mode register, 75... Comparator, 80... Request control circuit, 90... Resume at, response determination circuit, 900.901, 902... Selector. 2nd rj! J

Claims (1)

[Scope of Claims] An information processing device that includes a storage device and an instruction register and performs advance control of instructions, comprising: an instruction counter that holds the address of an instruction word retrieved from the storage device; and an instruction counter that decodes the instructions in the instruction register. an address adder that generates an address using the value of the address field specified in the instruction register; a processing mode register that stores processing mode information; and a process stored in the processing mode register. An instruction capable of updating the contents of the processing mode storage means is detected in the instruction decoding means from the comparison means for comparing mode information and newly set processing mode information, and the outputs of the instruction counter and the address adder. a restart address determining means for determining the restart address after execution of the instruction; a save register to which the restart address determined by the restart address determining means is set; and a save register for determining the restart address after the execution of the instruction; An information processing device characterized by comprising means for stopping advance control in response to an output of the comparison means, and then starting processing after changing the processing mode using the restart address saved in the save register.