JPS61214813A - Voltage comparing circuit with hysteresis - Google Patents

Abstract

PURPOSE:To reduce the number of circuit elements and set freely a hysteresis width by combining two differential pairs of transistors TRs and a current mirror circuit. CONSTITUTION:A current mirror CM is connected as a load to TRs Q1 and Q2 forming a differential pair. A TR Q7 is connected to the collector of a TR 4 out of TRs Q3 and Q4 forming another differential pair. A TR Q8 whose base the output potential of the TR Q7 is given to is provided between the earth and the connection point between emitters of TRs Q3 and Q4. An input voltage is given to a terminal 5 and reference voltages are given to bases of TRS Q2 and Q4 independently of each other to perform the voltage comparing operation where the hysteresis width is determined by two reference voltages. Thus, the number of circuit elements is reduced, and the hysteresis width is set freely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a voltage comparator circuit with hysteresis used in a pulse conversion circuit that converts an analog input signal into a pulse signal.

[Technical background of the invention]

Conventionally, when it is necessary to independently select and set the two threshold voltages (threshold voltage vTII in the input voltage increasing direction and threshold voltage VTL in the input voltage decreasing direction) of a voltage comparator circuit with hysteresis, it is necessary to select and set them independently as shown in FIG. A circuit configuration is adopted. That is, the input voltage vin is the first voltage comparator 5
It is applied to the non-inverting input terminal (G) of the second voltage comparator 52 and the inverting input terminal (G) of the second voltage comparator 52. A first reference voltage (corresponding to vTH) is applied to the input terminal of the first voltage comparator 51, and this output terminal is the set input terminal of the R8 type flip-flop 7' (FF) circuit 53. Connected to S. Further, a second reference voltage (corresponding to the VTL) is applied to the (g) input terminal of the second voltage comparator 52, and this output terminal is connected to the reset input terminal R of the FF circuit 53. ing.

In the above voltage comparator circuit, as shown in FIG.
The output of the second voltage comparator 51 is at the "1" level, and the output of the second voltage comparator 52 is at the "1" level during the period when the input voltage level is smaller than the v and rL. Therefore, The FF circuit 53 is set when the input voltage level becomes higher than the VTL, and reset when the input voltage level becomes lower than the VTL, so that the output terminal Q has the voltage shown in the figure. A pulse voltage such as
Since the circuit requires 7 to 10 elements in a normal circuit configuration, there is a drawback that the entire circuit requires a large number of elements, about 21 to 30.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and provides a voltage comparison circuit with hysteresis that can significantly reduce the number of circuit elements used, can independently set the voltage at both ends of the hysteresis width, and can freely set the hysteresis width. It is.

[Summary of the invention]

That is, in the voltage comparator circuit with hysteresis of the present invention, a current mirror circuit is connected as a common load to the differential pair transistors of the second differential pair transistor and the differential pair transistor of ta2, and the current mirror circuit is connected as a common load to the differential pair transistor of the second differential pair transistor. An output buffer circuit that takes the collector potential as input is provided,
A transistor to which the output potential of the 7A circuit is applied as a base input is connected between the emitter interconnection point of the second differential pair transistor and the ground terminal, and the first differential pair and the second The same voltage is applied to the base of each one transistor of the differential pair, and voltages of different levels are applied to the bases of each other transistor.

As a result, for example, the input voltage can be used as the same voltage, and the first . By applying the second reference voltage independently, a voltage comparison operation is performed in which the hysteresis width is determined by these two reference voltages, and the number of circuit elements used is extremely small, resulting in a simple circuit configuration. .

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, the emitters of a PNP-type first transistor Q1 and a second transistor Q2 are connected to each other to form a first differential pair. , 6. A first constant current source 1 for supplying constant current 1 is connected between this emitter connection point and the VCC power source. And the first transistor Q! An input voltage Win is applied to the base of
A first reference voltage v is applied to the base of the second transistor Q2.
TH is applied. Furthermore, the emitters of the PNP type second transistor Q3 and fourth transistor Q4 are connected to each other to form a second differential pair, and a constant current is applied between the emitter connection point and the VaC power supply. A second constant current source 2 is connected for flowing the goose. The input voltage vin is applied to the base of the third transistor Qs, and the second reference voltage v? is applied to the base of the fourth transistor Q4. L is applied. - On the other hand, the NPN type fifth transistor Qs and the sixth transistor Q6 have their bases connected to each other, their respective emitters are grounded, and the collector and base of the fifth transistor Q5 are connected to each other. These form a current mirror circuit CM. This current mirror circuit CM includes the first differential pair of transistors Q1#Q! and a common load for the second differential pair transistor Qs=Qa, and the collector of the fifth transistor Qs on the next side is connected to the first
The collector of the sixth transistor Q6 on the secondary side is connected to the collectors of the second transistor Q2 and the fourth transistor Q4. There is. Then, a cover is output to the collector of the transistor Q4,
7A circuit, for example, a seventh transistor Q7 of NPN type
The base of this transistor Qt is connected, the emitter of this transistor Qt is grounded, and a constant current I is connected between the collector and the vec power supply.
A third constant current source 3 for supplying 3 is connected, and the collector of the third constant current source 3 is connected to the output terminal 4. Further, this collector is connected to the NPN type eighth transistor Qs (D base) via the resistor R1, and this transistor Qs
The emitter of transistor No. 8 is grounded, and the collector thereof is connected to the emitter connection point of the second differential pair transistors Qs and Qa.

In the above circuit, the transistor Q forming the second differential pair
The emitter area ratio of s=Qa is 1:n (for example, 1:2)
The constant current of the constant current source 1 for the first differential pair 1 and the constant current of the constant current source 2 for the second differential pair! The ratio is l:n+1 (1:3 in this example).Is=3I
It is set to t.

Next, the operation of the voltage comparison circuit with hysteresis constructed as described above when, for example, a sinusoidal input voltage V1n is applied will be described with reference to FIG. The input voltage level is the first
The reference voltage vT! In period A, which is larger than I, Ia
l differential pair transistors Qs-Qs are each correspondingly turned off,
If not in the on state, the second transistor Qz K constant current! flows. Also, when the above-mentioned period A begins, the second differential pair transistor Q! =94 remain in the off state for a period to be described later.

Then, when period A begins, no current flows through the transistor Qs on the primary side of the current mirror circuit CM, no current flows through the transistor Q6 on the secondary side, and no current flows from the second transistor Q8. The seventh transistor Q7 is turned on by the current ■1, and the output terminal 4 is set to the ground potential (“0
#level). As a result, the eighth transistor Qs is turned off, the fourth transistor Q4 is turned on, and a constant current I3 from the constant current source 2 of jD and #E2 flows.

Next, the input voltage level decreases and the first reference voltage V
TH and second reference voltage v? During period B, which is midway between the first differential pair transistor QtpQ* and the first differential pair transistor QtpQ*, the first differential pair transistor QtpQ* is neither on nor off, and a constant current Il flows through the first transistor Q1. On the other hand, the second differential pair
The current mirror circuit CM's primary side transistor QsK flows through the current Il from the first transistor Q1, and the secondary side transistor Qs K is also a current! ! flows. Therefore, among the current I * (=31t) flowing through the fourth transistor Q4, the current 1 flowing through the secondary side transistor Q of the current mirror circuit CM
Since the current 2ftk is different from 1, the seventh transistor Qt remains turned on, so that the eighth transistor Qa is in the off state.

Furthermore, during the period C when the input voltage level decreases and becomes smaller than the second reference voltage VTL, the tenth differential pair transistor QttQ* remains in the on and off states, respectively, and the second Transistor Qs in the differential pair is in the on state, and this third transistor Q3 has a second
11 of the current I z (=3It) from the constant current source 2 flows. Therefore, the current 11 from the first transistor Q1 and the current ■! from the third transistor Q3 flow to the primary side transistor Qg of the current mirror circuit CM. , the current from the fourth transistor Q4 flows through the secondary side transistor Q6, and the seventh transistor Q7 is turned off because the base current necessary for turning it on does not flow. Output terminal 4 is at vcc potential (@
1# level). As a result, the eighth transistor Q8 is turned on by the constant current m I s, and this transistor Q8 is turned on as the electric current 2 from the second constant current source 2 flows, and the transistor Qs=Q4.・When the above period C comes, the third
The current Itt211 flows through the transistor Q3 and the fourth transistor Q4 corresponding to the emitter area ratio of 1:2, and the base-emitter voltages are equal, so the input voltage Vin and the second Reference voltage V
Good comparison accuracy with TL.

Next, the input voltage level increases to the second reference voltage V
TL and the first reference voltage vTI! During the intermediate period between , the second differential pair transistors Qs=Qa each remain in the off state, and the first differential pair transistor QseQs remains in the on and off states. Therefore, the primary side transistor Qs of the current mirror circuit CM
The electric current 1 from the first transistor Q1 flows through the transistor Q1, but no current flows through the secondary side transistor Q6, and the base current necessary for turning on the seventh transistor Q7 does not flow, so it remains in the off state. Yes, eighth transistor Q8
is driven by the constant current construction 3 and remains in the on state, and the 3rd. The fourth transistors Qs and Qa each remain in the off state.

That is, in the voltage comparator circuit with hysteresis,
It is possible to compare voltages having a hysteresis width corresponding to the difference between the first reference voltage VTH and the second reference voltage VTL, and each of the reference voltages VTH mentioned above.

It is possible to freely set the VTL independently.

In addition, in the above circuit, the reference voltages vT1i, vHL
(the second and fourth transistors Q2゜Q4
Since the input impedance of the reference voltage source (base) is high, a reference voltage source with high input impedance can be used, and the voltage range that can be set as the reference voltage vTH1VTL is wide.

In addition, by appropriately setting the current ratio between the first constant current source 1 and the second constant current source 2 and the emitter area ratio of the second differential pair transistor Q3=Q4, the second reference voltage can be adjusted. The accuracy of comparison between VTL and input voltage Vin is improved. Moreover, in the above voltage comparison circuit, if each current source is realized by one transistor, the number of transistors used is 11, the number of resistors used is 1, and the total number of circuit elements used is 12. This is extremely simplified compared to the conventional example.

FIG. 3 shows a modification of the circuit shown in FIG. 1. The differences from the circuit shown in FIG. 1 are (1) a resistor R, t R8sR4 between the input terminal 5 and the ground are connected in series,
(2) The connection point of the resistor R1pR3 is connected to the base of the first transistor Q1, and the connection point of the resistor R3tR4 is connected to the base of the third transistor Q3. The bases of the transistors Q4 are commonly connected and the reference voltage v8 is applied thereto;
(3) Seventh transistor Q as output cover and F circuit
A fourth constant current source connects the base of an NPN type ninth transistor Q9 to the collector of 7, grounds the emitter of this transistor Q-, and flows a constant current I4 between the collector and the VCE power supply terminal. 6 is connected, and the collector is connected to one end of the resistor R1.

Since the other parts are the same as in FIG. 1, the same parts as in FIG. 1 are given the same reference numerals.

In the above circuit, the input voltage Vln of the input terminal 5 is the first reference voltage v? Transistor Ql during a period larger than H
-Qs are each turned off, then vT1 is expressed as follows. Also, during a period when the input voltage Vin at the input terminal 60 is smaller than the second reference voltage VTL, the transistor Qx
If yQs are each turned on, the above v
? L is represented by .

The operation of the circuit shown in FIG. 3 is performed in accordance with the operation of the previous embodiment, but by adding the ninth transistor Q9, transistors Q7 and Q8 are in the same switch state, and the level of the output voltage vout is is V in the above example. It is in reverse phase with ut.

〔Effect of the invention〕

As described above, according to the voltage comparison circuit with hysteresis of the present invention, the number of circuit elements used can be significantly reduced, the voltages at both ends of the hysteresis width can be set independently, and the hysteresis width can be set freely.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the voltage comparison circuit with hysteresis of the present invention, FIG. 2 is a signal waveform diagram shown to explain the operation of the circuit of FIG. 1, and FIG. FIG. 4 is a circuit diagram showing a conventional voltage comparison circuit with hysteresis, and FIG. 5 is a signal waveform diagram showing the circuit operation of FIG. 4. 1-3, 6...constant current source, 4...output terminal, 5...
・Input terminal, Q1-Q9...transistor, R1-R
4...Resistance, CM...Current mirror circuit.

Claims (3)

[Claims] (1) Transistors Q_1 and Q_2 whose emitters are connected together to form a first differential pair, and transistors Q_1 and Q_2 whose emitters are connected to each other to form a second differential pair.
2, a current mirror circuit connected as a load to the collectors of the transistors Q_3 and Q_4, and an output buffer circuit whose input is the collector potential of the transistor Q_4. , a transistor Q_8 to which the output potential of the output buffer circuit is applied as a base input and connected between the emitter interconnection point of the second differential pair transistors Q_3 and Q_4 and a predetermined potential end; The same voltage is applied to the bases of the transistors in each of the first differential pair and the second differential pair, and voltages at different levels are applied to the bases of the other transistors. A voltage comparator circuit with hysteresis. (2) Hysteresis according to claim 1, wherein the same voltage is an input voltage, and the voltages at different levels are a first reference voltage V_T_H and a second reference voltage V_T_L. voltage comparator circuit. (3) The voltage comparison with hysteresis according to claim 1, wherein the same voltage is a reference voltage V_s, and the voltages at different levels are generated by dividing an input voltage. circuit.