JPS61212017A - Solid-phase epitaxial growth method for nisi2 film - Google Patents
Solid-phase epitaxial growth method for nisi2 filmInfo
- Publication number
- JPS61212017A JPS61212017A JP5160385A JP5160385A JPS61212017A JP S61212017 A JPS61212017 A JP S61212017A JP 5160385 A JP5160385 A JP 5160385A JP 5160385 A JP5160385 A JP 5160385A JP S61212017 A JPS61212017 A JP S61212017A
- Authority
- JP
- Japan
- Prior art keywords
- film
- nisi2
- substrate
- epitaxial growth
- phase epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000007790 solid phase Substances 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000013078 crystal Substances 0.000 claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 229910012990 NiSi2 Inorganic materials 0.000 abstract description 21
- 238000007740 vapor deposition Methods 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 3
- 239000012071 phase Substances 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 7
- 238000004458 analytical method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000007665 sagging Methods 0.000 description 2
- 241000356545 Beana Species 0.000 description 1
- 229910018098 Ni-Si Inorganic materials 0.000 description 1
- 229910018529 Ni—Si Inorganic materials 0.000 description 1
- 238000010549 co-Evaporation Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Electrodes Of Semiconductors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はNiSi2膜の形成法に関する。特に良質の結
晶性を有するN15il単結晶膜を容易に形成でき、同
時に、Si基板中へNiSi2からの不純物の拡散の影
響が少いという、半導体素子に好適なNiSi2膜の固
相エピタキシャル成長法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for forming a NiSi2 film. In particular, the present invention relates to a solid-phase epitaxial growth method for NiSi2 films suitable for semiconductor devices, in which an N15il single crystal film with good crystallinity can be easily formed, and at the same time, the influence of impurity diffusion from NiSi2 into a Si substrate is small.
従来、Si単結晶の上にNiSi2単結晶膜をエピタキ
シャル成長する方法として、Ni膜とSi基板とを反応
させる固相エピタキシャル(たとえばS、5aitoh
et al、 Japan J A P
、、 20 (1981)。Conventionally, as a method for epitaxially growing a NiSi2 single crystal film on a Si single crystal, solid phase epitaxial growth (for example, S, 5aitoh
et al, Japan JAPA
, 20 (1981).
1649)と、Si基板上にNiとSiの蒸発原子を同
時に照射する同時蒸着法(たとえばJ、C,Beana
t al、、 A P L、、 37 (1980)、
643〜)が知られていた。同相エピタキシャル法で
は形成法が容易であるが1反応が拡散を伴ったものであ
り、Si中にNiが拡散したり、膜の表面のモルホロジ
ー(morpholgy)が悪いという欠点を有した。1649) and the simultaneous evaporation method (for example, J, C, Beana
tal, APL, 37 (1980),
643~) was known. Although the in-phase epitaxial method is easy to form, one reaction involves diffusion, and it has drawbacks such as diffusion of Ni into Si and poor morphology of the surface of the film.
一方、同時蒸着法は、良好な結晶性の膜ができ1表面の
モルホロジーも良く、Si基板中へのNi原子の拡散も
少いという長所を有しているが、膜の形成方法、特にS
iとNiの比を化学量論組成に時間的に一定に保つのが
困難であった。これが実用上の難点である。On the other hand, the co-evaporation method has the advantage of producing a film with good crystallinity, good morphology on the surface, and less diffusion of Ni atoms into the Si substrate.
It was difficult to keep the ratio of i and Ni constant over time to the stoichiometric composition. This is a practical difficulty.
本発明の目的は、NiSi2膜の形成法において。 The object of the present invention is to provide a method for forming a NiSi2 film.
従来の固相エピタキシャル法並みの容易さと、同時蒸着
法並みの良質の結晶性と、Si基板への影響を少くする
ような、固相エピタキシャル法を提供することにある。The object of the present invention is to provide a solid phase epitaxial method that is as easy as the conventional solid phase epitaxial method, has good crystallinity comparable to that of the simultaneous vapor deposition method, and has less influence on the Si substrate.
従来の同相エピタキシャル法の欠点は、下地のSi基板
との反応により核形成による膜の成長が生じたり、また
SiとNiの拡散反応が必須であるため、Si基板中に
Ni原子が不純物として固溶されてしまうということで
あった。したがって、同時蒸着法と同様にSi基板と同
相反応を生じさせないようにし、エピタキシャル成長は
下地のSi基板に従うようにしてやれば、上記の固相エ
ピタキシャル法の欠点は解消される。そのためにSi基
板上に下地との反応が生じにくい350℃以下の基板温
度で望ましくは25〜200℃にて、NiSi2の組成
比になるようにSiとNiの多層膜を形成する。安定な
NiSi2相が形成されていない時は、350℃以上、
特に450℃以上の基板温度では、下地のSi基板と上
に形成した膜との反応が顕著になるので望ましくない、
多層膜の全体としての組成はSiとの格子のミスマツチ
が少く、容易にエピタキシャル成長が生じ、しかも、S
iとの共存相として安定なNiSi2になるようにした
。この時NiとSiとの組成比がSi/N1)2では、
エピタキシャル成長させた時にNiSi2膜に余分のS
iが析出した状態になり望ましくない、またSi/Ni
>1.8ではNiSi2膜を形成する際不足のSi原子
をおぎなうため下地からSi[子が拡散してくるが、そ
れに伴い、NiSi2膜の表面モルホロジーが悪くなり
、望ましくない。200℃以下で形成したSiとNiの
多層膜は、各層が30〜300人と非常に薄く、また基
板の単結晶基板に比べ、多量の格子欠陥を含むので、拡
散しやすく100℃以下でも一部NiSi2が形成され
ており、350℃30分という低温でのアニールでも下
地のSiと反応することなく容易に均一なNi51g相
となる。このNiSi2を形成するアニール温度は上述
の如くSi基板との反応を防ぐという観点から、350
〜450℃である。なお、この多層膜からNiSi2膜
を形成する工程は、省略してもよい。The disadvantages of the conventional in-phase epitaxial method are that film growth occurs due to nucleation due to reaction with the underlying Si substrate, and because a diffusion reaction between Si and Ni is essential, Ni atoms may become fixed as impurities in the Si substrate. It was said that it would be dissolved. Therefore, similarly to the simultaneous vapor deposition method, if the in-phase reaction with the Si substrate is prevented and the epitaxial growth is made to follow the underlying Si substrate, the above-mentioned drawbacks of the solid phase epitaxial method can be overcome. For this purpose, a multilayer film of Si and Ni is formed on a Si substrate at a substrate temperature of 350° C. or lower, preferably 25 to 200° C., where reaction with the underlying layer is less likely to occur, so as to have a composition ratio of NiSi2. When stable NiSi2 phase is not formed, the temperature is 350℃ or higher,
In particular, a substrate temperature of 450°C or higher is undesirable because the reaction between the underlying Si substrate and the film formed thereon becomes significant.
The overall composition of the multilayer film has little lattice mismatch with Si, and epitaxial growth occurs easily.
NiSi2 was made to be stable as a coexisting phase with i. At this time, when the composition ratio of Ni and Si is Si/N1)2,
Excess S is added to the NiSi2 film during epitaxial growth.
i becomes precipitated, which is undesirable, and Si/Ni
>1.8, Si atoms diffuse from the underlying layer to cover the insufficient Si atoms when forming the NiSi2 film, but this is undesirable because the surface morphology of the NiSi2 film deteriorates. Multilayer films of Si and Ni formed at temperatures below 200°C are extremely thin, with each layer having 30 to 300 layers, and contain a large number of lattice defects compared to single crystal substrates, so they are easily diffused and do not remain stable even below 100°C. A uniform Ni51g phase is formed, and even by annealing at a low temperature of 350° C. for 30 minutes, it easily becomes a uniform Ni51g phase without reacting with the underlying Si. The annealing temperature for forming this NiSi2 is 350°C from the viewpoint of preventing reaction with the Si substrate as described above.
~450°C. Note that the step of forming the NiSi2 film from this multilayer film may be omitted.
次にNiSi2膜あるいはNi−Si多層膜を、下地S
i単結晶基板に対し、固相エピタキシャル成長させるた
め、350℃〜750℃に基板を加熱した。単結晶成長
は、Si基板表面が清浄であれば、350℃でも生じる
が、結晶性は悪い。Next, apply a NiSi2 film or a Ni-Si multilayer film to the base layer S.
i A single crystal substrate was heated to 350° C. to 750° C. for solid phase epitaxial growth. Single crystal growth can occur even at 350° C. if the Si substrate surface is clean, but the crystallinity is poor.
500〜650℃にて、結晶性も良好で、また。Good crystallinity at 500-650°C.
表面の凹凸も原子層オーダーの非常に平滑な単結晶膜を
得ることができる。650℃以上、特に750℃に加熱
すると、結晶性は良いが、表面の凹凸が大きくなり、極
端な場合は、NiSi2膜に穴がおいて、下地のSi基
板が露出するようになる。したがって、500〜650
℃の基板加熱温度が同相エピタキシャル成長させる最適
の温度領域である。A very smooth single crystal film with surface irregularities on the order of atomic layers can be obtained. When heated to 650° C. or higher, especially 750° C., the crystallinity is good, but the surface becomes rough, and in extreme cases, holes are formed in the NiSi2 film, exposing the underlying Si substrate. Therefore, 500-650
A substrate heating temperature of °C is the optimum temperature range for in-phase epitaxial growth.
以下本発明の詳細を実施例により説明する。 The details of the present invention will be explained below with reference to Examples.
実施例1゜
Si (111)単結晶基板を分子線成長装置に挿入し
、10−”torr台の超高真空中にて低温サーマルエ
ツチング法により表面の清浄化を行った。Example 1 A Si (111) single crystal substrate was inserted into a molecular beam growth apparatus, and the surface was cleaned by low-temperature thermal etching in an ultra-high vacuum of 10-'' torr.
次に基板温度を室温に下げ、Si層とNi層を各々17
5人、50λの周期で4層ずつ交互に形成した。その後
、30分間600℃に基板を上げた。Next, the substrate temperature was lowered to room temperature, and the Si layer and Ni layer were each
Five people alternately formed four layers at a period of 50λ. Thereafter, the substrate was heated to 600° C. for 30 minutes.
反射電子線回折により結晶性を判定したところ単結晶パ
ターンが得られ、下地のSi基板(ni)面に対して、
同様に(111)面のエピタキシャル成長が生じている
ことが判った。次にオージェ電子分光により分析したと
ころ、NiSi2に特有のラインシェープのS i t
、vvピークが得られ。When the crystallinity was determined by reflected electron beam diffraction, a single crystal pattern was obtained, and with respect to the underlying Si substrate (ni) surface,
Similarly, it was found that epitaxial growth of the (111) plane occurred. Next, when analyzed by Auger electron spectroscopy, it was found that the line shape Si t peculiar to NiSi2
, vv peaks are obtained.
N15izが生成していることが判った。断面を観察し
たところ通常の固相エピタキシャル法の場合とは異なり
、第1図(b)に示すように、下地のSi基板を食って
N15izが成長しているということはなかった。なお
、第1図(a)はSi基板2上にNi層を形成した状態
を示す断面図、第1図(b)はこれを固相エピタキシャ
ル成長後の断面図である。It was found that N15iz was generated. When the cross section was observed, unlike in the case of the normal solid phase epitaxial method, as shown in FIG. 1(b), there was no growth of N15iz eating into the underlying Si substrate. Note that FIG. 1(a) is a cross-sectional view showing a Ni layer formed on a Si substrate 2, and FIG. 1(b) is a cross-sectional view of this after solid phase epitaxial growth.
一方、第2図(a)は本発明の方法を用いたもので、N
i層(1)とSi層(3)を交互にSi基板(2)上に
積層した状態を示す。第2図(b)はこの状態で同相エ
ピタキシャル成長を施こした状態である。また、表面の
モルホロジー(molphology)も、ノマルスキ
ー型光学顕微鏡でみても何の構造もみられない程、鏡面
状態であった。深さ方向に、IMA分析を行ったところ
第3図シこ示すように1通常の固相エピタキシャル法の
場合、上のように界面のダレは2000人であり、一方
1本発明の同相エピタキシャル抜工の場合は、界面のダ
レは500人程定形あった。このダレは、分析のイオン
スパッタに伴うイオン衝撃によるダレの程度であり、本
発明による方法では、Si基板中へN1J7i子が拡散
するのは非常に少いことが明らかである。On the other hand, FIG. 2(a) shows the result using the method of the present invention, with N
A state in which i-layers (1) and Si layers (3) are alternately stacked on a Si substrate (2) is shown. FIG. 2(b) shows a state in which in-phase epitaxial growth is performed in this state. Furthermore, the surface morphology was so mirror-like that no structure could be seen even when viewed with a Nomarski optical microscope. When IMA analysis was performed in the depth direction, as shown in Figure 3, in the case of the normal solid-phase epitaxial method, the sag at the interface was 2000 as shown above, whereas in the case of the in-phase epitaxial method of the present invention, the sag was 2000. In the case of engineering, there were about 500 regular sag marks on the interface. This sagging is the extent of sagging due to ion bombardment accompanying ion sputtering in analysis, and it is clear that in the method according to the present invention, the diffusion of N1J7i molecules into the Si substrate is extremely small.
以上1本発明によれば、 (1) Si基板からSi原子を食うことなしに。 According to the above first invention, (1) Without eating Si atoms from the Si substrate.
しかも従来の固相エピタキシャル法と同程度の容易さで
、同時蒸着法で得られる膜質と同等のものが形成できる
。Moreover, it is possible to form a film with the same quality as that obtained by simultaneous vapor deposition with the same degree of ease as the conventional solid phase epitaxial method.
(2)シかも半導体層へNi原子の拡散が少いという特
徴を有している。(2) It is also characterized by less diffusion of Ni atoms into the semiconductor layer.
半導体に対しN15izを使用できるという極めて大き
い効用がある。There is an extremely large effect that N15iz can be used for semiconductors.
第1図(a)、 (b)は従来の固相エピタキシャル法
による成長層の断面図で、同(a)は基板にNi膜形成
後の断面図、同(b)はこれを固相エピタキシャル成長
した後の断面図である。
第2図(a)、 (b)は本発明による固相エピタキシ
ャル法による成長層の断面図で、同(a)はN15iz
膜の多層膜形成後の断面図、同(b)はこれを固相エピ
タキシャル成長した後の断面図である。
第3図は二次イオン質量分析によるNiの深さ方向分析
結果を示す図である。
1・・・Ni膜、2・・・Si基板、3・・・Si膜。
4・・・NiSi2膜。Figures 1(a) and 1(b) are cross-sectional views of a layer grown by conventional solid-phase epitaxial method, in which (a) is a cross-sectional view after forming a Ni film on a substrate, and (b) is a cross-sectional view of a layer grown by solid-phase epitaxial growth. FIG. FIGS. 2(a) and 2(b) are cross-sectional views of a layer grown by the solid phase epitaxial method according to the present invention;
A cross-sectional view of the film after the multilayer film is formed, and (b) is a cross-sectional view of the film after solid-phase epitaxial growth. FIG. 3 is a diagram showing the results of depth direction analysis of Ni by secondary ion mass spectrometry. 1...Ni film, 2...Si substrate, 3...Si film. 4...NiSi2 film.
Claims (1)
度で、30〜300Åの厚さで所望の周期でNiおよび
Si膜を交互に当該積層膜全体の組成比が▲数式、化学
式、表等があります▼になるように積層膜を形成した後
、350〜750℃に加熱してNiSi_2膜を形成す
ることによりNiSi_2単結晶膜をエピタキシャル成
長させることを特徴とするNiSi_2膜の固相エピタ
キシャル成長法。 2、前記Si膜とNi膜の積層膜をアニールによってN
iSi_2膜とせしめ、次いでNiSi_2単結晶膜を
エピタキシャル成長させることを特徴とする特許請求の
範囲第1項記載のNiSi_2膜の固相エピタキシャル
成長法。[Claims] 1. On a Si single crystal substrate, at a substrate temperature of 350°C or less, Ni and Si films are alternately formed at a desired periodicity with a thickness of 30 to 300 Å, and the composition ratio of the entire laminated film is changed. NiSi_2 is characterized by epitaxially growing a NiSi_2 single crystal film by forming a laminated film so that ▲ is ▼ and then heating it to 350 to 750°C to form a NiSi_2 film. Solid-phase epitaxial growth of films. 2. The laminated film of the Si film and Ni film is annealed to
A solid phase epitaxial growth method for a NiSi_2 film according to claim 1, characterized in that an iSi_2 film is formed and then a NiSi_2 single crystal film is epitaxially grown.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5160385A JPS61212017A (en) | 1985-03-16 | 1985-03-16 | Solid-phase epitaxial growth method for nisi2 film |
US07/110,580 US5047111A (en) | 1985-03-16 | 1987-10-16 | Method of forming a metal silicide film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5160385A JPS61212017A (en) | 1985-03-16 | 1985-03-16 | Solid-phase epitaxial growth method for nisi2 film |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61212017A true JPS61212017A (en) | 1986-09-20 |
JPH0511411B2 JPH0511411B2 (en) | 1993-02-15 |
Family
ID=12891473
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5160385A Granted JPS61212017A (en) | 1985-03-16 | 1985-03-16 | Solid-phase epitaxial growth method for nisi2 film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61212017A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004070804A1 (en) * | 2003-02-07 | 2004-08-19 | Nec Corporation | Method for forming nickel silicide film, method for manufacturing semiconductor device, and method for etching nickel silicide |
-
1985
- 1985-03-16 JP JP5160385A patent/JPS61212017A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004070804A1 (en) * | 2003-02-07 | 2004-08-19 | Nec Corporation | Method for forming nickel silicide film, method for manufacturing semiconductor device, and method for etching nickel silicide |
JPWO2004070804A1 (en) * | 2003-02-07 | 2006-05-25 | 日本電気株式会社 | Nickel silicide film forming method, semiconductor device manufacturing method, and nickel silicide film etching method |
JP4509026B2 (en) * | 2003-02-07 | 2010-07-21 | 日本電気株式会社 | Nickel silicide film forming method, semiconductor device manufacturing method, and nickel silicide film etching method |
Also Published As
Publication number | Publication date |
---|---|
JPH0511411B2 (en) | 1993-02-15 |
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