JPH0342818A - Compound semiconductor device and its manufacture - Google Patents

Compound semiconductor device and its manufacture

Info

Publication number
JPH0342818A
JPH0342818A JP17832889A JP17832889A JPH0342818A JP H0342818 A JPH0342818 A JP H0342818A JP 17832889 A JP17832889 A JP 17832889A JP 17832889 A JP17832889 A JP 17832889A JP H0342818 A JPH0342818 A JP H0342818A
Authority
JP
Japan
Prior art keywords
substrate
gaas
compound semiconductor
layer
porous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17832889A
Other languages
Japanese (ja)
Inventor
Taketaka Kohama
剛孝 小濱
Yoshiaki Kadota
門田 好晃
Tokuro Omachi
大町 督郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP17832889A priority Critical patent/JPH0342818A/en
Publication of JPH0342818A publication Critical patent/JPH0342818A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent generation of warpage and crack of a compound semiconductor by forming a porous layer on an Si substrate and by enabling Si to grow on it. CONSTITUTION:A porous layer 2 is formed on the surface of an Si substrate 1 and then the substrate is subjected to Si homoepitaxial growth 3 by the organic metal vapor growth method. Then, growing Si and then an As coated surface on Si, a GaAs low-temperature layer 4 is formed and then GaAs growth is performed successively, thus achieving improved surface flatness and crystallinity as compared with a GaAs epitaxial layer which is directly allowed to grow on the surface of Si substrate. Also, no cracks occur even if the film thickness of GaAs exceeds 4mum.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、Si基板上に従来技術のものと比較して、基
板の反り及びクラックを極めて低く抑えた高品質の化合
物半導体装置とその製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention provides a high-quality compound semiconductor device on a Si substrate in which warpage and cracking of the substrate are extremely suppressed compared to those of the prior art, and its manufacture. It is about the method.

(従来の技術) GaAsに代表される■−■族化合物半導体は、現在主
流であるSlと比較して直接遷移であり高い電子移動度
を有するため、高速デバイス、光デバイスに利用されて
いる。しかしながら、GaAsに代表される上記■−v
族化合物半導体は、W1械的に脆く、大面積が得られな
いため高価格である。このような問題を解決するため、
安価で機械的熱的特性の優れたSI基板上に上記■−■
族化合物半導体をエピタキシャル成長させ、そこにデバ
イスを形成する方法が試みられている。
(Prior Art) ■-■ group compound semiconductors represented by GaAs are used in high-speed devices and optical devices because they are direct transitions and have higher electron mobility than Sl, which is currently the mainstream. However, the above ■-v represented by GaAs
W1 group compound semiconductors are mechanically fragile and cannot be formed over a large area, so they are expensive. In order to solve such problems,
The above ■-■ is mounted on an SI substrate that is inexpensive and has excellent mechanical and thermal properties.
Attempts have been made to epitaxially grow group compound semiconductors and form devices thereon.

(発明が解決しようとする課題) しかしながら、上記GaAsを例にとると、Siと格子
定数で約4%、熱膨張係数について約2倍の不整合があ
るため、Si基板上には直接成長しがたい。
(Problem to be Solved by the Invention) However, taking the above-mentioned GaAs as an example, it has a mismatch with Si of about 4% in lattice constant and about twice the coefficient of thermal expansion, so it cannot be grown directly on a Si substrate. It's tough.

この問題を解決するため現在では、上記Si基板上に成
長温度300〜400℃、数100人の低温GaAs層
を形成後、成長温度600〜800°CでGaAs層を
形成する二段階成長法が行われ、良好な結晶性が得られ
ている。また、さらに上記方法に加えて熱アニ−リング
を行うことによって、結晶性1表面平坦性もより一層向
上したGaAsエピタキシャル層をSi基板上に形成可
能にしている。
To solve this problem, a two-step growth method is currently available in which several hundred low-temperature GaAs layers are formed on the Si substrate at a growth temperature of 300 to 400°C, and then a GaAs layer is formed at a growth temperature of 600 to 800°C. Good crystallinity has been obtained. Furthermore, by performing thermal annealing in addition to the above method, it is possible to form a GaAs epitaxial layer with even further improved crystallinity and surface flatness on the Si substrate.

しかしながら、上記Siと上記GaAsとの間には前述
したように約2倍の熱膨張係数差が存在するため、上記
GaAs威長後の室温への冷却過程において非常に大き
な引っ張り応力が働く、このため上記GaAsエピタキ
シャル層は上に凸の反った状態になり、膜厚が3/!a
を越えるとクラックが発生するという問題があった。
However, as mentioned above, there is a difference in thermal expansion coefficient of approximately twice that between the Si and the GaAs, so a very large tensile stress acts during the cooling process to room temperature after the GaAs is heated. The GaAs epitaxial layer has an upwardly convex curved shape, and the film thickness is 3/! a
There was a problem that cracks would occur if the temperature was exceeded.

(発明の目的) 本発明は上記の欠点を改善するために提案されたもので
、その目的は、Si基板上に■−V族化合物半導体を形
成するに当たって、該1[[−V族化合物半導体に発生
する反り、クラックを従来法と比較して著しく抑えた化
合物半導体装置とその製造方法を提供することにある。
(Objective of the Invention) The present invention was proposed to improve the above-mentioned drawbacks. It is an object of the present invention to provide a compound semiconductor device and a method for manufacturing the same in which warping and cracking occurring in the semiconductor device are significantly suppressed compared to conventional methods.

(課題を解決するための手段) 上記目的を達成するために、本発明者等は種々の実験を
行ってきた結果、上記Si基板表面を多孔賀状にし、前
記多孔質Si表面上にSiをホモエピタキシャル成長し
、前記基板上にGaAsをエピタキシャル成長すること
によって、基板の反りを大幅に低減し、クランクについ
ても従来法ではGaAs成長¥が3μ詭を越えると発生
していたが、本発明によると3nを越えてもクランクが
発生しなかったことを発見した。
(Means for Solving the Problem) In order to achieve the above object, the present inventors have conducted various experiments and found that the surface of the Si substrate is made into a porous shape and Si is homogenized on the porous Si surface. By epitaxially growing GaAs on the substrate, the warpage of the substrate can be significantly reduced, and cranks also occur when the GaAs growth exceeds 3μ in the conventional method, but according to the present invention, 3n can be reduced. I discovered that the crank did not occur even when I crossed it.

上記の目的を達成するため、本発明はSi基板と、前記
Si基板上に形成された多孔質層と、前記多孔質層上に
形成されたホモエピタキシャル層と、前記ホモエピタキ
シャル層上に形成された化合物半導体層とを備えること
を特徴とする化合物半導体装置を発明の要旨とするもの
である。
In order to achieve the above object, the present invention includes a Si substrate, a porous layer formed on the Si substrate, a homoepitaxial layer formed on the porous layer, and a porous layer formed on the homoepitaxial layer. The gist of the invention is a compound semiconductor device characterized by comprising a compound semiconductor layer.

さらに、本発明はSi基板上に化合物半導体を形成する
工程において、前記Si基板表面に多孔質Siを形成す
る工程と、前記多孔質Si表面上にSiをエピタキシャ
ル成長せしめる工程とを具備することを特徴とする化合
物半導体装置の製造方法を発明の要旨とするものである
Furthermore, the present invention is characterized in that the step of forming a compound semiconductor on a Si substrate includes the steps of forming porous Si on the surface of the Si substrate, and growing Si epitaxially on the surface of the porous Si. The gist of the invention is a method for manufacturing a compound semiconductor device.

(作用) 本発明はSi基板表面をl孔質状にし、この表面上にS
iをホモエピタキシャル成長し、さらにこの上にGaA
sをエピタキシャル成長を行っているため、基板の反り
を大幅に低減することができるものである。
(Function) The present invention makes the surface of the Si substrate porous and deposits S on this surface.
i is homoepitaxially grown, and GaA is further grown on top of this.
Since s is epitaxially grown, the warpage of the substrate can be significantly reduced.

(実施例) 次に本発明の実施例について説明する。なお、実施例は
一つの例示であって、本発明の精神を逸脱しない範囲で
、種々の変更あるいは改良を行いうろことは言うまでも
ない。
(Example) Next, an example of the present invention will be described. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

以下、有機金属気相成長法(以下MOCVD法)を用い
て、Si基板上にGaAsをエピタキシャル成長させる
場合を例に、本発明の実施例について説明する。
Embodiments of the present invention will be described below, taking as an example a case where GaAs is epitaxially grown on a Si substrate using a metal organic chemical vapor deposition method (hereinafter referred to as MOCVD method).

集1図は本発明によるSi基板上に形成したGaAsエ
ピタキシャル層の断面図を示す0図において、1はSi
基板、2は多孔質状Si、 3はSiホモエピタキシャ
ル層、4はGaAsエピタキシャル層を示す。
Figure 1 is a cross-sectional view of a GaAs epitaxial layer formed on a Si substrate according to the present invention.
2 is a porous Si substrate, 3 is a Si homoepitaxial layer, and 4 is a GaAs epitaxial layer.

基板としては、面方位が<100>かられずかにずれた
、抵抗率0.01Ωam以下の厚さ300n、P型Sl
基板を用いた。 Si基板表面を多孔質状にするために
、通常の洗浄後HF溶液中で陽極化成を電流密度0.1
A/c+w” 、 20分間行い、厚さ1.6nの多孔
質層を形成した。その後基板を上記MOCVD装置に導
入し、H8雰囲気中で1000’C110分の基板加熱
を行い、Si基板の表面クリーニングを行った。
The substrate is a P-type Sl with a resistivity of 0.01 Ωam or less and a thickness of 300 nm, with a plane orientation slightly deviated from <100>.
A substrate was used. In order to make the Si substrate surface porous, anodization was carried out in an HF solution at a current density of 0.1 after normal cleaning.
A/c+w'' for 20 minutes to form a porous layer with a thickness of 1.6 nm.Then, the substrate was introduced into the above MOCVD apparatus, and the substrate was heated at 1000'C for 110 minutes in an H8 atmosphere to coat the surface of the Si substrate. I did some cleaning.

そして基板温度を900°Cに設定し、5I84をリア
クターに導入し、SlをInホモエピタキシャル成長を
行った。モしてSi戒長後AsH,を導入し、Si上に
As被覆面を形成した後、基板温度を400℃に設定し
GaAs低温層を150人形威し、引続き基板温度を7
50℃に設定しGaAs成長を行った。
Then, the substrate temperature was set at 900°C, 5I84 was introduced into the reactor, and In homoepitaxial growth of Sl was performed. After introducing Si and forming an As-coated surface on the Si, the substrate temperature was set at 400°C and a GaAs low-temperature layer was applied for 150 times, and then the substrate temperature was lowered to 70°C.
GaAs growth was performed at a temperature of 50°C.

上記工程に従って製造したSi基板上のGaAsエピタ
キシャル層について、表面平坦性、及びX線二結晶法等
による結晶性評価を行った結果、従来法、すなわちSI
基板表面に直接成長したGaAsエピタキシャル層と比
較しても、遜色のないことがH1認された0次に基板の
反りを調べるため、フラットネステスターを用いてGa
As1ll厚2nの基板曲率を測定した。第1表にその
結果を示す、従来法ではフラットネステスターによる曲
率が6.4mであるのに対して、本発明ではフラットネ
ステスターによる曲率が15mとなり大幅に反りが低減
されているのが分かる。また、従来法ではGaAsの膜
厚が3nを越えたところで、クラックが発生し始めたが
、本発明によると4μを越えてもクラックは発生しなか
った。
As a result of evaluating the surface flatness and crystallinity of the GaAs epitaxial layer on the Si substrate manufactured according to the above process by the X-ray double crystal method, it was found that
In order to investigate the warpage of the zero-order substrate, which was found to be comparable to a GaAs epitaxial layer grown directly on the substrate surface, a GaAs epitaxial layer was grown using a flatness tester.
The curvature of a substrate of As1ll thickness 2n was measured. The results are shown in Table 1. In the conventional method, the curvature measured by the flatness tester was 6.4 m, whereas in the present invention, the curvature measured by the flatness tester was 15 m, which shows that the warpage is significantly reduced. . Furthermore, in the conventional method, cracks began to occur when the GaAs film thickness exceeded 3 nm, but according to the present invention, no cracks occurred even when the thickness exceeded 4 μ.

第1表 以上の実施例では、■−V族化合物半導体としてGaA
sを例に取り説明したが、■=V族化合物半導体として
InAs、 GsP、 InP等を使用しても上記効果
が得られることは言うまでもない、なお、本実施例では
Si基板上にGaAsからなる■−V族化合物半導体を
形成するに際して、MOCVD法を用いてエピタキシャ
ル成長を行っているが、本実施例は一つの例示であって
、他の結晶成長法を適用できることは言うまでもない。
In the examples shown in Table 1 and above, GaA is used as the ■-V group compound semiconductor.
s is used as an example, but it goes without saying that the above effect can be obtained even if InAs, GsP, InP, etc. are used as the = V group compound semiconductor. In addition, in this example, a semiconductor device made of GaAs on a Si substrate is used. (2) In forming the V group compound semiconductor, epitaxial growth is performed using the MOCVD method, but this example is just an example, and it goes without saying that other crystal growth methods can be applied.

例えば、分子線エピタキシャル(以下MBEと呼ぶ)法
でSi基板上にGaAsを形成する場合、多孔質層を形
成したSi基板を上記MBE装置に導入し、超高真空中
で1000°C110分の基板加熱を行い、Si基板の
表面クリーニングを行う、そして基板温度を500°C
に設定し、電子ビーム蒸着源を用いてSiを蒸発させ、
Siを1nホモエピタキシヤル成長を行う、そしてSi
戒成長クヌードセンセルを用いて^Sを蒸発させ、Si
上に^3被覆面を形成した後、基板温度を400℃に設
定しGaAs低温層を150人形成し、引続き基板温度
を750℃に設定しGaAs成長を行う。
For example, when forming GaAs on a Si substrate by molecular beam epitaxial (hereinafter referred to as MBE) method, the Si substrate on which a porous layer has been formed is introduced into the above MBE apparatus, and the substrate is heated at 100°C for 110 minutes in an ultra-high vacuum. Heating is performed, the surface of the Si substrate is cleaned, and the substrate temperature is increased to 500°C.
, and evaporate Si using an electron beam evaporation source.
Perform 1n homoepitaxial growth of Si, and
Using a grown Knudsen cell, ^S is evaporated and Si
After forming the ^3 coating surface on top, the substrate temperature is set to 400°C to form 150 GaAs low temperature layers, and then the substrate temperature is set to 750°C to perform GaAs growth.

(発明の効果) 以上説明したように、本発明によれば、Si基板表面を
多孔質状にし、その上にSiを成長させることによって
、化合物半導体に発生する反り、クラックを従来法と比
較して著しく抑えることが可能になった。このため、リ
ソグラフィー工程上高精度なデバイス設計が可能になる
結果、製造歩留まりが向上し、デバイス性能が向上する
等、経済効果は大である。
(Effects of the Invention) As explained above, according to the present invention, by making the surface of a Si substrate porous and growing Si on it, warping and cracking that occur in compound semiconductors can be reduced compared to conventional methods. It has now become possible to significantly reduce this. Therefore, it becomes possible to design devices with high precision in the lithography process, resulting in significant economic effects such as improved manufacturing yield and improved device performance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は面方位<100>のSi基板上に形成されたG
aAsエピタキシャル層の断面を表す図である。 1・・・Si基板 2・・・多孔質状Si 3・・・Siホモエピタキシャル層 4・・・GaAsエピタキシャル層 第 図
Figure 1 shows G formed on a Si substrate with a plane orientation of <100>.
FIG. 3 is a diagram showing a cross section of an aAs epitaxial layer. 1...Si substrate 2...Porous Si 3...Si homoepitaxial layer 4...GaAs epitaxial layer Fig.

Claims (2)

【特許請求の範囲】[Claims] (1)Si基板と、前記Si基板上に形成された多孔質
層と、前記多孔質層上に形成されたホモエピタキシャル
層と、前記ホモエピタキシャル層上に形成された化合物
半導体層とを備えることを特徴とする化合物半導体装置
(1) A Si substrate, a porous layer formed on the Si substrate, a homoepitaxial layer formed on the porous layer, and a compound semiconductor layer formed on the homoepitaxial layer. A compound semiconductor device characterized by:
(2)Si基板上に化合物半導体を形成する工程におい
て、前記Si基板表面に多孔質Siを形成する工程と、
前記多孔質Si表面上にSiをエピタキシャル成長せし
める工程とを具備することを特徴とする化合物半導体装
置の製造方法。
(2) a step of forming a compound semiconductor on a Si substrate, a step of forming porous Si on the surface of the Si substrate;
A method for manufacturing a compound semiconductor device, comprising the step of epitaxially growing Si on the porous Si surface.
JP17832889A 1989-07-10 1989-07-10 Compound semiconductor device and its manufacture Pending JPH0342818A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17832889A JPH0342818A (en) 1989-07-10 1989-07-10 Compound semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17832889A JPH0342818A (en) 1989-07-10 1989-07-10 Compound semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH0342818A true JPH0342818A (en) 1991-02-25

Family

ID=16046569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17832889A Pending JPH0342818A (en) 1989-07-10 1989-07-10 Compound semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH0342818A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0969522A1 (en) * 1998-07-03 2000-01-05 Interuniversitair Microelektronica Centrum Vzw A thin-film opto-electronic device and a method of making it
WO2000002259A1 (en) * 1998-07-03 2000-01-13 Interuniversitair Micro-Elektronica Centrum A thin-film opto-electronic device and a method of making it
US6121117A (en) * 1992-01-30 2000-09-19 Canon Kabushiki Kaisha Process for producing semiconductor substrate by heat treating
JP2007124451A (en) * 2005-10-31 2007-05-17 Access Co Ltd Presence control system, method for controlling presence and presence registration terminal device
JP2008292889A (en) * 2007-05-28 2008-12-04 Chugoku Electric Power Co Inc:The Display tool

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121117A (en) * 1992-01-30 2000-09-19 Canon Kabushiki Kaisha Process for producing semiconductor substrate by heat treating
EP0969522A1 (en) * 1998-07-03 2000-01-05 Interuniversitair Microelektronica Centrum Vzw A thin-film opto-electronic device and a method of making it
WO2000002259A1 (en) * 1998-07-03 2000-01-13 Interuniversitair Micro-Elektronica Centrum A thin-film opto-electronic device and a method of making it
US6683367B1 (en) 1998-07-03 2004-01-27 Imec Vzw Thin-film opto-electronic device and a method of making it
US6815247B2 (en) 1998-07-03 2004-11-09 Interuniversitair Microelektronica Centrum (Imec) Thin-film opto-electronic device and a method of making it
JP2007124451A (en) * 2005-10-31 2007-05-17 Access Co Ltd Presence control system, method for controlling presence and presence registration terminal device
JP2008292889A (en) * 2007-05-28 2008-12-04 Chugoku Electric Power Co Inc:The Display tool

Similar Documents

Publication Publication Date Title
US6191006B1 (en) Method of bonding a III-V group compound semiconductor layer on a silicon substrate
JPS58130517A (en) Manufacture of single crystal thin film
JP2021180225A (en) Manufacturing method of semiconductor substrate, manufacturing method of soi wafer and soi wafer
JPH03160714A (en) Semiconductor device and manufacture thereof
JP5238189B2 (en) Method for producing stretch-strained germanium thin film, stretch-strained germanium thin film, and multilayer structure
US5229332A (en) Method for the growth of epitaxial metal-insulator-metal-semiconductor structures
JPH0342818A (en) Compound semiconductor device and its manufacture
JP4213896B2 (en) Manufacturing method of semiconductor substrate
US5753040A (en) Method for the growth of epitaxial metal-insulator-metal-semiconductor structures
JPH04198095A (en) Method for growing thin film of compound semiconductor
JPS62171999A (en) Epitaxy of iii-v compound semiconductor
Li et al. Growth and characterization of GaAs layers on polished Ge/Si by selective aspect ratio trapping
JPH02139918A (en) Manufacture of hetero structure
JPH04182386A (en) Substrate susceptor for epitaxial growth
JPH0536605A (en) Manufacture of compound semiconductor substrate
JP2747823B2 (en) Method for producing gallium arsenide layer and method for producing gallium arsenide / aluminum gallium arsenide laminate
JPH02210817A (en) Inp epitaxial growth method
TWI387999B (en) Compound semiconductor epitaxial wafer and method of manufacturing the same
JP5032522B2 (en) Compound semiconductor epitaxial wafer and manufacturing method thereof
CN114438595A (en) Gallium nitride epitaxial growth method beneficial to improving heat dissipation performance
JPH047819A (en) Gaas thin film
JPH04280898A (en) Process for growing compound semiconductor crystal on si substrate
JPH09106949A (en) Compound semiconductor substrate and manufacture thereof
JPH0551295A (en) Production of compound semiconductor substrate
JPS6374992A (en) Growth of crystal of compound semiconductor