JPH0511411B2 - - Google Patents

Info

Publication number
JPH0511411B2
JPH0511411B2 JP5160385A JP5160385A JPH0511411B2 JP H0511411 B2 JPH0511411 B2 JP H0511411B2 JP 5160385 A JP5160385 A JP 5160385A JP 5160385 A JP5160385 A JP 5160385A JP H0511411 B2 JPH0511411 B2 JP H0511411B2
Authority
JP
Japan
Prior art keywords
film
nisi
substrate
phase epitaxial
solid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5160385A
Other languages
Japanese (ja)
Other versions
JPS61212017A (en
Inventor
Akitoshi Ishizaka
Yasuhiro Shiraki
Taku Ooshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP5160385A priority Critical patent/JPS61212017A/en
Publication of JPS61212017A publication Critical patent/JPS61212017A/en
Priority to US07/110,580 priority patent/US5047111A/en
Publication of JPH0511411B2 publication Critical patent/JPH0511411B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はNiSi2膜の形成法に関する。特に良質
の結晶性を有するNiSi2単結晶膜を容易に形成で
き、同時に、Si基板中へNiSi2からの不純物の拡
散の影響が少ないという、半導体素子に好適な
NiSi2膜の固相エピタキシヤル成長法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for forming a NiSi 2 film. In particular, NiSi 2 single-crystal films with good crystallinity can be easily formed, and at the same time, there is little influence of impurity diffusion from NiSi 2 into the Si substrate, making it suitable for semiconductor devices.
Concerning solid-phase epitaxial growth of NiSi 2 films.

〔発明の背景〕[Background of the invention]

従来、Si単結晶の上にNiSi2単結晶膜をエピタ
キシヤル成長する方法として、Ni膜とSi基板と
を反応させる固相エピタキシヤル(たとえばS.
Saitoh et al、Japan JAP.、20(1981)、1649)
と、Si基板上にNiとSiの蒸発原子を同時に照射
する同時蒸着法(たとえばJ.C.Beanet al.、
APL.、37(1980)、643〜)が知られていた。固
相エピタキシヤル法では形成法が容易であるが、
反応が拡散を伴つたものであり、Si中にNiが拡
散したり、膜の表面のモルホロジー
(morpholgy)が悪いという欠点を有した。一方、
同時蒸着法は、良好な結晶性の膜ができ、表面の
モルホジーも良く、Si基板中へのNi原子の拡散
も少いという長所を有しているが、膜の形成方
法、特にSiとNiの比を科学量論組成に時間的に
一定に保つのが困難であつた。これが実用上の難
点である。
Conventionally, as a method for epitaxially growing a NiSi 2 single crystal film on a Si single crystal, solid-phase epitaxial growth (for example, S.
Saitoh et al, Japan JAP., 20 (1981), 1649)
and a simultaneous evaporation method in which Ni and Si evaporated atoms are simultaneously irradiated onto a Si substrate (e.g., JCBeanet al.,
APL., 37 (1980), 643~) was known. Although the solid phase epitaxial method is easy to form,
The reaction involved diffusion, and the disadvantages were that Ni diffused into Si and the morphology of the film surface was poor. on the other hand,
The co-evaporation method has the advantage of producing a film with good crystallinity, good surface morphology, and little diffusion of Ni atoms into the Si substrate, but the method of forming the film, especially the Si and Ni It was difficult to keep the ratio constant over time to the stoichiometric composition. This is a practical difficulty.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、NiSi2膜の形成法において、
従来の固相エピタキシヤル法並みの容易さと、同
時蒸着法並みの良質の結晶性と、Si基板への影響
を少くするような、固相エピタキシヤル法を提案
することにある。
The purpose of the present invention is to provide a method for forming a NiSi 2 film,
Our objective is to propose a solid-phase epitaxial method that is as easy as the conventional solid-phase epitaxial method, has good crystallinity comparable to that of the simultaneous vapor deposition method, and has less influence on the Si substrate.

〔発明の概要〕[Summary of the invention]

従来の固相エピタキシヤル法の欠点は、下地の
Si基板との反応により核形成による膜の成長が生
じたり、またSiとNiの拡散反応が必須であるた
め、Si基板中にNi原子が不純物として固溶され
てしまうということであつた。したがつて、同時
蒸着法と同様にSi基板と固相反応を生じさせない
ようにし、エピタキシヤル成長は下地のSi基板に
従うようにしてやれば、上記の固相エピタキシヤ
ル法の欠点は解消される。そのためにSi基板上に
下地との反応が生じにくい350℃以下の基板温度
で望ましくは25〜200℃にて、NiSi2の組成比に
なるようにSiとNiの多層膜を形成する。安定な
NiSi2相が形成されていない時は、350℃以上、
特に450℃以上の基板温度では、下地のSi基板と
上に形成した膜との反応が顕著になるので望まし
くない。多層膜の全体としての組成はSiとの格子
のミスマツチが少く、容易にエピタキシヤル成長
が生じ、しかも、Siとの共存相として安定な
NiSi2になるようにした。この時NiとSiとの組成
比がSi/Ni>2では、エピタキシヤル成長させ
た時にNiSi2膜に余分のSiが折出した状態になり
望ましくない。またSi/Ni>1.8ではNiSi2膜を形
成する際不足のSi原子をおぎなうため下地からSi
原子が拡散してくるが、それに伴い、NiSi2膜の
表面モルホロジーが悪くなり、望ましくない。
200℃以下で形成したSiとNiの多層膜は、各層が
30〜300Åと非常に薄く、また基板の単結晶基板
に比べ、多量の格子欠陥を含むので、拡散しやす
く100℃以下でも一部NiSi2が形成されており、
350℃30分という低温でのアニールでも下地のSi
と反応することなく容易に均一なNiSi2相とな
る。このNiSi2を形成するアニール温度は上述の
如くSi基板との反応を防ぐという観点から、350
〜450℃である。なお、この多層膜からNiSi2
を形成する工程は、省略してもよい。
The disadvantage of the conventional solid-phase epitaxial method is that
The reaction with the Si substrate causes film growth due to nucleation, and since a diffusion reaction between Si and Ni is essential, Ni atoms are dissolved as impurities in the Si substrate. Therefore, the above-mentioned drawbacks of the solid-phase epitaxial method can be overcome by preventing a solid-phase reaction with the Si substrate and allowing the epitaxial growth to follow the underlying Si substrate, as in the case of the simultaneous vapor deposition method. For this purpose, a multilayer film of Si and Ni is formed on the Si substrate at a substrate temperature of 350° C. or less, preferably 25 to 200° C., where reaction with the underlying layer is less likely to occur, so that the composition ratio is NiSi 2 . stable
When NiSi 2 phase is not formed, 350℃ or higher,
In particular, a substrate temperature of 450° C. or higher is undesirable because the reaction between the underlying Si substrate and the film formed thereon becomes significant. The overall composition of the multilayer film is such that there is little lattice mismatch with Si, easy epitaxial growth occurs, and it is stable as a coexisting phase with Si.
Changed to NiSi 2 . At this time, if the composition ratio of Ni and Si is Si/Ni>2, excess Si will precipitate into the NiSi 2 film during epitaxial growth, which is undesirable. In addition, when Si/Ni>1.8, Si is removed from the base to cover the insufficient Si atoms when forming the NiSi 2 film.
As atoms diffuse, the surface morphology of the NiSi 2 film deteriorates, which is undesirable.
A multilayer film of Si and Ni formed at temperatures below 200°C has a
It is extremely thin (30 to 300 Å) and contains a large number of lattice defects compared to the single crystal substrate, so it is easy to diffuse and some NiSi 2 is formed even below 100°C.
Even when annealing is performed at a low temperature of 350°C for 30 minutes, the underlying Si
It easily becomes a homogeneous NiSi 2 phase without reacting with. The annealing temperature for forming this NiSi 2 is set at 350° C. from the viewpoint of preventing reaction with the Si substrate as mentioned above.
~450℃. Note that the step of forming a NiSi 2 film from this multilayer film may be omitted.

次にNiSi2膜あるいはNi−Si多層膜を、下地Si
単結晶基板に対し、固相エピタキシヤル成長させ
るため、350℃〜750℃に基板を加熱した。単結晶
成長は、Si基板表面が清浄であれば、350℃でも
生じるが、結晶性は悪い。
Next, apply a NiSi 2 film or a Ni-Si multilayer film to the underlying Si layer.
In order to perform solid phase epitaxial growth on a single crystal substrate, the substrate was heated to 350°C to 750°C. Single crystal growth can occur even at 350°C if the Si substrate surface is clean, but the crystallinity is poor.

500〜650℃にて、結晶性も良好で、また、表面
の凹凸も原子層オーダーの非常に平滑な単結晶膜
を得ることができる。650℃以上、特に750℃に加
熱すると、結晶性は良いが、表面の凹凸が大きく
なり、極端な場合は、NiSi2膜に穴があいて、下
地のSi基板が露出するようになる。したがつて、
500〜650℃の基板加熱温度が固相エピタキシヤル
成長させる最適の温度領域である。
At 500 to 650°C, a single crystal film with good crystallinity and a very smooth surface with irregularities on the order of atomic layers can be obtained. When heated to 650°C or higher, especially 750°C, the crystallinity is good, but the surface becomes rough, and in extreme cases, holes form in the NiSi 2 film, exposing the underlying Si substrate. Therefore,
A substrate heating temperature of 500 to 650°C is the optimum temperature range for solid phase epitaxial growth.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の詳細を実施例により説明する。 The details of the present invention will be explained below with reference to Examples.

実施例 1 Si(111)単結晶基板を分子線成長装置に挿入
し、10-10torr台の超高真空中にて低温サーマル
エツチング法により表面の清浄化を行つた。次に
基板温度を室温に下げ、Si層とNi層を各々175
Å、50Åの周期で4層ずつ交互に形成した。その
後、30分間600℃に基板を上げた。反射電子線回
折により結晶性を判定したところ単結晶パターン
が得られ、下地のSi基板(111)面に対して、同
様に(111)面のエピタキシヤル成長が生じてい
ることが判つた。次にオージエ電子分光により分
析したところ、NiSi2に特有のラインシエープの
SiLVVピークが得られ、NiSi2が生成していること
が判つた。断面を観察したところ通常の固層エピ
タキシヤル法の場合とは異なり、第1図bに示す
ように、下地のSi基板を食つてNiSi2が成長して
いるということはなかつた。なお、第1図aはSi
基板2上にNi層を形成した状態を示す断面図、
第1図bはこれを固相エピタキシヤル成長後の断
面図である。一方、第2図aは本発明の方法を用
いたもので、Ni層1とSi層3を交互にSi基板2
上に積層した状態を示す。第2図bはこの状態で
固相エピタキシヤル成長を施こした状態である。
また、表面のモルホロジー(molphology)も、
ノマルスキー型光学顕微鏡でみても何の構造もみ
られない程、鏡面状態であつた。深さ方向に、
IMA分析を行つたところ第3図に示すように、
通常の固相エピタキシヤル法の場合、のように
界面のダレは2000Åであり、一方、本発明の固相
エピタキシヤル法の場合は、界面のダレは500
Å程度であつた。このダレは、分析のイオンスパ
ツタに伴うイオン衝撃によるダレの程度であり、
本発明による方法では、Si基板中へNi原子が拡
散するのは非常に少いことが明らかである。
Example 1 A Si (111) single crystal substrate was inserted into a molecular beam growth apparatus, and the surface was cleaned by low-temperature thermal etching in an ultra-high vacuum of 10 -10 torr. Next, the substrate temperature was lowered to room temperature, and the Si layer and Ni layer were each
Four layers were formed alternately with a period of 50 Å and a period of 50 Å. Then, raise the substrate to 600 °C for 30 min. When the crystallinity was determined by backscattered electron diffraction, a single crystal pattern was obtained, and it was found that epitaxial growth of the (111) plane had similarly occurred on the (111) plane of the underlying Si substrate. Next, analysis using Auger electron spectroscopy showed that the line shape characteristic of NiSi 2
A Si LVV peak was obtained, indicating that NiSi 2 was produced. When the cross section was observed, unlike in the case of the normal solid-layer epitaxial method, as shown in Figure 1b, there was no growth of NiSi 2 eating into the underlying Si substrate. In addition, Fig. 1 a shows Si
A cross-sectional view showing a state in which a Ni layer is formed on the substrate 2,
FIG. 1b is a sectional view of this after solid phase epitaxial growth. On the other hand, Fig. 2a shows a case using the method of the present invention, in which the Ni layer 1 and the Si layer 3 are alternately placed on the Si substrate.
The state shown is that it is stacked on top. FIG. 2b shows the state in which solid phase epitaxial growth was performed in this state.
In addition, the morphology of the surface
It was so mirror-like that no structure could be seen even when viewed with a Nomarski optical microscope. In the depth direction,
When IMA analysis was performed, as shown in Figure 3,
In the case of the normal solid phase epitaxial method, the sag at the interface is 2000 Å as shown in a , while in the case of the solid phase epitaxial method b of the present invention, the sag at the interface is 500 Å.
It was about . This sagging is the extent of sagging due to ion bombardment caused by ion spatter during analysis.
It is clear that with the method according to the invention there is very little diffusion of Ni atoms into the Si substrate.

〔発明の効果〕〔Effect of the invention〕

以上、本発明によれば、 (1) Si基板からSi原子を食うことなしに、しかも
従来の固相エピタキシヤル法と同程度の容易さ
で、同時蒸着法で得られる膜質と同等のものが
形成できる。
As described above, according to the present invention, (1) film quality equivalent to that obtained by the simultaneous vapor deposition method can be obtained without eating Si atoms from the Si substrate, and with the same ease as the conventional solid-phase epitaxial method; Can be formed.

(2) しかも半導体層へNi原子の拡散が少いとい
う特徴を有している。
(2) Moreover, it has the characteristic that there is little diffusion of Ni atoms into the semiconductor layer.

半導体に対しNiSi2を使用できるという極めて
大きい効用がある。
The ability to use NiSi 2 for semiconductors has an extremely large effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a,bは従来の固相エピタキシヤル法に
より成長層の断面図で、同aは基板にNi膜形成
後の断面図、同bはこれを固相エピタキシヤル成
長した後の断面図である。第2図a,bは本発明
による固相エピタキシヤル法による成長層の断面
図で、同aはNiSi2膜の多層膜形成後の断面図、
同bはこれを固相エピタキシヤル成長した後の断
面図である。第3図は二次イオン質量分析による
Niの深さ方向分析結果を示す図である。 1……Ni膜、2……Si膜板、3……Si膜、4
……NiSi2膜。
Figures 1a and 1b are cross-sectional views of a layer grown by the conventional solid-phase epitaxial method. Figure 1a is a cross-sectional view after forming a Ni film on a substrate, and Figure 1b is a cross-sectional view after solid-phase epitaxial growth. It is. Figures 2a and 2b are cross-sectional views of a layer grown by the solid-phase epitaxial method according to the present invention, and Figure 2a is a cross-sectional view after forming a multilayer film of NiSi 2 film.
FIG. 6B is a cross-sectional view of this after it has been grown by solid phase epitaxial growth. Figure 3 is based on secondary ion mass spectrometry.
It is a figure showing the depth direction analysis result of Ni. 1...Ni film, 2...Si film plate, 3...Si film, 4
...NiSi 2 film.

Claims (1)

【特許請求の範囲】 1 Si単結晶基板上に、基板温度が350℃以下の
温度で、30〜300Åの厚さで所望の周期でNiおよ
びSi膜を交互に当該積層膜全体の組成比がSi/
Ni=2{+0 −0.2になるように積層膜を形成した後、
350〜750℃に加熱してNiSi2膜を形成することに
よりNiSi2単結晶膜をエピタキシヤル成長させる
ことを特徴とするNiSi2膜の固相エピタキシヤル
成長法。 2 前記Si膜とNi膜の積層膜をアニールによつ
てNiSi2膜とせしめ、次いでNiSi2単結晶膜をエ
ピタキシヤル成長させることを特徴とする特許請
求の範囲第1項記載のNiSi2膜の固相エピタキシ
ヤル成長法。
[Claims] 1. On a Si single crystal substrate, at a substrate temperature of 350°C or less, Ni and Si films are alternately deposited at a desired periodicity with a thickness of 30 to 300 Å so that the composition ratio of the entire laminated film is adjusted. Si/
After forming a laminated film so that Ni=2{+0 −0.2,
A solid-phase epitaxial growth method for a NiSi 2 film, characterized in that a NiSi 2 single crystal film is epitaxially grown by heating to 350 to 750°C to form a NiSi 2 film. 2. The NiSi 2 film according to claim 1, characterized in that the laminated film of the Si film and Ni film is annealed to form a NiSi 2 film, and then a NiSi 2 single crystal film is epitaxially grown. Solid phase epitaxial growth method.
JP5160385A 1985-03-16 1985-03-16 Solid-phase epitaxial growth method for nisi2 film Granted JPS61212017A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP5160385A JPS61212017A (en) 1985-03-16 1985-03-16 Solid-phase epitaxial growth method for nisi2 film
US07/110,580 US5047111A (en) 1985-03-16 1987-10-16 Method of forming a metal silicide film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5160385A JPS61212017A (en) 1985-03-16 1985-03-16 Solid-phase epitaxial growth method for nisi2 film

Publications (2)

Publication Number Publication Date
JPS61212017A JPS61212017A (en) 1986-09-20
JPH0511411B2 true JPH0511411B2 (en) 1993-02-15

Family

ID=12891473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5160385A Granted JPS61212017A (en) 1985-03-16 1985-03-16 Solid-phase epitaxial growth method for nisi2 film

Country Status (1)

Country Link
JP (1) JPS61212017A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004070804A1 (en) * 2003-02-07 2004-08-19 Nec Corporation Method for forming nickel silicide film, method for manufacturing semiconductor device, and method for etching nickel silicide

Also Published As

Publication number Publication date
JPS61212017A (en) 1986-09-20

Similar Documents

Publication Publication Date Title
US5010037A (en) Pinhole-free growth of epitaxial CoSi2 film on Si(111)
JPS58130517A (en) Manufacture of single crystal thin film
JPH076950A (en) Manufacture of structural parts for electron, lightning and optical constituent
US4816421A (en) Method of making a heteroepitaxial structure by mesotaxy induced by buried implantation
US5364468A (en) Method for the growth of epitaxial metal-insulator-metal-semiconductor structures
US5047111A (en) Method of forming a metal silicide film
US5753040A (en) Method for the growth of epitaxial metal-insulator-metal-semiconductor structures
JPH0511411B2 (en)
JPH01315127A (en) Formation of gallium arsenide layer
JPS5893220A (en) Preparation of semiconductor single crystal film
JPH0511412B2 (en)
JPH0476217B2 (en)
US5837053A (en) Process for preparing single crystal material and composite material for forming such single crystal material
JPS62132312A (en) Manufacture of semiconductor thin film
JP3205666B2 (en) Method for synthesizing CeO2 epitaxial single crystal thin film on Si single crystal substrate
JPH02316A (en) Surface flattening method and soi substrate forming method using said surface flattening method
JP2705524B2 (en) How to make a semiconductor crystal
JPS5893228A (en) Preparation of semiconductor single crystal thin film
JPH02191321A (en) Method of forming crystal
JP2771635B2 (en) Ca lower 1-lower x Sr lower x F lower 2
JPS63137412A (en) Manufacture of semiconductor substrate
JP2522618B2 (en) Phosphorus alloyed cubic boron nitride film
JPS59171114A (en) Manufacture of semiconductor single crystal film
JPS6229397B2 (en)
JPS61203630A (en) Structure of material

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term