JPS61210664A - Electrode forming method - Google Patents
Electrode forming methodInfo
- Publication number
- JPS61210664A JPS61210664A JP60051481A JP5148185A JPS61210664A JP S61210664 A JPS61210664 A JP S61210664A JP 60051481 A JP60051481 A JP 60051481A JP 5148185 A JP5148185 A JP 5148185A JP S61210664 A JPS61210664 A JP S61210664A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode film
- photoelectric conversion
- upper electrode
- patterning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000006243 chemical reaction Methods 0.000 claims abstract description 31
- 238000000059 patterning Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims 2
- 238000005530 etching Methods 0.000 abstract description 14
- 239000011229 interlayer Substances 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 6
- 238000000206 photolithography Methods 0.000 abstract description 4
- 239000007788 liquid Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 95
- 239000010410 layer Substances 0.000 description 15
- 239000004642 Polyimide Substances 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 2
- 229910001120 nichrome Inorganic materials 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electrodes Of Semiconductors (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
技術分野
本発明は、ファクシミリの等倍光センサー等のデバイス
における電極形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a method for forming electrodes in a device such as a 1-magnification optical sensor for a facsimile.
従来技術
従来、ファクシミリにおいては、ａ −Ｓ ｉ等倍光セ
ンサーを用いたものがある。第３図はそのコプラナー型
等倍光センサーの製造工程を概略的に示すものである。BACKGROUND ART Conventionally, some facsimile machines use an a-Si equal-magnification optical sensor. FIG. 3 schematically shows the manufacturing process of the coplanar type 1-magnification optical sensor.
まず、同図（ａ）に示すように、絶縁性基板１上にａ
−Ｓ ｉ光電変換膜２を形成し、この上に平面対向型電
極３ａ、３ｂを形成する。First, as shown in FIG. 2(a), a
-Si photoelectric conversion film 2 is formed, and planar opposing electrodes 3a and 3b are formed thereon.
次に、同図（ｂ）に示すように、電極３ｂ側に多層配線
用の層間絶縁膜４を形成する。この層間絶縁膜４として
は例えばポリイミド系材料が用いられる。この場合、全
面にポリイミドを塗布した後、第３図（ｂ）において斜
線を施して示す部分を除去する必要がある。そして、同
図（ｃ）に示すように、第２電極５の形成工程を行なう
。６はこの第２電極５のエツチング用のレジストである
。Next, as shown in FIG. 3B, an interlayer insulating film 4 for multilayer wiring is formed on the electrode 3b side. As this interlayer insulating film 4, for example, a polyimide material is used. In this case, after coating the entire surface with polyimide, it is necessary to remove the shaded area in FIG. 3(b). Then, as shown in FIG. 3(c), a step of forming the second electrode 5 is performed. 6 is a resist for etching this second electrode 5.
このような従来方式による場合、まず、同図（ｂ）に示
した層間絶縁膜４の形成工程において。In the case of such a conventional method, first, in the step of forming the interlayer insulating film 4 shown in FIG. 4(b).
ａ−８ｉ光電変換膜２の表面がポリイミド及びそのエッ
チャント（又は現像液）に接することになる。又、同図
（ｃ’ ）に示した第２電極５の形成工程においても、
そのエツチング時にａ −Ｓ ｊ光電変換膜２表面がレ
ジス１へ６やレジスト剥離液に接することになる。この
ようにａ −Ｓ ｊ光電変換膜２表面が何度も異なる外
部環境に直接的に晒されることになり、ａ −Ｓ ｉ光
電変換膜２の特性にバラツキや劣化を生ずるこ−とにな
る。The surface of the a-8i photoelectric conversion film 2 comes into contact with polyimide and its etchant (or developer). Also, in the step of forming the second electrode 5 shown in FIG.
During the etching, the surface of the a-Sj photoelectric conversion film 2 comes into contact with the resist 1 to 6 and the resist stripping solution. In this way, the surface of the a-S j photoelectric conversion film 2 is directly exposed to different external environments many times, causing variations and deterioration in the characteristics of the a-S i photoelectric conversion film 2. .
目的
本発明は、このような点に鑑みなされたもので、光電変
換膜がフォトレジストやレジスト剥離液等の外部環境に
晒されることがなく、その特性劣化を防止した状態で電
極を形成することができる電極形成方法を提供すること
を目的とする。Purpose The present invention was made in view of the above points, and it is an object of the present invention to form an electrode in a state where the photoelectric conversion film is not exposed to the external environment such as photoresist or resist stripping solution, and its characteristics are prevented from deteriorating. The purpose of the present invention is to provide an electrode forming method that allows for the formation of electrodes.
構成
本発明は、上記目的を達成するため、平面対向型電極構
造を有して多層配線を要するデバイスの電極形成方法に
おいて、基板上に形成された光電変換膜上に最下層電極
膜から多層配線に用いられる最上層電極膜まで順次積層
し、この最上層電極膜を積層した後レジスト材料を用い
て前記光電変換膜上部分の最下層電極膜を残して前記最
上電極膜のパターン化を行ない、このパターン化により
形成された上部電極をマスクとして前記最下層電極膜の
パターン化を行なって下部電極を形成することを特徴と
するものである。Structure In order to achieve the above object, the present invention provides an electrode formation method for a device having a planar facing electrode structure and requiring multilayer wiring. After stacking the uppermost electrode film, the uppermost electrode film is patterned using a resist material, leaving the lowermost electrode film above the photoelectric conversion film; The method is characterized in that the lowermost electrode film is patterned using the upper electrode formed by this patterning as a mask to form a lower electrode.
以下、本発明の第一の実施例を第１図に基づいて説明す
る。まず、同図（ａ）に示すように絶縁性基板１１上に
島状にパターン化されたａ−８ｉ光電変換膜１２を形成
する。このようなａ −Ｓ ｉ膜の形成には、ＳｉＨ４
のグロー放電分解法が好ましく用いられる。薄膜状に形
成したこのａ−８ｉ膜は、フォトリソグラフィー、エツ
チング工程により所望の島状にパターン化される。ここ
で、エツチングにはＣＦ、プラズマ、レジスト剥離には
０２プラズマを用いたドライエツチングプロセスが好ま
しく用いられるが、エツチングに（ＨＦ 十ＮＨ，Ｆ）
溶液、レジスト剥離にアルカリ系剥離液を用いた通
常のウェットエツチングプロセスであってもよい。Hereinafter, a first embodiment of the present invention will be described based on FIG. First, as shown in FIG. 4A, an a-8i photoelectric conversion film 12 patterned into an island shape is formed on an insulating substrate 11. To form such an a-Si film, SiH4
The glow discharge decomposition method is preferably used. This A-8i film formed into a thin film is patterned into a desired island shape by photolithography and etching steps. Here, a dry etching process using CF and plasma for etching and 02 plasma for resist stripping is preferably used;
A normal wet etching process using an alkaline stripping solution for resist stripping may be used.
このように島状のａ−８ｉ光電変換膜１２を形成した後
、全面に最下層電極膜となる下部電極膜１３を形成する
。この際、同図（ｂ）におけるＡ部分が多層配線を要す
る部分であり、このＡ部分のみを通常のフォトリソグラ
フィー、エツチングニー３＝
程によりパターン化する。このエツチング工程はウェッ
トプロセスでもドライプロセスでもよい。After forming the island-shaped a-8i photoelectric conversion film 12 in this manner, a lower electrode film 13 serving as the lowermost electrode film is formed on the entire surface. At this time, part A in FIG. 3B is a part that requires multilayer wiring, and only this part A is patterned by ordinary photolithography and etching. This etching step may be a wet process or a dry process.
下部電極膜１３を形成した後、同図（ｂ）に示すように
、Ａ部分に多層配線用の層間絶縁膜１４を形成する。こ
の層間絶縁膜１４の材料としては、ポリイミド等の有機
系材料やＳｉｏ２．５ｉａＮ４等の無機系材料あるいは
これらを組み合わせたものが用いられる。１５はコンタ
クトホールである。After forming the lower electrode film 13, an interlayer insulating film 14 for multilayer interconnection is formed in a portion A, as shown in FIG. 3(b). As the material of this interlayer insulating film 14, an organic material such as polyimide, an inorganic material such as Sio2.5iaN4, or a combination thereof is used. 15 is a contact hole.
このように層間絶縁膜１４を形成後、同図（ｃ）に示す
ように、多層配線用となる最上層電極膜としての上部電
極膜１６を全面に形成する。このような上部電極膜１６
は同図（ｄ）に示すように、レジスト１７を用いた通常
のフォトリソグラフィー、エツチング工程によりこの上
部電極膜１６のみがパターン化されて、上部電極１８が
形成されるとともに、ａ−８ｉ光電変換膜１２付近には
マスクパターン１９が形成される。この際、ａ−８ｉ光
電変換膜１２部分における下部電極膜１３は残される。After forming the interlayer insulating film 14 in this manner, an upper electrode film 16 as the uppermost layer electrode film for multilayer wiring is formed over the entire surface, as shown in FIG. 3(c). Such an upper electrode film 16
As shown in FIG. 4(d), only this upper electrode film 16 is patterned by a normal photolithography and etching process using a resist 17 to form an upper electrode 18, and a-8i photoelectric conversion. A mask pattern 19 is formed near the film 12. At this time, the lower electrode film 13 in the a-8i photoelectric conversion film 12 portion is left.
この上部電極膜１６のパターン化の後、そのフ−４＝
オドレジスト１７を剥離し、前記ａ−８ｉ光電変換膜１
２付近の下部電極膜１３上に残された上部電極膜１６の
マスクパターン１９をマスクとして下部電極膜１３のエ
ツチングを行ない、パターン化してａ−８ｉ光電変換膜
１２の左右に別れた平面対向型電極２０ａ、２０ｂが形
成される。After patterning the upper electrode film 16, the photoresist 17 is peeled off and the a-8i photoelectric conversion film 1 is removed.
Using the mask pattern 19 of the upper electrode film 16 left on the lower electrode film 13 near 2 as a mask, the lower electrode film 13 is etched and patterned to form a planar facing type that is separated into left and right sides of the A-8I photoelectric conversion film 12. Electrodes 20a, 20b are formed.
このような工程により、ａ−８ｉ等倍光センサーが形成
される。本実施例方式によれば、ａ−８ｉ光電変換膜１
２のパターン形成時と最後の上部電極膜１６をマスクと
した下部電極膜１３のエツチング時以外の工程において
は、ａ −Ｓ ｉ光電変換膜１２の表面が常に下部電極
膜１３により覆われており、フォトレジストやレジスト
剥離液、ポリイミド等の有機系材料及びそれらのエツチ
ング液（感光性材料の場合には、現像液）等にａ−８ｉ
光電変換膜１２表面が晒されることがなく、製造プロセ
スにおけるａ−８ｉ光電変換膜１２の特性のバラツキや
劣化を最小限に抑えることができる。この結果、歩留り
も向上し、かつ、完成したデバイスの長期的な信頼性も
向上することになる。Through these steps, an a-8i 1x optical sensor is formed. According to the method of this embodiment, the a-8i photoelectric conversion film 1
The surface of the a-Si photoelectric conversion film 12 is always covered with the lower electrode film 13 in steps other than the pattern formation in step 2 and the final etching of the lower electrode film 13 using the upper electrode film 16 as a mask. , a-8i for photoresists, resist stripping solutions, organic materials such as polyimide, and their etching solutions (developing solutions in the case of photosensitive materials), etc.
The surface of the photoelectric conversion film 12 is not exposed, and variations and deterioration in the characteristics of the a-8i photoelectric conversion film 12 during the manufacturing process can be minimized. This results in improved yield and long-term reliability of the completed device.
ここで、下部電極膜１３としては、ａ−８ｉ光電変換膜
１２とのオーミックコンタクトを形成するＡＱ （膜厚
５００人〜１μｍ程度）が好ましく、上部電極膜１６と
しては、下部電極膜１３のエツチング時にマスクとして
使えるＮ１Ｃｒ（膜厚５００人〜１μｍ程度）が好まし
い。もつとも、このような組合せに限定されるものでな
く、例えば下部電極膜１３にＡ Ｑ −Ｓ ｉ、上部電
極膜１６にＣｒを用いるような組合せでもよい。Here, the lower electrode film 13 is preferably AQ (film thickness of about 500 to 1 μm) that forms ohmic contact with the a-8i photoelectric conversion film 12, and the upper electrode film 16 is preferably formed by etching the lower electrode film 13. N1Cr (film thickness of about 500 to 1 μm), which can sometimes be used as a mask, is preferable. However, the combination is not limited to such a combination, and for example, a combination in which AQ-S i is used for the lower electrode film 13 and Cr is used for the upper electrode film 16 may be used.
つづいて、本発明の第二の実施例を第２図により説明す
る。第１図で示した部分と同一部分は同一符号を付して
示す。基本的には、前記実施例と同様であるが、下部電
極膜１３を２層構造として第一下部電極膜１３ａと第二
下部電極膜１３ｂとに分けて形成するとともに、上部電
極膜１６も２層構造として第一上部電極膜１６ａと第二
上部電極膜１６ｂとに分けて形成したものである。まず
、下部電極膜１３を２層に分けるのは、層間絶縁膜１４
のコンタクトホール１５での上部電極膜１６とのコンタ
クトを取り易くするためである。一方。Next, a second embodiment of the present invention will be described with reference to FIG. Components that are the same as those shown in FIG. 1 are designated by the same reference numerals. Basically, it is the same as the above embodiment, but the lower electrode film 13 has a two-layer structure and is formed separately into a first lower electrode film 13a and a second lower electrode film 13b, and the upper electrode film 16 is also formed. A two-layer structure is formed separately into a first upper electrode film 16a and a second upper electrode film 16b. First, the lower electrode film 13 is divided into two layers by the interlayer insulating film 14.
This is to facilitate contact with the upper electrode film 16 through the contact hole 15. on the other hand.
上部電極膜１６を２層構造にするのは、セルフアライン
メントエツチングの際のマスクにするためである。The reason why the upper electrode film 16 has a two-layer structure is to use it as a mask during self-alignment etching.
しかして、この第２図（ｄ）、（ｅ）に示すように、上
部電極膜１６のエツチングの際に、まず、フォトレジス
ト１４をマスクにして最下層の第二下部電極膜１３ｂの
みの一層だけを残してエツチングし、フォトレジスト１
４を剥離除去した後、電極膜１６ａ、１６ｂ、１３ａを
マスクとして最下層の第二下部電極膜１３ｂをセルフア
ラインメントエツチングするものである。As shown in FIGS. 2(d) and 2(e), when etching the upper electrode film 16, first, using the photoresist 14 as a mask, only the second lower electrode film 13b, which is the lowest layer, is etched. Etch leaving only the photoresist 1
After peeling off and removing the second lower electrode film 13b, the second lower electrode film 13b, which is the lowest layer, is subjected to self-alignment etching using the electrode films 16a, 16b, and 13a as masks.
本実施例において、第一下部電極膜１３ａとしてはＡＱ
、第二下部電極膜１３ｂとしてはＮｉＣｒの組合せ、第
一上部電極膜１６ａとしてはＮｉＣｒ、第二上部電極膜
１６ｂとしてはＡＱの組合せが好ましいが、これに限定
されるものではない。In this embodiment, the first lower electrode film 13a is AQ
A combination of NiCr for the second lower electrode film 13b, NiCr for the first upper electrode film 16a, and AQ for the second upper electrode film 16b is preferred, but the combination is not limited thereto.
又、本実施例では、下部電極膜１３及び上部電極膜１６
を共に２層構造としたが、更に多層構造としてもよいこ
とは勿論である。Further, in this embodiment, the lower electrode film 13 and the upper electrode film 16
Both have a two-layer structure, but it is of course possible to have a multi-layer structure.
なお、これらの実施例では、ａ−８層等倍光センサーを
例にとり説明したが、これに限らず同様の構造を有する
デバイスの電極形成に適用できるものである。In addition, although these examples have been explained by taking an a-8 layer equal-magnification optical sensor as an example, the present invention is not limited to this and can be applied to electrode formation of a device having a similar structure.
効果
本発明は、上述したように最下層電極膜から最上層電極
膜まで順次積層形成してこの最上層電極膜のパターン化
を光電変換膜上の最下層電極膜が残るように行ない、そ
の後、上部電極をマスクとして最下層電極膜のパターン
化を行なうようにしたので、光電変換膜が自身のパター
ン形成時と最後の最下層電極膜のパターン化時以外の時
にはその表面が最下層電極膜により常に覆われているこ
とになり、よって、光電変換膜の表面がフォトレジスト
やレジスト剥離液等による外部環境に晒されることがな
く、製造プロセスにおける光電変換膜の特性のバラツキ
や特性劣化を最小限に抑えることができるものである。Effects In the present invention, as described above, layers are sequentially formed from the bottom electrode film to the top electrode film, the top electrode film is patterned so that the bottom electrode film remains on the photoelectric conversion film, and then, Since the lowermost electrode film is patterned using the upper electrode as a mask, when the photoelectric conversion film is not forming its own pattern or patterning the final lowermost electrode film, its surface is exposed to the lowermost electrode film. This means that the surface of the photoelectric conversion film is always covered, so the surface of the photoelectric conversion film is not exposed to the external environment due to photoresist, resist stripping liquid, etc., and variations in the characteristics of the photoelectric conversion film and property deterioration during the manufacturing process are minimized. This can be suppressed to .
第１図（ａ）〜（ｅ）は本発明の第一の実施例を工程順
に示す断面図、第２図（ａ）〜（ｅ）は本発明の第二の
実施例を工程順に示す断面図、第３図（ａ）〜（ｃ）は
従来例を工程順に示す断面図である。
１１・・・基板、１２・・・ａ−８ｉ光電変換膜（光電
変換膜）、１３・・・下部電極膜（最下層電極膜）、１
４・・・レジスト、１６・・・上部電極膜（最上層電極
膜）、１７・・・上部電極、１８・・・マスクパターン
、１９・・・下部電極、１３ｂ・・・第二下部電極膜（
最下層電極膜）、１６ａ・・・第一上部電極膜（最上層
電極膜）
出 願゛ 人 株式会社 リ コ −、ＪＺ図FIGS. 1(a) to (e) are cross-sectional views showing the first embodiment of the present invention in the order of steps, and FIGS. 2(a) to (e) are cross-sectional views showing the second embodiment of the present invention in the order of steps. 3(a) to 3(c) are cross-sectional views showing a conventional example in the order of steps. 11... Substrate, 12... a-8i photoelectric conversion film (photoelectric conversion film), 13... Lower electrode film (lowest layer electrode film), 1
4... Resist, 16... Upper electrode film (top layer electrode film), 17... Upper electrode, 18... Mask pattern, 19... Lower electrode, 13b... Second lower electrode film (
(lowest layer electrode film), 16a...first upper electrode film (top layer electrode film) Applicant: Ricoh Co., Ltd., JZ diagram
Claims (1)
の電極形成方法において、基板上に形成された光電変換
膜上に最下層電極膜から多層配線に用いられる最上層電
極膜まで順次積層し、この最上層電極膜を積層した後レ
ジスト材料を用いて前記光電変換膜上部分の最下層電極
膜を残して前記最上電極膜のパターン化を行ない、この
パターン化により形成された上部電極をマスクとして前
記最下層電極膜のパターン化を行なつて下部電極を形成
することを特徴とする電極形成方法。In a method for forming electrodes for a device having a planar facing electrode structure and requiring multilayer wiring, the method comprises sequentially laminating layers from the lowest electrode film to the uppermost electrode film used for multilayer wiring on a photoelectric conversion film formed on a substrate, After laminating this uppermost electrode film, the uppermost electrode film is patterned using a resist material, leaving the lowermost electrode film above the photoelectric conversion film, and the upper electrode formed by this patterning is used as a mask. An electrode forming method comprising forming a lower electrode by patterning the lowermost electrode film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60051481A JPS61210664A (en) | 1985-03-14 | 1985-03-14 | Electrode forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60051481A JPS61210664A (en) | 1985-03-14 | 1985-03-14 | Electrode forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61210664A true JPS61210664A (en) | 1986-09-18 |
Family
ID=12888146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60051481A Pending JPS61210664A (en) | 1985-03-14 | 1985-03-14 | Electrode forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61210664A (en) |
-
1985
- 1985-03-14 JP JP60051481A patent/JPS61210664A/en active Pending
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