JPS61210629A - Pattern formation method - Google Patents
Pattern formation methodInfo
- Publication number
- JPS61210629A JPS61210629A JP60051704A JP5170485A JPS61210629A JP S61210629 A JPS61210629 A JP S61210629A JP 60051704 A JP60051704 A JP 60051704A JP 5170485 A JP5170485 A JP 5170485A JP S61210629 A JPS61210629 A JP S61210629A
- Authority
- JP
- Japan
- Prior art keywords
- resist film
- pattern
- photomask
- exposure
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、パターン形成方法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a pattern forming method.
従来、露光工程では第５図に示すように半導体基板１上
にレジスト膜２を形成し、これに第６図に示すように光
透過領域３と光遮蔽領域４を有するフォトマスク５を通
して光を照射する。Conventionally, in the exposure process, a resist film 2 is formed on a semiconductor substrate 1 as shown in FIG. irradiate.
このような光の選択的照射によって光が当ったレジスト
膜２の領域は感光し、現像することによシ第７図に示す
ように残存パターン６となる。As a result of this selective irradiation of light, the area of the resist film 2 that is hit by the light is exposed to light, and by development, a residual pattern 6 is formed as shown in FIG.
光が当らなかった領域のレジスト膜２の部分は除去され
開口部７となる。これはボッ型のレジスト膜２を露光・
現像した場合である。ネガ型のレジスト膜の場合は露光
後に残存する領域が逆に光の当らなかった領域となる。The portions of the resist film 2 that are not exposed to light are removed to form openings 7. This exposes the resist film 2 in the shape of a hole.
This is the case when it is developed. In the case of a negative resist film, the area remaining after exposure is the area that was not exposed to light.
ボッ型、ネガ型の倒れにしても従来の・９ターン形成方
法では、−回の露光に一枚のフォトマスクを使用してい
る。In the conventional 9-turn forming method, one photomask is used for -times of exposure, even when it comes to flat and negative shapes.
而して、半導体基板１上に段差が存在するとその表面に
形成したレジスト膜２の膜厚が段差の前後で相違する。Therefore, when a step exists on the semiconductor substrate 1, the thickness of the resist film 2 formed on the surface thereof is different before and after the step.
一般に第８図に示すように段差の上側８ではレジスト膜
１の膜厚は薄くなり、段差の下側９では厚くなる。その
結果、段差によって膜厚が不均一になった状態で第９図
に示すようなフォトマスク５を用いて一定光量の露光を
施すと、第８図に示すように、段差の上側８ではノ９タ
ーニングされたレジスト膜２の幅が狭く、段差の下側９
では幅が広くなる。また、第１０図に示す如く、段差の
上下の所定領域に対応してコンタクトホールを形成する
ための光遮蔽領域１θ、１ノを有するフォトマスク１２
を用いてレジスト膜２の７４ターニングを行うと、第１
１図に示すように、レジスト膜２の開口された窓１３．
１４は、段差の上側８では径が大きく、段差の下側９で
は小さくなる。因みに、露光時間が５００ ｍｓでレジ
スト膜２の膜厚が厚肉側で２，０μｍ、薄肉側で１．２
μｍ（膜厚比０．６）の場合、レジスト膜２に開口され
た窓１３．１４の径は、段差の上側８のものでは２．１
μｍφとなり、段差の下側９のものでは１６μｍφとな
る。このように段差がある場合にパターニングされるレ
ジスト膜２の形状に影響を及ぼす因子としては、段差の
高さ、断面形状、下地の反射率、レジスト膜２の膜厚、
光源の特性等が考えられる。何れにしても段差上のレジ
スト膜２にサブミクロン寸法のパターニングヲｍす場合
には、段差の上下で形成されるパターンの不均一によっ
て所謂レジストショートを起こす問題があった。Generally, as shown in FIG. 8, the thickness of the resist film 1 is thinner on the upper side 8 of the step, and thicker on the lower side 9 of the step. As a result, if a photomask 5 as shown in FIG. 9 is used to expose a film with a constant amount of light in a state where the film thickness is uneven due to the step, as shown in FIG. 9 The width of the turned resist film 2 is narrow, and the lower side of the step 9
Then the width becomes wider. Further, as shown in FIG. 10, a photomask 12 having light shielding regions 1θ and 1NO for forming contact holes corresponding to predetermined regions above and below the step.
When the resist film 2 is turned 74 times using
As shown in FIG. 1, the resist film 2 has an opened window 13.
14 has a large diameter on the upper side 8 of the step and becomes smaller on the lower side 9 of the step. Incidentally, when the exposure time is 500 ms, the thickness of the resist film 2 is 2.0 μm on the thick side and 1.2 μm on the thin side.
μm (film thickness ratio 0.6), the diameter of the window 13.14 opened in the resist film 2 is 2.1 in the case of the upper side 8 of the step.
The diameter is 16 μmφ on the lower side 9 of the step. Factors that influence the shape of the resist film 2 patterned when there is a step as described above include the height of the step, the cross-sectional shape, the reflectance of the base, the thickness of the resist film 2,
Possible factors include the characteristics of the light source. In any case, when patterning the resist film 2 on a step with submicron dimensions, there is a problem in that a so-called resist short circuit occurs due to non-uniformity of the pattern formed above and below the step.
本発明は、半導体基板上の段差部の寸法差の影響を排除
して、所定パターンのレジスト膜を正確に形成すること
ができる・ゼターン形成方法を提供することをその目的
とするものである。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a zetern which can accurately form a resist film in a predetermined pattern by eliminating the influence of dimensional differences in step portions on a semiconductor substrate.
本発明は、段差によって生じたレジスト膜の膜厚差に応
じた露光量でレジスト膜に露光処理を施すようにしたこ
とにより、半導体基板上の段差部の寸法差の影響を排除
して、所定パターンのレジスト膜を正確に形成すること
ができるパターン形成方法である。The present invention eliminates the influence of the dimensional difference of the step portion on the semiconductor substrate by performing exposure processing on the resist film with an exposure amount corresponding to the film thickness difference of the resist film caused by the step difference, and thereby This is a pattern forming method that can accurately form a patterned resist film.
以下、本発明の実施例について図面を参照して説明する
。先ず、第１図（蜀に示す如く、段差を有する半導体基
板２θ上にレジスト膜２１を形成する。次いで、例えば
段差を通過して直線状のレジスト膜・母ターンを形成す
る場合は、先ず同図（Ｂ）に示すような目的とするレジ
スト膜パターンと同じパターンの光遮蔽領域２２を有す
るフォトマスク２３を用意し、このフォトマスク２３を
介してレジスト膜２ノに露光処理を施す。この露光処理
後には従来の方法と同様に第２図に示すような段差の下
側２７で幅Ｌ１が広く、段差の上側２８で幅Ｌ２の狭い
レジスト膜パターンが形成される。次にこのレジスト膜
パターンの形状の不均一を修正するために、第１図Ｃ）
に示す如く、レジスト膜パターンの幅広の領域に対応し
てこれよりも幅Ｌｓの狭い光遮蔽領域２４を有するフォ
トマスク２５を用意する。Embodiments of the present invention will be described below with reference to the drawings. First, as shown in FIG. A photomask 23 having a light shielding area 22 with the same pattern as the intended resist film pattern as shown in FIG. 2B is prepared, and the resist film 2 is exposed to light through this photomask 23. After processing, a resist film pattern is formed in which the width L1 is wide at the lower side 27 of the step and the width L2 is narrower at the upper side 28 of the step, as shown in FIG. 2, as in the conventional method.Next, this resist film pattern is In order to correct the non-uniformity of the shape of Figure 1C)
As shown in FIG. 2, a photomask 25 having a light shielding region 24 having a width Ls narrower than the wide region of the resist film pattern is prepared.
次いで、このフォトマスク２５を介してレジスト膜パタ
ーンに露光処理を施すことにより、第１図囚にて実線で
示すように直線上のレジスト膜パターン２６を段差を通
過して半導体基板２θに形成する。なお、フォトマスク
２３による第１の露光時間とフォトマスク２５による第
２の露光時間が異なっても良い。Next, by exposing the resist film pattern through this photomask 25, a straight resist film pattern 26 is formed on the semiconductor substrate 2θ passing through the step, as shown by the solid line in FIG. . Note that the first exposure time using the photomask 23 and the second exposure time using the photomask 25 may be different.
また、段差の下側２７と上側２８の夫々の領域に同形状
のコンタクトホールを形成する場合は、第２図（Ａ）に
示すように段差の下側２７に形成するコンタクトホール
の形状に対応した光透過領域２９を有する第１フオトマ
スク３０と、段差の上側２８に形成するコンタクトホー
ルの形状に対応した光透過領域３１を有する第２図（Ｂ
）に示すような第２フオトマスク３２を用意する。この
場合夫々の光透過領域２９の形状は同じであるが形成位
置が異っている。而して、第１フオトマスク３０を用い
て段差の下側２７にだけ露光処理を施し、所定形状のコ
ンタクトホールをレジスト膜２１に形成する。次いで、
これよシも多い露光量で第２フオトマスク３２を用いて
段差の上側２８のレジスト膜２１上に所定形状のコンタ
クトホールを形成する。因みに、第３図に示す如く、段
差の上側２８に形成されるコンタクトホールの径と露光
時間の関係が特性線（Ｉ）で示され１段差の下側２７に
形成される６一
コンタクトホールの径と露光時間の関係が特性線ω）で
表わされる場合、段差の上下両側２７゜２８に２．０μ
ｍφのコンタクトホールを形成しようとすると、第１回
目の露光時間（下側２７）は約４２０ ｍｓであり、第
２回目の露光時間（上側２８）は約６５０ ｍｓである
。In addition, when forming contact holes of the same shape on the lower side 27 and upper side 28 of the step, the shape corresponds to the shape of the contact hole formed on the lower side 27 of the step, as shown in FIG. 2(A). FIG. 2 (B
) Prepare a second photomask 32 as shown in FIG. In this case, the shapes of the respective light transmitting regions 29 are the same, but the formation positions are different. Then, using the first photomask 30, exposure processing is performed only on the lower side 27 of the step, and a contact hole of a predetermined shape is formed in the resist film 21. Then,
A contact hole of a predetermined shape is formed on the resist film 21 on the upper side 28 of the step using the second photomask 32 with a larger exposure amount. Incidentally, as shown in FIG. 3, the relationship between the diameter of the contact hole formed on the upper side 28 of the step and the exposure time is shown by the characteristic line (I). When the relationship between the diameter and exposure time is expressed by the characteristic line ω), 2.0μ is applied at 27°28 on both sides of the step.
When attempting to form a contact hole of mφ, the first exposure time (lower side 27) is about 420 ms, and the second exposure time (upper side 28) is about 650 ms.
また、実施例のように２回露光によってライン状のレジ
スト膜ツリー７２６やコンタクトホールを形成した場合
、段差の大きさと形成する・９ターンの所定値からのず
れは第４図に特性線（２）にて示す通シであり、はぼ零
に等しか、従来の方法によるものでは同図に特性線面に
て示す如く、段差が大きくなるに従って所定値から大き
くずれたノ４ターンになることが確認されている。In addition, when a line-shaped resist film tree 726 or a contact hole is formed by two exposures as in the example, the size of the step and the deviation from the predetermined value of 9 turns are shown in the characteristic line (2 ), which is approximately equal to zero, but with the conventional method, as shown in the characteristic line in the same figure, as the step increases, the value becomes 4 turns, which deviates greatly from the predetermined value. has been confirmed.
以上説明した如く、本発明に係るパターン形成方法によ
れば、半導体基板上の段差部の寸法差による影響を排除
して、所定の・９ターンを正確に形成することができる
ものである。As explained above, according to the pattern forming method according to the present invention, it is possible to eliminate the influence of the dimensional difference in the step portion on the semiconductor substrate, and to form the predetermined 9 turns accurately.
第１図（Ａ）は、本発明方法を示す説明図、同図（Ｂ）
、 （Ｃ’）及び第２図（Ａ） ｅ （Ｂ） ハ、本
発Ｌ７［Ｋ−ｃＭ用するフォトマスクの斜視図、第３図
は、コンタクトホールと露光時間の関係を示す特性図、
第４図は、所定パターンからのずれ値と段差の大きさと
の関係を示す特性図、第５図は、半導体基板上にレジス
ト膜を形成した状態を示す説明図、第６図、第９図及び
第１０図は、従来の方法で使用するフォトマスクの斜視
図、第７図及び第１１図は、従来の方法で）ｆターニン
グされたレジスト膜の説明図、第８図は、段差の上下で
レジスト膜の膜厚が異りている状態を示す説明図である
。
２θ・・・半導体基板、２ノ・・・レジストＨＩＸ、２
２・・・光遮蔽領域、２３・・・フォトマスク、２４・
・・光遮蔽領域、２５・・・フォトマスク、２６・・・
レジスト膜パターン、２７・・・段差の下側、２８・・
・段差の上側、２９・・・光透過領域、３０・・・フォ
トマスク、３１・・・光透過領域、３２・・・フォトマ
スク。
ｆ板【恢−１＼菱−ｇ５實９う
憾FIG. 1(A) is an explanatory diagram showing the method of the present invention, and FIG. 1(B) is an explanatory diagram showing the method of the present invention.
, (C') and Figures 2 (A) e (B) C. A perspective view of the photomask used for the present invention L7 [K-cM, Figure 3 is a characteristic diagram showing the relationship between contact holes and exposure time,
FIG. 4 is a characteristic diagram showing the relationship between the deviation value from a predetermined pattern and the size of the step, FIG. 5 is an explanatory diagram showing the state in which a resist film is formed on a semiconductor substrate, and FIGS. 6 and 9 and FIG. 10 are perspective views of a photomask used in the conventional method, FIGS. 7 and 11 are explanatory diagrams of a resist film that has been turned by the conventional method, and FIG. 8 is a perspective view of a photomask used in the conventional method. FIG. 3 is an explanatory diagram showing a state in which the thickness of the resist film is different between the two resist films. 2θ...semiconductor substrate, 2no...resist HIX, 2
2... Light shielding area, 23... Photomask, 24...
...Light shielding area, 25... Photomask, 26...
Resist film pattern, 27... Bottom side of step, 28...
- Above the step, 29... Light transmission area, 30... Photomask, 31... Light transmission area, 32... Photomask. f board [恢-1\Rhi-g5 fact 9 regret
Claims (2)
を形成する工程と、該レジスト膜の所定領域に該所定領
域部分の膜厚に応じた露光量で選択的に露光する工程と
を具備することを特徴とするパターン形成方法。(1) A step of forming a resist film on the uneven surface of a semiconductor substrate, and a step of selectively exposing a predetermined region of the resist film with an exposure amount depending on the film thickness of the predetermined region portion. A pattern forming method characterized by:
段が、２枚以上のフォトマスクを用いた複数回の露光に
て行うものである特許請求の範囲第１項記載のパターン
形成方法。(2) The pattern formation according to claim 1, wherein the means for determining the exposure amount according to the film thickness of a predetermined area portion is performed by multiple exposures using two or more photomasks. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60051704A JPS61210629A (en) | 1985-03-15 | 1985-03-15 | Pattern formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60051704A JPS61210629A (en) | 1985-03-15 | 1985-03-15 | Pattern formation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61210629A true JPS61210629A (en) | 1986-09-18 |
Family
ID=12894279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60051704A Pending JPS61210629A (en) | 1985-03-15 | 1985-03-15 | Pattern formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61210629A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007163632A (en) * | 2005-12-12 | 2007-06-28 | Hitachi Displays Ltd | Method for manufacturing display device, display device and exposure apparatus |
-
1985
- 1985-03-15 JP JP60051704A patent/JPS61210629A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007163632A (en) * | 2005-12-12 | 2007-06-28 | Hitachi Displays Ltd | Method for manufacturing display device, display device and exposure apparatus |
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