JPS61205176U - - Google Patents
Info
- Publication number
- JPS61205176U JPS61205176U JP8897385U JP8897385U JPS61205176U JP S61205176 U JPS61205176 U JP S61205176U JP 8897385 U JP8897385 U JP 8897385U JP 8897385 U JP8897385 U JP 8897385U JP S61205176 U JPS61205176 U JP S61205176U
- Authority
- JP
- Japan
- Prior art keywords
- hole
- inner via
- multilayer printed
- wiring board
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims 1
- 239000011229 interlayer Substances 0.000 claims 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Description
第１図は本考案の一実施例の多層印刷配線板の
断面図、第２図は従来の多層印刷配線板を示す断
面図、第３図は従来の多層印刷配線板の平面図、
第４図は一実施例の多層印刷配線板の平面図であ
る。
１：多層印刷配線板、２：絶縁体層、３：表層
配線パターン（第１層、第ｎ層）、４：内層配線
パターン（第２層〜第ｎ―１層）、５：スルーホ
ール、６：インナーバイアホール、７：本実施例
特有のインナーバイアホール。
FIG. 1 is a sectional view of a multilayer printed wiring board according to an embodiment of the present invention, FIG. 2 is a sectional view of a conventional multilayer printed wiring board, and FIG. 3 is a plan view of a conventional multilayer printed wiring board.
FIG. 4 is a plan view of a multilayer printed wiring board according to one embodiment. 1: Multilayer printed wiring board, 2: Insulator layer, 3: Surface layer wiring pattern (1st layer, nth layer), 4: Inner layer wiring pattern (2nd layer to n-1th layer), 5: Through hole, 6: Inner via hole, 7: Inner via hole unique to this embodiment.
Claims (1)
続用のインナーバイアホールとを有する多層印刷
配線板において、 少なくとも一つのインナバイアホール７をスル
ーホール５より大径に形成し、 該インナーバイアホール７をスルーホール５と
同心状に設けて、 該インナーバイアホール７及びスルーホール５
の絶縁を保持しつつ、両者を同一位置に設けたこ
とを特徴とする多層印刷配線板。[Claims for Utility Model Registration] In a multilayer printed wiring board having through holes 5 for connecting interlayer wiring and inner via holes for connecting inner layer wiring, at least one inner via hole 7 is formed to have a larger diameter than the through hole 5. The inner via hole 7 is provided concentrically with the through hole 5, and the inner via hole 7 and the through hole 5 are arranged concentrically.
A multilayer printed wiring board characterized in that both are provided at the same position while maintaining insulation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8897385U JPS61205176U (en) | 1985-06-14 | 1985-06-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8897385U JPS61205176U (en) | 1985-06-14 | 1985-06-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61205176U true JPS61205176U (en) | 1986-12-24 |
Family
ID=30642628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8897385U Pending JPS61205176U (en) | 1985-06-14 | 1985-06-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61205176U (en) |
-
1985
- 1985-06-14 JP JP8897385U patent/JPS61205176U/ja active Pending