JPS622274U - - Google Patents
Info
- Publication number
- JPS622274U JPS622274U JP9390885U JP9390885U JPS622274U JP S622274 U JPS622274 U JP S622274U JP 9390885 U JP9390885 U JP 9390885U JP 9390885 U JP9390885 U JP 9390885U JP S622274 U JPS622274 U JP S622274U
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrates
- insulating
- layers
- insulating substrate
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Non-Adjustable Resistors (AREA)
- Combinations Of Printed Boards (AREA)
Description
第１図および第２図は本考案の一実施例を示し
、第１図はこの実施例の縦断側面図、第２図はこ
の実施例の多層印刷配線板の作成手順の一例を示
す工程図、第３図は本考案の他の実施例を示す中
央縦断側面図、第４図は従来例の多層印刷配線板
の作成手順を示す工程図である。
１ａ，１ｂ，１ｃ……絶縁基板、２ａ，２ｂ，
２ｃ……導体層、８……抵抗。
1 and 2 show an embodiment of the present invention, FIG. 1 is a longitudinal cross-sectional side view of this embodiment, and FIG. 2 is a process diagram showing an example of the procedure for producing a multilayer printed wiring board of this embodiment. 3 is a central vertical sectional side view showing another embodiment of the present invention, and FIG. 4 is a process diagram showing the procedure for producing a conventional multilayer printed wiring board. 1a, 1b, 1c...Insulating substrate, 2a, 2b,
2c...conductor layer, 8...resistance.
Claims (1)
絶縁基板の主表面上に導体層を印刷形成すると共
に各絶縁基板を積層してなり、前記各絶縁基板の
少なくとも層間に位置する導体層に抵抗が設けら
れてなる多層印刷配線板において、前記各絶縁基
板は予め焼成されており、前記各導体層が前記絶
縁基板に焼き付けられ、かつ、前記層間に位置す
る抵抗を所望値に設定した状態において、前記各
絶縁基板を積層したことを特徴とする多層印刷配
線板。 A plurality of insulating substrates made of ceramic are provided, a conductive layer is printed on the main surface of each insulating substrate, and the insulating substrates are laminated, and a resistor is provided in at least the conductive layer located between the layers of each insulating substrate. In the multilayer printed wiring board, each of the insulating substrates is fired in advance, and each of the conductor layers is baked onto the insulating substrate, and the resistance located between the layers is set to a desired value. A multilayer printed wiring board characterized by laminating various insulating substrates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9390885U JPS622274U (en) | 1985-06-20 | 1985-06-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9390885U JPS622274U (en) | 1985-06-20 | 1985-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS622274U true JPS622274U (en) | 1987-01-08 |
Family
ID=30652005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9390885U Pending JPS622274U (en) | 1985-06-20 | 1985-06-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS622274U (en) |
-
1985
- 1985-06-20 JP JP9390885U patent/JPS622274U/ja active Pending