JPS61201448A - Formation of multilayer interconnection structure - Google Patents

Abstract

PURPOSE:To avoid disconnection and short circuit by a method wherein a groove is not produced in a layer insulation film. CONSTITUTION:A resist 10 which has a high absorption rate in an ultraviolet (UV) sensitive region is applied on a substrate 1. After exposure, the resist 10 is removed and a pattern is formed. The pattern is tapered so as to make a trapezoid wiring space due to absorption of UV in the resist. A wiring conductor 11, for instance Al, is deposited in the wiring space by a means of good penetration such as a vacuum evaporation apparatus with a planetary movement or a sputtering apparatus. Thus, the lower layer wiring 11 has a tapered trapezoid cross section. With this constitution, the resist 10 is easy to be peeled off and a shape of a layer insulation film 12 is also gently-sloped so that a groove is not created.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for forming a multilayer wiring structure for flattening a living room insulating film in a semiconductor device having a multilayer wiring structure.

<Prior art> In manufacturing a semiconductor device having a multilayer wiring structure,
When forming an interlayer insulating film with lower wiring, there are various methods for leveling the living room insulating film, such as so-called etch-back and lift-off.

Among these, the etch-back method employs the following steps.

To explain with reference to FIG. 2, a lower wiring pattern 2 is formed on a substrate l, and an interlayer insulation ff1l is placed on top of this.
1513 (FIG. 2(b)), then apply resist 4 etc. (FIG. 2(C)), and dry etching with RIE (Realize Ion Etcher) etc. to separate the resist 4 and interlayer insulating film 3. the same etch rate
(Carve with (Fig. 2 (C) a) (perform etch Φ back)
This makes the living room insulation film 3 flat (FIG. 2 (d))
, and then form the upper layer wiring 5 (FIG. 2(e)).

(Problems to be solved by the invention) In the etch-back method described in FIG.
), the flatness of the living room insulating film 3 is still not sufficient because the etching speed by RIE etc. varies depending on the thickness and other conditions, and the etching rate for each manufacturing unit is not uniform. This is because the etching cannot be controlled, making it difficult to stop the etching at a suitable position (for example, line a in FIG. 2(C)), and thus the groove 3S formed in the interlayer insulating film 3 remains. The generation of this groove 3'S also causes disconnection of the layer wiring &t4 as shown in FIG. 2(e), and also causes disconnection between the upper layer wiring 4 and If they are too close to the lower layer wiring 2, it may cause a short circuit.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, one object of the present invention is to provide a method for forming a multilayer wiring structure that prevents the occurrence of disconnections and short circuits by preventing the formation of grooves in the interlayer insulating film.

<Means for Solving the Problems> The present invention, which achieves the object L, is to form a trapezoidal cross-section wiring on the substrate using a resist having a high absorption rate for UV when forming the lower layer wiring on the substrate. It is characterized by a step of patterning to form a space, and then depositing the wiring conductor in a planetary motion so as to wrap around it.

<Example> The present invention will now be described in detail with reference to FIG. In FIG. 1, a resist (10) having a high absorption rate in the ultraviolet sensitive region UV (ultra violet) is coated on a substrate 1, and patterning is performed by exposing the resist 10 to remove the resist lO (FIG. 1(a)). ).

In this case, the wiring space is tapered to form a trapezoidal shape as shown in FIG. 1(a) because of UV absorption by the resist.

Then, the wiring conductor 1, for example, An, is deposited in the wiring space using a vacuum evaporation device with planetary motion or a method with good wraparound, such as sputtering (FIG. 1(b)).

After this, only the lower layer wiring 11 is patterned by removing the resist 1O by the lift-off method (FIG. 1(C)). In this case, since the lower layer wiring 11 has a tapered trapezoidal cross section, It becomes easier to remove the resist 1O when it is peeled off, and the disadvantage of the conventional re-ret Φ-off method that the resist cannot be removed sufficiently can also be eliminated. That is, Regis) 1 in FIG. 1(C)
0 can be removed satisfactorily.

A living room insulation film 12 is deposited on the substrate 1 so as to cover the lower layer wiring 11 (FIG. 1(d)).
2. For example, C*D (chemical paper)
PSG (phosphosilicate)
Some are made of glass).

In forming this living room insulating film 12, the lower wiring 11 is formed to have a trapezoidal cross-section with a gentle shoulder, so the interlayer insulating film 12 also has a gently sloping shape, unlike the conventional one. Grooves will no longer occur.

Next, a resist 13 is coated on the interlayer insulating film 12 (FIG. 1(e)), and the resist 13 and a part of the interlayer insulating film 12 are removed by the etch-O-back method described above.
2 is leveled (Fig. 1(f)). At this time, even if some steps remain due to variations in etching speed or non-uniformity in etch rate control, no grooves are formed and the desired level is achieved. can be converted.

Upper layer wiring 14 is formed on the flattened interlayer insulating film 12 (FIG. 1(g)).

<Effects of the Invention> As explained above, according to the present invention, the living room insulating film can be deposited in a trapezoidal shape with a taper on the lower layer wiring with good step coverage, can be deposited without forming grooves, and can be deposited without etch back. The flattening by the method can be stabilized, short circuits between the lower and upper layer wirings are less likely to occur, the withstand voltage can be improved, and there is no disconnection of the upper layer wiring.

[Brief explanation of drawings]

FIG. 1 is a manufacturing process diagram showing an embodiment of the present invention. Figure O shows a conventional manufacturing process diagram. Figure middle 1 is the board, 10.13 is resist, 11 is a wiring conductor or lower layer wiring. 12 is a living room insulating film.

Claims (1)

[Claims] When forming lower layer wiring on the substrate, UV light is applied to the substrate.
A method for forming a multilayer wiring structure, comprising the steps of: patterning a wiring space with a trapezoidal cross section using a resist with a high absorption rate;