JPS61196530U - - Google Patents
Info
- Publication number
- JPS61196530U JPS61196530U JP1985075403U JP7540385U JPS61196530U JP S61196530 U JPS61196530 U JP S61196530U JP 1985075403 U JP1985075403 U JP 1985075403U JP 7540385 U JP7540385 U JP 7540385U JP S61196530 U JPS61196530 U JP S61196530U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- circuit board
- printed circuit
- flexible printed
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案半導体チツプの装着構造を示す
斜視図、第２図は第１図におけるＡ―Ａ′断面図
、第３図は本考案装着構造により半導体チツプを
ガラス基板に取り付けたときの断面図、第４図は
従来の装着構造を示す断面図である。
１，６…ガラス基板、２，９…半導体チツプ、
３，３…１０，１０…ボンデイングパツド、７，
７…第１の端子、８…電源供給ライン、１１…裏
面電極、１２…フレキシブルプリント基板、１３
…開口、１４，１４…第２の端子、１５…異方性
導電膜、１６…引き出しリード端子。
Fig. 1 is a perspective view showing the mounting structure of the semiconductor chip of the present invention, Fig. 2 is a cross-sectional view taken along line A-A' in Fig. 1, and Fig. 3 shows the mounting structure of the semiconductor chip mounted on a glass substrate using the mounting structure of the present invention. 4 is a sectional view showing a conventional mounting structure. 1, 6... Glass substrate, 2, 9... Semiconductor chip,
3,3...10,10...bonding pad, 7,
7... First terminal, 8... Power supply line, 11... Back electrode, 12... Flexible printed circuit board, 13
...Opening, 14, 14...Second terminal, 15...Anisotropic conductive film, 16...Output lead terminal.
Claims (1)
造において、ガラス基板上に設けられた第１の端
子と、上記半導体チツプがフエイスダウンボンド
されるフレキシブルプリント基板と、このフレキ
シブルプリント基板に設けられ、上記半導体のボ
ンデイングパツドと圧着される第２の端子と、こ
のフレキシブルプリント基板とガラス基板間に介
在され、ガラス基板の第１の端子からフレキシブ
ルプリント基板の第２の端子までを電気的に接続
する異方性導電膜と、から成る半導体チツプの装
着構造。 In a mounting structure for mounting a semiconductor chip on a glass substrate, a first terminal provided on the glass substrate, a flexible printed circuit board to which the semiconductor chip is face-down bonded, and a mounting structure provided on the flexible printed circuit board and connected to the semiconductor chip. A second terminal is crimped to the bonding pad of the flexible printed circuit board, and a second terminal is interposed between the flexible printed circuit board and the glass substrate to electrically connect the first terminal of the glass substrate to the second terminal of the flexible printed circuit board. A semiconductor chip mounting structure consisting of a directional conductive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985075403U JPS61196530U (en) | 1985-05-21 | 1985-05-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985075403U JPS61196530U (en) | 1985-05-21 | 1985-05-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61196530U true JPS61196530U (en) | 1986-12-08 |
Family
ID=30616593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985075403U Pending JPS61196530U (en) | 1985-05-21 | 1985-05-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61196530U (en) |
-
1985
- 1985-05-21 JP JP1985075403U patent/JPS61196530U/ja active Pending