JPS61195480A - Ic card - Google Patents

Abstract

PURPOSE:To prevent an IC card from being damaged due to an electrostatic charge given carelessly by connecting a depression-type FET element across the electrode and the earth of an IC chip and then connecting the gate of the FET to a DC current power source connecting electrode. CONSTITUTION:The depression-type FET elements 11, 12 and 13 are connected across the power source terminal 1 of the IC chip, terminals 2 and 3 and the earth terminal 8, and a bias available from dividing a voltage by resistances 9 and 10 is impressed on the gate of each FET element from the power source terminal 1. In the disuse of the card, an impedance between the drain and source of the FET elements 11-13 comes to a low value because a voltage between the gate and source is low. When data is written and read from the card, a bias of about 1V is given to the gate from the power source terminal 1 to raise the impedance between the drain and the source. Thus even if the electrostatic charge is carelessly given to the electrode in the disuse of the card, a sharp rise in a potential can be prevented, and the card can be protected from the damage.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an IC card containing an IC chip therein.

Conventional technology IC card concepts and IC card construction methods are discussed, for example, in Paul Parmentier's “E
Electronic Memory Card: Te
chnologiesarzone it″I M
C1982Pxocedingi.

Tokyo, May 24-26, 1982 pp.
439-446.

As shown in this document, the concept of this IC card was devised to further improve the security of the widely used business card-sized magnetic cards. It has a structure in which an IC chip is embedded inside a PVC card having stripes, and its electrode portions are exposed on the surface of the card.

As mentioned above, when the electrode part is exposed on the card surface, static charge often adheres to the electrode part, although it depends on the material of the card.When introducing a memory chip with an MO8 structure as an IC chip, This problem is particularly important because IC chips are easily destroyed by static charges.

As a countermeasure against this static charge, several proposals have been proposed so far.

For example, a method of covering the periphery of the electrode part with a shielding electrode connected to ground is disclosed in Japanese Patent Publication No. 57-188.
No. 849 "Device for protecting electronic circuits from static charges" discloses that each electrode of the electrode section is formed on a semiconductive circuit board, a resistive element is connected between each of the electrodes, Furthermore, by adopting a structure in which a semi-conductive adhesive material is applied across each of the electrodes, a minute current path is created between each electrode of the electrode section, and as a countermeasure against static charge. The method is shown in JP-A-59-22353, JP-A-59-22354, and JP-A-69-22365.

Problems to be Solved by the Invention As mentioned above, countermeasures against static charges in IC cards are extremely important problems, and various countermeasures are being proposed. With the above method of using shielding electrodes, the probability that static charges are inadvertently applied to each electrode is reduced, but it cannot be reduced to zero. If the impedance of the current path is large, the rise in potential due to static charge is large, so it is not a complete countermeasure against static charge.If the impedance of the current path is lowered, signal leakage occurs between each electrode, creating a new problem.

The present invention has been made in view of these points, and it is an object of the present invention to obtain an IC card having a simple structure and having excellent antistatic characteristics.

Means for Solving the Problems In order to solve the above problems, the present invention provides a depression type FKT gate between the electrode of the IC chip and the ground, and the gate of the depression type FET element is connected to the DC power supply connection electrode. An IC with excellent anti-static characteristics that prevents the potential of each electrode portion from increasing significantly even if static charge is inadvertently applied to each of the electrode portions provided on the surface of the IC card.
It is intended to compose a card.

Operation According to the above-described configuration, when the IC card is not in use, each electrode provided on the surface of the IC card and the ground are connected with a low impedance between the drain and source of the depletion type FET element which is biased to zero. Therefore, even if an electrostatic charge is inadvertently applied to each electrode, the potential of that electrode will not increase much, and the IC installed in the IC card will
The chip can be protected from destruction due to static charge, and an extremely stable IC card can be obtained.

In addition, by using the DC power supply to operate the IC card and operating the bias circuit, the above-mentioned F
By turning off the ET element, there is no need for a control voltage application terminal to separately turn off the FET element, and an IC card that is extremely stable against electrostatic damage with an electrode configuration compatible with conventional IC cards is obtained. be able to.

Embodiment FIGS. 1 and 2 are circuit diagrams mainly showing an IC card surface electrode part, which shows an embodiment of the present invention, and FIG. 3 is a circuit diagram showing an example of the present invention.
Junction type F as a channel depression type FET element
FIG. 3 is a characteristic diagram showing drain and source characteristics when ET2ST84 is used.

In Fig. 1, terminals 1.2 and 3.8 indicate electrode terminals on the surface of the IC card, 1 is a power supply terminal for power supply connection, terminal 8 is a ground terminal, and terminals 1 and 8 are connected to resistive elements 9 and 8. 1
o is connected, and these resistance elements 9 and 1o operate as a bias circuit for the depression type FET elements 11, 12, and 13.

The drains and sources of depletion type FET elements 11, 12, 13 are connected between terminals 1, 2.3 and ground terminal 8, respectively, and the gates of each FET element are connected to resistor element 9.
, 1o.

In Figure 1, each terminal 1 when this IC card is not used.
．． No other external circuit is connected to 2, 3.8, and each F
Since the impedance between the drain and source of the ET elements 11, 12, and 13 is zero, the voltage between the gate and the source is zero, so the FET element is, for example, a P-channel junction FET as shown in FIG.

When 2SJ84 is used, the value is as low as about 150 ohms, which means that each terminal 1 to 7 is connected to ground with sufficiently low impedance.

Therefore, in this case, even if static charges are inadvertently applied to terminals 1 to 7, the potential of each of these terminals will not increase significantly (this can protect the circuit inside the IC card). In order to read and write information to and from an IC card configured as shown in FIG. As is clear from 0 In the above explanation, it is assumed that a positive DC voltage is applied to the power supply terminal 1, and a P-channel junction type FET is used. However, when a negative DC voltage is applied to the power supply terminal 1, an N-channel type FET is used. Needless to say, it is sufficient to use an FET of .

Furthermore, in order to improve the resistance of each terminal 1 to 7 in FIG. 1 to static charges, it is of course possible to connect a resistive element between each terminal 1 to 7 and the ground terminal 8.

Furthermore, although a junction FET has been described here as a depletion type FET element, it goes without saying that an MO8 type FET can also be employed in the same manner.

Furthermore, it goes without saying that it is desirable from economical considerations to use these depression type FET elements simultaneously fabricated in a monolithic form in an IC chip for an xC card.

Figure 2 shows a protective resistor element 1 connected in series with each terminal 2 to 7 in order to improve the resistance to static electricity in the circuit shown in Figure 1.
8.19 is provided, and has the same functions as those shown in Figure 1 by Motoshisha, which are given the same numbers as in Figure 1.

The protective resistance element shown in Figure 2 limits the current flowing to the FET element when static charge is inadvertently applied to each terminal 2 to 7, and the other operations are completely the same as those in Figure 1. Since they are the same, further details will be omitted.

It should be noted that the bias circuits shown in FIGS. 1 and 2 show the simplest case, and it goes without saying that various changes can be made without departing from the gist of the present invention.

Effects of the Invention As described above, according to the present invention, it is possible to obtain an IC card with a simple structure that is extremely resistant to static charges, and is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are ICs showing one embodiment of the present invention.
FIG. 3 is a circuit diagram mainly showing the surface electrode portion of the card, and a characteristic diagram showing drain and source characteristics when a junction type FET is used as a deblessing type FET element. 1...Power terminal, 2, 3...Terminal, 9
...Resistance element, 10...Resistance element.

Claims (4)

[Claims] (1) An IC card in which a depression type FET element is provided between an electrode of an IC chip and ground, and a gate of the depression type FET element is connected to a DC power supply connection electrode. (2) The IC card according to claim 1, wherein the depression type FET element is monolithically formed in an IC chip included in the IC card. (3) Connect the drain of the depression type FET element to each electrode provided on the surface of the IC card via a protective resistor, and connect the drain of the FET element to the IC chip and its peripheral circuit included in the IC card. The IC card according to claim 1, characterized in that the IC card is connected. (4) The IC card according to claim 1, wherein a depression type FET element, a bias circuit, and a protection resistor are simultaneously formed monolithically within an IC chip included in the IC card.