JP2865132B2 - Input / output protection circuit for semiconductor devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output static protection circuit for a semiconductor device which prevents an internal circuit from being damaged by applying an excessive voltage to an input / output portion of the semiconductor device.

[0002]

2. Description of the Related Art FIG. 4 is a top view showing an example of an input / output electrostatic protection circuit of a semiconductor device of this kind. FIG. 5 is an equivalent circuit diagram thereof.

Referring to FIGS. 4 and 5, this input / output electrostatic protection circuit includes an enhancement-type n-channel transistor 39 and an enhancement-type p-channel transistor 38 as well.
And input / output interface buffer 2 as internal circuit
By connecting between the input and output terminals 00 and 00, when an excessive voltage is applied to the input / output pad 33, a current flows through the power supply line 34 or the ground line 35, thereby eliminating the influence on the input / output interface buffer 200. In FIG. 4, reference numeral 31 denotes a contact, 32 denotes a gate, 36 denotes a source, 3
7 is a drain and 30 is a signal line.

Another conventional example is to reduce the current density in the diffusion layer of the input / output current by increasing the contact hole between the diffusion layer and the power supply line in the protection circuit or the cross-sectional area of the diffusion layer. There is an example of preventing destruction at that location. As still another conventional example, there is an example in which the impurity concentration in a contact hole portion of a diffusion layer is increased and the impurity concentration in other portions is decreased, thereby improving the electrostatic breakdown voltage of a transistor. These two conventional examples are also represented by the equivalent circuit diagram of FIG.

[0005]

In the input / output electrostatic protection circuit of the conventional semiconductor device, including the conventional examples shown in FIGS. 4 and 5 and the other two conventional examples, an excessive voltage is applied to the input / output pad. When the current is applied to the input / output interface buffer as an internal circuit through the input / output interface buffer, depending on the operation state of the input / output interface buffer, the current passes not only through the protection circuit itself but also through the transistors constituting the input / output interface buffer to the power supply line, Flows into lines. In such a case, the current is concentrated on the diffusion layer of the input / output interface buffer, so that the diffusion layer and the gate oxide film may be thermally damaged. That is, the input / output electrostatic protection circuit of the conventional semiconductor device has a problem that the protection operation is not sufficient and reliable.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input / output electrostatic protection circuit for a semiconductor device in which the protection operation for the semiconductor device is sufficient and reliable.

[0007]

According to the present invention, the present invention extends between an input / output pad and an input / output interface buffer of a semiconductor device, and directly connects between the input / output pad and the input / output interface buffer. At least one of the signal line and a power supply line extending substantially parallel to the signal line, and / or the signal line and a ground line extending substantially parallel to the signal line. An input / output electrostatic protection circuit of a semiconductor device having substantially a plurality of transistors arranged in parallel in the direction in which the wiring extends, and protecting the input / output interface buffer, wherein each of the plurality of transistors The resistance value between the wiring and the wiring may be gradually decreased from the input / output pad side to the input / output interface buffer side. O ESD protection circuit of the semiconductor device can be obtained.

According to the present invention, each contact of the plurality of transistors is inclined at a position in the channel width direction of the transistor so as to approach the gate from the input / output pad side to the internal circuit side. An input / output electrostatic protection circuit for the semiconductor device is provided.

Further, according to the present invention, each contact of the plurality of transistors is inclinedly increased in the channel width direction from the input / output pad side toward the internal circuit side. An input / output electrostatic protection circuit for the semiconductor device is obtained.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an input / output electrostatic protection circuit of a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

An input / output electrostatic protection circuit of a semiconductor device according to an embodiment of the present invention extends between an input / output pad and an input / output interface buffer of the semiconductor device, and extends between the input / output pad and the input / output interface buffer. At least one of a signal line directly connecting the power supply line and a power supply line extending substantially parallel to the signal line, and / or a signal line and a ground line extending substantially parallel to the signal line. On the other hand, it has substantially a plurality of transistors arranged in parallel in the direction in which the wiring extends. The resistance value between each of the plurality of transistors and the wiring is configured to gradually decrease from the input / output pad side toward the input / output interface buffer side.

[First Embodiment] FIG. 1 is a top view showing an input / output electrostatic protection circuit of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is an equivalent circuit diagram thereof.

Referring to FIGS. 1 and 2, the input / output electrostatic protection circuit comprises an enhancement type n-channel transistor 19 and an enhancement type p-channel transistor 18 as well. Input / output interface buffer 20 as internal circuit
By connecting between 0 and 0, when an excessive voltage is applied to the input / output pad 13, a current flows through the power supply line 14 or the ground line 15, and the influence on the input / output interface buffer 200 is eliminated. In FIG. 1, reference numeral 11 denotes a contact, 12 denotes a gate, 16 denotes a source, 17
Is a drain, and 10 is a signal line.

The n-channel transistor 19 and the p-channel transistor 18 are connected by their contacts 11 to the signal lines 10 and 10 extending between the input / output interface buffer 200 and the input / output pad 13.
And a power supply line 14 extending substantially parallel to the signal line 14, and a signal line 14 and a ground line 15 extending substantially parallel to the signal line 14. Substantially including a plurality of transistors.

Each of the contacts 11 of the plurality of transistors is inclined with respect to the position in the channel width direction of the transistor so as to approach the gate 12 from the input / output pad 13 side toward the input / output interface buffer 200 side. I have. As a result, the resistance value between each of the plurality of transistors and the wiring gradually increases from the input / output pad 13 toward the input / output interface buffer 200.

With the above structure, the input / output pad 1
Even if an excessive voltage is applied to 3, the plurality of transistors are sequentially turned on from the side of the input / output pad 13 having a relatively large electrostatic withstand voltage and current flows to the power supply line 14 or the ground line 15, so that The transistor on the side of the input / output interface buffer 200 having a small electrostatic withstand voltage is not easily broken. Further, since the sheet resistance and the contact resistance of the source and drain of the transistor are smaller than those of the conventional example shown in FIGS. 4 and 5, for example, an excessive voltage is not easily applied to the input / output interface buffer 200. Therefore, the input / output electrostatic protection circuit itself and the internal circuit are reliably and sufficiently protected.

[Second Embodiment] FIG. 3 is a top view showing an input / output electrostatic protection circuit of a semiconductor device according to a second embodiment of the present invention. The equivalent circuit is the same as in the first embodiment.
As shown in FIG.

Referring to FIGS. 3 and 2, the input / output electrostatic protection circuit includes an enhancement-type n-channel transistor 29 and an enhancement-type p-channel transistor 28 as well. Input / output interface buffer 20 as internal circuit
By connecting between 0 and 0, when an excessive voltage is applied to the input / output pad 13, a current flows through the power supply line 24 or the ground line 25, and the influence on the input / output interface buffer 200 is eliminated. In FIG. 3, reference numeral 21 denotes a contact, 22 denotes a gate, 26 denotes a source, 27
Is a drain, and 20 is a signal line. The n-channel transistor 29 and the p-channel transistor 28 are connected to the signal line 2 extending between the input / output interface buffer 200 and the input / output pad 23 by their contacts 21.
0 and a power supply line 2 extending substantially parallel to the signal line 20
4, between the signal line 24 and the ground line 25 extending substantially in parallel with the signal line 24, including substantially plural transistors arranged in parallel in the direction in which these lines extend. I have.

The number of contacts 21 of a plurality of transistors increases in the channel width direction from the input / output pad 23 side toward the input / output interface buffer 200 side. In this example, in addition to the number, the position is also determined from the input / output pad 23 side.
The gates are inclined so as to approach the gate 22 toward the 00 side. As a result, the resistance value between each of the plurality of transistors and the wiring gradually increases from the input / output pad 23 toward the input / output interface buffer 200.

With the above structure, the input / output pad 2
Even if an excessive voltage is applied to 3, the plurality of transistors are sequentially turned on from the side of the input / output pad 23 having a relatively large electrostatic withstand voltage and current flows to the power supply line 24 or the ground line 25. The transistor on the side of the input / output interface buffer 200 having a small electrostatic withstand voltage is not easily broken. The destruction prevention effect is higher than in the first embodiment. Further, since the sheet resistance and the contact resistance of the source and drain of the transistor are smaller than those of the conventional example shown in FIGS. 4 and 5, for example, an excessive voltage is not easily applied to the input / output interface buffer 200.
This effect is even higher than in the first embodiment. Therefore, the input / output electrostatic protection circuit itself and the internal circuit are reliably and sufficiently protected.

[0021]

The input / output electrostatic protection circuit of the semiconductor device according to the present invention extends between the input / output pad and the input / output interface buffer of the semiconductor device and directly connects between the input / output pad and the input / output interface buffer. At least one of between a signal line connected to the power line and a power line extending substantially parallel to the signal line, and between a signal line and a ground line extending substantially parallel to the signal line. An input / output electrostatic protection circuit of a semiconductor device having substantially a plurality of transistors arranged in parallel in a direction in which the wiring extends, and protecting an input / output interface buffer, wherein each of the plurality of transistors is connected to a wiring. About the resistance value between
Since the slope of the input / output interface buffer is gradually decreased from the input / output pad side to the input / output interface buffer side, the transistor on the input / output interface buffer side having a relatively small electrostatic withstand voltage is hardly destroyed. The output interface buffer is reliably and well protected.

[Brief description of the drawings]

FIG. 1 is a diagram showing an input / output electrostatic protection circuit of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the input / output electrostatic protection circuit shown in FIGS. 1 and 3.

FIG. 3 is a diagram showing an input / output electrostatic protection circuit of a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a diagram showing an input / output electrostatic protection circuit of a semiconductor device according to a conventional example.

FIG. 5 is an equivalent circuit diagram of the input / output electrostatic protection circuit shown in FIG.

[Explanation of symbols]

 10, 20, 30 signal lines 11, 21, 31 contacts 12, 22, 32 gates 13, 23, 33 input / output pads 14, 24, 34 power supply lines 15, 25, 35 ground lines 16, 26, 36 sources 17, 27 , 37 Drain 18, 28, 38 P-channel transistor 19, 29, 39 N-channel transistor 200 Input / output interface buffer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/04 H01L 21/822 H01L 23/60

Claims (3)

(57) [Claims] An input / output pad and an input / output input of a semiconductor device.
The input / output pad extending between the
And the input / output interface buffer
At least one of the following signal line and a power supply line extending substantially parallel to the signal line, and / or between the signal line and a ground line extending substantially parallel to the signal line. On the other hand, the input / output interface has substantially a plurality of transistors arranged in parallel in the direction in which the wiring extends.
A O ESD protection circuit of a semiconductor device for protecting a Subaffa, the resistance value between the respective wiring of the plurality of transistors, entering-from the output pad side
An input / output electrostatic protection circuit for a semiconductor device, characterized in that the input / output electrostatic protection circuit decreases inclining toward the output interface buffer . 2. The method according to claim 1, wherein each contact of the plurality of transistors has a position in a channel width direction of the transistor.
2. The input / output electrostatic protection circuit for a semiconductor device according to claim 1, wherein the gate is arranged so as to approach the gate from the input / output pad side toward the internal circuit side. 3. The method according to claim 1, wherein each contact of the plurality of transistors has a number of transistors in a channel width direction.
3. The input / output electrostatic protection circuit of a semiconductor device according to claim 1, wherein the input / output electrostatic protection circuit is inclinedly increased from the input / output pad side toward the internal circuit side.