JPS61150090A - Ic card - Google Patents

Abstract

PURPOSE:To improve the anti-electrostatic charge characteristic of an IC card by connecting resistance elements between an IC chip and the grounding of a peripheral circuit part and between a gate and a grounding and providing a D-type FET with a gate as a zero bias. CONSTITUTION:Gates, sources and groundings of depression-type FET elements 11-18 are connected to an electrode terminal for releasing an IC card protecting function 9, a grounding electrode terminal and terminals 1-8, respectively. Between the terminal 9 and the grounding a resistance element for setting a space between gates and sources of respective FET elements is connected. When an electrostatic charge is given to the terminals 1-8, it is discharged to the grounding through each FET. In case of reading and writing information, a negative voltage of about one volt is impressed on said electrode terminal 9 to turn off each FET.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an IC card containing an IC chip therein.

Regarding conventional technology IC card concepts and IC card configuration methods, see, for example, "Paul Parmentier"
Electonic Memory Card:Te
chronology around it”I
MC1982Proceedings.

Tokyo, May 24-26. 1982 pp.
439-446.

As shown in this document, the concept of this IC card was devised to further improve the security of magnetic cards, which are larger than business card size and are widely used. P with magnetic stripes similar to
It has a structure in which an IC chip is embedded inside the VC card, and its electrode portions are exposed on the surface of the card.

However, if the electrode part is exposed on the card surface, static charge often adheres to the electrode part, although it depends on the material of the card.When introducing a memory chip with an MO3 structure as an IC chip, the IC chip becomes static. This problem is particularly important because it is easily destroyed by electric charges.

As a countermeasure against this static charge, several proposals have been proposed so far.

For example, a method of covering the periphery of an electrode part with a shielding electrode connected to ground is shown in Japanese Patent Laid-Open No. 188849/1984, and a method in which each electrode of the electrode part is formed on a semiconductive circuit board is disclosed. , by connecting a resistive element between each electrode, or by adopting a structure in which a semiconductive adhesive material is attached across each electrode, minute current paths can be created between each electrode in the electrode section. The method of providing static charge countermeasures is
JP-A-59-22363, JP-A-59-2235
No. 4 and Japanese Patent Application Laid-Open No. 59-22355.

Problems to be Solved by the Invention As described above, countermeasures against static charges in IC cards are extremely important problems, and various countermeasures are being proposed. However, with the method of using shielding electrodes, the probability that static charge is inadvertently applied to each electrode decreases, but it does not become zero. If the impedance of the current path is large, the increase in potential due to static charge is large, so it is not a complete countermeasure against static charge, and if the impedance of the current path is lowered, there is a problem that signal leakage will occur between each electrode. .

The present invention has been made in view of these points, and it is an object of the present invention to obtain an IC card having a simple structure and having excellent antistatic characteristics.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention has electrode sections provided on the surface of the IC card connected to the IC chip and its peripheral circuits. A depletion type FET element is provided between the gates of each FET element and the ground, and a resistance element is connected between the gate of each FET element and the ground, thereby constructing an IC card with the gate at zero bias.

Function The present invention has the above configuration, so when the IC card is not used, the I
Each electrode provided on the surface of the C card and the ground are connected through a low impedance between the drain and source of a depletion type FET element with zero bias, so even if static charge is inadvertently applied to each electrode, , the potential of the electrode does not increase much, and the IC chip provided in the IC card can be protected from destruction due to static charge, making it possible to obtain an extremely stable IC card.

Embodiment FIG. 1 is a circuit diagram showing an example of the present invention, mainly showing the electrode section on the surface of an IC card, and FIG. 2 shows the drain and source characteristics when a junction type FET2SK155 is used as a depression type FET element. FIG.

In FIG. 1, terminals 1 to 10 indicate electrode terminals on the surface of the IC card. Here, terminal 10 is a ground electrode terminal, terminal 9 is an electrode terminal for canceling the IC card protection function, and depression type FET elements 11, 12, 13, 17
．． 18 gate electrodes, and furthermore, this terminal 9
A resistive element 19 is connected between the gate and the ground to set zero bias between the gate and source of each FET element.

In the same figure, when the card is inconvenient, no other circuit is connected to the terminals 1 to 10, and the impedance between the drain and the source is, for example, a junction type FET 2SK1 having depreciation type characteristics as shown in FIG. 2 as an FET element.
When using 55, it shows a low value of about 100 ohm,
Each terminal 1 to 8 will be connected to ground with sufficiently low impedance.

Therefore, in this case, even if static charges are inadvertently applied to the terminals 1 to 8, the potential of each terminal does not increase significantly, and the circuit inside the IC card can be protected.

In order to read and write information to and from an IC card configured in this manner, it is desirable to use the FET elements 11, 12, 13, and 17.18 in the OFF state, but this is not possible. As is clear from the characteristic diagram in Fig. 2, the electrode terminal 9 for canceling the IC card protection function has a
It is sufficient to apply a negative voltage of about volts.

Note that when the terminal 9 is not led out to the card surface as a card surface electrode, and therefore the terminal 9 is used in a state where no control voltage is applied even when the card is in use, the FET elements 11, 12, 13, 17 .18 is
If the voltage of the input signal from terminals 1 to 8 is several volts or more, it will operate as a constant current sinking element as shown in Figure 2, but the external read/write circuit should be designed with this in mind. If so, it goes without saying that there is no need to apply any control voltage to the terminal 9.

In addition, in order to improve the resistance to static charges at terminals 1 to 8 in Figure 1, a resistor element having a relatively large value (for example, 100Ω) is installed between each terminal from terminals 1 to 8 and the ground. Of course, they may be connected.

Furthermore, although a junction FET has been explained here as a depletion type FET element, it goes without saying that a MOS type FET can also be adopted in the same way. Needless to say, this method is preferable in view of the fact that it can be manufactured and used at the same time, and considering economic efficiency.

Furthermore, although not shown, each terminal 1 to 8 in FIG.
It goes without saying that if the drains of the FET elements 11 to 18 are not directly connected as shown in FIG. 1, but a protective resistor is introduced between them, the protection effect against static charges will be further improved.

Effects of the Invention As described above, according to the present invention, it is possible to obtain an IC card with a simple structure that is extremely resistant to static charges, and is extremely useful in practice.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram around the surface electrode portion of an IC card showing an embodiment of the present invention, and Fig. 2 is a characteristic diagram of a junction type FET as a depression type FET element.0 1.2, 3, 7.8 ...Electrode terminal, 9...
・・Electrode terminal for canceling IC card protection function, 10・・・・
・・Earth electrode terminal, 11.12, 13, 17.18・
...Depression type FET element, 19...
...Resistance element.

Claims (5)

[Claims] (1) In order to connect the IC chip included in the IC card body and its peripheral circuit section with an external circuit section, each electrode is connected to the IC chip body and its peripheral circuit section and provided on the surface of the IC card. A depletion type FET is connected between the IC chip and the ground of the peripheral circuitry.
1. An IC card characterized in that an IC card is provided with an FET element, and a resistor element is connected between the gate of each FET element and the ground to set the gate to zero bias. (2) Between the gate and source of the depletion type FET element, only when using an IC card, the drain of the FET element,
2. The IC card according to claim 1, wherein a bias voltage is applied to turn off between the sources. (3) The IC card according to claim 1, wherein the depression type FET element is simultaneously formed in a monolithic form within an IC chip included in the IC card. (4) Connect the drain of the depression type FET element to each electrode part provided on the surface of the IC card via a protective resistor, and connect the drain of the FET element to the IC chip included in the IC card and its peripheral circuit part. An IC card according to claim 1, characterized in that: (5) IC for depletion type FET element and protection resistor
2. The IC card according to claim 1, wherein the IC card is formed simultaneously in a monolithic form within an IC chip contained within the card.