JPS61282980A - Ic card - Google Patents

Abstract

PURPOSE:To prevent the electrostatic destruction of a latch-up preventing MOS transistor and to improve remarkably an electrostatic characteristic by setting the impedance of a signal line to the prescribed value. CONSTITUTION:A data processing part 3 and a data memory 4 are loaded on an IC card main body 1, and a drive pulse is supplied to a data processing part 3 through a signal line 6 from an external terminal 5 and to a processing circuit through a protecting resistance 8 and a gate 10. The MOS transistor 9 is provided between the input side of the gate 10 and a grounding to prevent a latch-up phenomenon. An additional resistance 12 is provided between the external terminal 5 and the data processing part 3, and the values of the additional resistance 12 and a floating capacity 7 are set. The impedance of the signal line 6 is set so that a charge quality Q built in the MOS transistor 9 can be less than CM.Vth, where CM and Vth denote a MOS capacity and the threshold of a destruction voltage. Then a voltage caused by a charged electric charge is limited below the withstand voltage of the MOS transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC card in which data can be written and read.

[Prior art]

In recent years, compact IC cards that can be attached to terminal devices to write and read large amounts of data have been provided, and are attracting a lot of attention because they can be used in a wide range of applications such as cash cards and data files. .

As shown in FIG. 4, such an IC card is provided in a card body 1 made of resin (in a recessed part, a data processing section 3 and a data memory 4 are mounted, and this data processing section 3 and an external terminal A board 2 on which a signal line, a power supply line, a grounding wire (not shown), etc. are wired is inserted between 5. and 5., respectively, and the entire board 2 is covered except for external terminals 51 to 5I. The data processing unit 3 is an IC chip consisting of a microprocessor, a program memory, etc., and performs processing for writing and reading data in the data memory 4.
The data memory 4 is a non-volatile memory IC chip such as a programmable read-only memory.

When writing or reading data using such an IC card, the IC card may be attached to a terminal (not shown) and predetermined operations may be performed. When the IC card is inserted into the terminal, the external terminals 51 to 5 are connected to the external terminals of the terminal, respectively, and the external terminals 5.5 are connected from the terminal to the IC card. ~5.
Power supply voltage, clock pulses, reset pulses, etc. are supplied through the terminal, and the IC card is grounded to be in an operating state, and data is sent and received between the terminal and the IC card by operating the terminal.

By the way, as the data processing section 3, C-MO3 (Co
mplementary Metal Qxide S
This C-MO3 IC has a bare structure similar to that in a DIP (dual in-line package), and is compatible with PNP and NPN types. It has a circuit configuration using FETs (field effect transistors). For this reason, if the potential of the signal line becomes abnormally higher than the potential of the power supply line or abnormally lower than the potential of the grounding line, the power supply will be disconnected from the power supply ground via C-MO3 unless the power is turned off. A so-called latch-up phenomenon occurs in which current constantly flows to the ground wire, and the C-MOS
will be thermally destroyed.

Normally, DIP type ICs are provided with protection circuits around them as necessary, and prevent C-M due to latch-up phenomenon.
To prevent O3O thermal damage, even in the case of an IC card, a protection circuit is provided in the data processing unit 3 at the front stage of the processing system for clock pulses and reset pulses (hereinafter collectively referred to as drive pulses). ing.

FIG. 5 is a circuit diagram showing a drive pulse transmission system from an external terminal to an input stage of the data processing unit 3, in which 5 is an external terminal, 6 is a signal line, 7 is a stray capacitance, 8 is a protective resistor, and 9 is M.O.
S transistor, IO is the gate, 11 is the data processing section 3
This is the input terminal of

In the figure, the data processing section 3 is on the right side from the broken line A-A', and drive pulses from the terminal are supplied from the input terminal 11 to the data processing section 3 via the signal line 6 from the external terminal 5. In the data processing section 3, this driving pulse is applied to the protective resistor 8. The signal is supplied to a predetermined processing circuit (not shown) via a gate 10.

Here, a MOS transistor 9 is provided between the input side of the gate 10 and the ground terminal (this is the connection line mentioned above), and this MOS transistor 9 prevents the latch-up phenomenon from occurring. That is, as explained earlier, if the signal line 6 becomes at an abnormal potential for some reason, the resulting current flows into the ground line through the MOS transistor 9, and this current does not flow into the processing circuit through the gate 10. do it like this. This can prevent latch-up phenomena.

On the other hand, when an abnormal voltage is applied to a MOS transistor, dielectric breakdown occurs in its oxide layer. The breakdown voltage of the oxide layer of currently used MOS transistors is 100 to 20
0■, and in the packaged data processing section 3,
A protective resistor 8 is provided between the input terminal 11 and the gate 10 so that a withstand voltage of 500 cm is obtained.

In FIG. 5, stray capacitance 7 is generated between signal line 6 and ground line (not shown).

[Problem that the invention seeks to solve]

Incidentally, an IC card having such a structure is kept for a much longer time than it is to be used by being attached to a terminal. Moreover, since IC cards are compact, they are often kept in clothing pockets, and in this case, the IC card is susceptible to static electricity when it comes into contact with clothing. This static electricity can reach as high as 1,500V, and when such a high voltage is generated on the signal line 6, a large current flows through the MOS transistor 9, charging its MO3 capacitance, and the oxide layer is charged. A voltage higher than the withstand voltage will be generated and the MOS transistor will be destroyed. For this reason, the latch-up phenomenon in the data processing section 3 cannot be prevented.

To solve this problem, diodes are installed between the signal line, the power line, and between the signal line and the ground line, so that when static electricity occurs on the signal line, the abnormal current is transferred to the power line and the ground line through these diodes. However, since diodes have a small current capacity, they are easily destroyed by such abnormal currents. Therefore, it has been proposed to use a bipolar transistor with a large current capacity instead of a diode (Japanese Patent Application Laid-Open No. 57-1999).
115854), the circuit configuration becomes complicated, and if static electricity of about 1500V is generated, the bipolar transistor will also be destroyed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an IC card that solves this problem and improves anti-static characteristics with a simple configuration.

[Means to solve the problem]

To this end, the present invention sets the impedance of the signal line within a predetermined range, and provides M
The present invention is characterized in that the amount of charge charged in the MOS capacitor of the OS transistor is reduced, and the voltage associated with the charge can be limited to a withstand voltage of the MOS transistor or less.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a main part showing an embodiment of an IC card according to the present invention, 12 is an additional resistor, and parts corresponding to those in FIG. 4 are given the same reference numerals.

In FIG. 1, an additional resistor 12 having a predetermined resistance value is provided between the external terminal 5 and the data processing section 3, and this and the stray capacitance 7 serve as the impedance of the signal line 6. Here, the resistance value of the protective resistor 8 is R, the equivalent resistance when the MOS transistor 9 is turned on is R1, and the resistance value of the additional resistor 12 is RP+signal line 6.
Assuming that the capacitance value of the stray capacitance 7 is C1, the equivalent circuit of FIG. 1 including the static electricity source becomes as shown in FIG. 2. In the figure, the capacitor 14 and the switch 13 constitute a static electricity source, and closing the switch 13 means that static electricity has been generated in the signal line 6. Here, the capacitance value of the capacitor 14 is assumed to be 00. In addition, 15 is the protective resistor 8 in Figure 1.
and the resistance of the MOS transistor 9 when it is on, and the combined resistance value R is (RI+RIB).

In this equivalent circuit, when the voltage of static electricity generated in the capacitor 14 is vo, and the switch 13 is closed, the capacitor 14 is instantaneously discharged into the stray capacitance 7, and the voltage across these terminals V, becomes, and then, The following current i flows through the resistor 15, that is, the MOS transistor 9 (FIG. 1).

oVa (R+Rp)(Co+Cs) When the MOS transistor 9 is damaged by static electricity, if the threshold current for this static electricity damage is i, as shown in FIG.
The amount of charge Q stored in the OS transistor 9 becomes a problem, and when its MOS capacitance is CM + the breakdown voltage threshold is V, in order for the MOS transistor 9 not to be destroyed, Q<C3-V (= CH)・・・・・・・・・・・・
...It must be (2).

Therefore, the time t0 at which the current i shown in equation (1) becomes equal to the threshold current ith becomes t mr ·In (IP / 1th), and the electricity i1Q becomes th.

On the other hand, since C, = 600-9009F, Vth = about 100V, Q = 60000-90000pC, Co = 100 pF, Vo = 1500 VR-
If the resistance value R2 of the additional resistor 12 is selected to be 1 to 3 Ω, then from the above formula (3), Q = 52300 pC (Rr- From equation (2), Cvi# 900 p
In the case of F, if an additional resistor 12 of approximately Ω or more is provided on the signal line, and in the case of CM#600 pF,
If an additional resistor 12 of approximately Ω or more is provided to 3, the voltage will be 500V.
MOS transistor 9
It can be seen that it is possible to protect

In addition, if the additional resistor 12 is not provided, (RP-〇)
, if the capacitance value C3 of stray capacitance 7 is selected to be 50 to 120 pF, then Q=57800pC (Cs=120pF) to 76800
pC(Cs-50pF), which can be calculated from equation (2) and similarly protects the MOS transistor 9 against static electricity up to about 1500V. The capacitance value C8 of the floating capacitance M7 is determined by the length E of the signal line 6 on the insulating substrate 2 (FIG. 3) and the length E of the signal line 6. Since it is determined by the ratio to the distance d between the ground lines, it is easy to set the capacitance value C3 as described above depending on the wiring pattern of the signal line 6 on the insulating substrate 2.

In the above, static electricity prevention is achieved by selecting the values of the additional resistor 12 or the stray capacitance 7, but it is also possible to prevent static electricity by appropriately setting the respective values of the additional resistor 12 and the stray capacitance 7. In short, static electricity can be prevented by appropriately setting the impedance of the signal line.

Note that if the resistance value R2 of the additional resistor 12 and the capacitance value C1 of the stray capacitance 7 are increased, the current l becomes smaller, as is clear from equation (1), and the amount of charge Q stored in the Mo3 transistor 9 becomes This makes the static electricity prevention effect better, but on the other hand, the time constant of the signal line 6 becomes larger, and the rise and fall of the drive pulse becomes gentler, resulting in waveform rounding. From this, the resistance value RP and capacitance value C8 are too thick (cannot be made, and the amount of charge Q is
It is preferable to set the resistance value RF+required value C5 to be slightly smaller than 4.

〔Effect of the invention〕

As explained above, according to the present invention, even if very high voltage static electricity occurs, the M
The amount of charge stored in the o3 transistor can be reduced, and the M
Electrostatic damage to the OS transistor can be prevented and the electrostatic characteristics can be greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a main part showing an embodiment of an IC card according to the present invention, FIG. 2 is an equivalent circuit diagram thereof, and FIG.
Graph diagram 1 showing the amount of charge stored in the OS transistor
, FIG. 4 is a plan view showing the overall structure of the IC card, and FIG. 5 is a circuit diagram of the main part of the conventional IC card. l... Card body, 2... Board, 3.
...Data processing unit, 4...Data memory, 5...External terminal, 6...Signal line, 7
... Stray capacitance, 8... Protective resistance, 9.
...MOS transistor for latch-up prevention, 1
0...Gate, 12...Old...Additional resistance. Figure 1 to Figure 4 Figure 5

Claims (1)

[Claims] A nonvolatile data memory and a data processing section are provided on an insulating substrate, and signal lines are provided between the data processing section and a plurality of external terminals exposed to the outside. and
An IC in which a predetermined signal line to which a drive pulse is supplied from the external terminal among the signal lines is connected to a MOS transistor for latch-up prevention through a protective resistor in the data processing section.
In the card, the amount of charge Q accumulated in the MOS transistor by a current exceeding the threshold current of the MOS transistor flowing through the MOS transistor with the generation of static electricity is determined by the MOS capacitance C_M of the MOS transistor and the breakdown voltage. An IC card characterized in that the impedance of the predetermined signal line is set so that Q<C_M·V_t_h with respect to a threshold value V_t_h.