JPS61194781A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To increase drain withstanding voltage by forming a laminate with a T-shaped section to an eave shape and shaping a source electrode or a source region and a drain electrode or a drain region at a symmetric position while holding a gate electrode. CONSTITUTION:A semiconductor layer 3 is formed from the main surface 2 side in a semiconductor substrate 1, and a laminate 43 in which a layer 41 consisting of an insulating material, a conductive material, etc. and a layer 42 composed of an insulating material, a conductive material, etc. different from said materials, etc. are laminated is shaped. A mask layer 8 is formed into the laminate 43, and a laminate 43' is shaped through etching treatment. A mask layer 8' is removed, and a mask layer 50 and a mask layer 51 in a continuous manner onto the laminate 43', a side surface 44b and the semiconductor substrate 1 are formed simultaneously through evaporation treatment from the oblique upper section of the semiconductor substrate 1. A laminate 43'' is shaped through etching treatment. The mask layers 50 and 51 are dissolved and removed, and an asymmetric section T-shaped laminate 43''' is formed through etching treatment.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a method for manufacturing a field effect transistor.

2. Description of the Related Art Conventionally, as a method for manufacturing a field effect transistor, the method described below with reference to FIG. 3 has been proposed.

That is, a semiconductor substrate 1 having high resistance is prepared in advance (FIG. 3A).

Then, an N-type semiconductor layer 3 having a predetermined width is formed in the semiconductor substrate 1 from the main surface 2 side by, for example, implanting N-type impurity ions (FIG. 3B).

Next, a laminate 6 is placed on the semiconductor substrate 1, in which a conductor layer 4 made of, for example, a metal material, which will later become a gate electrode, and a conductor layer 5 made of a different material are laminated in that order. is formed so as to form a Schottky junction 7 with the semiconductor layer 3 (FIG. 3C).

Next, a mask layer 8 made of, for example, photoresist is formed on the laminate 6, extending in a stripe shape across the semiconductor layer 3 in the width direction when viewed from above (FIG. 3D).

Next, by etching the laminate 6, a conductor layer 5' formed from the conductor layer 5 of the laminate 6 and having the same pattern as the mask layer 8, and a conductor layer 5' formed from the conductor layer 4.
The conductor layer 4' having a smaller pattern around the circumference than the conductor layer 5' forms a U-shaped laminate 6' with a T cross section in which the conductor layers 4' and 5' are laminated in this order (FIG. 3E). .

Next, the mask layer 8 is removed from above the T-shaped cross-sectional U-shaped stack 6', and then a semiconductor layer 3 is formed on the semiconductor substrate 1 with almost the same pattern as the semiconductor layer 3 formed thereon. A mask layer 10 made of, for example, photoresist is formed having a window 9 that exposes the surface to the outside (FIG. 3F).

Next, a conductive layer 11 is deposited on the T-section U-shaped stack 6' by vapor deposition of a conductive material from vertically above the semiconductor substrate 1 using the mask layer 10 and the T-shaped U-shaped stack 6' as a mask.
At the same time, the conductor layer 11 and the T-shaped laminate 6' are laminated to form a laminate 15 with a square cross section. Conductor layers 12 and 13 are formed at both sandwiched positions (see Fig. 3G).
). In this case, the conductor layers 11 to 13 are also formed on the mask layer 10.
A conductor layer 14 of the same material is formed.

Next, by dissolving the mask layer 10, the mask layer 10 is removed from the semiconductor substrate 1, and at the same time, the conductor layer 14 formed on the mask layer 10 is removed (see FIG. ).

As described above, the semiconductor layer 3 is used as an active layer, the T-shaped cross-sectional laminate 15 is used as a gate electrode forming a Schottky junction 7 with the semiconductor layer 3, and the conductor layers 12 and 13 are used as a source electrode and a drain, respectively. A field effect transistor used as an electrode is manufactured.

In addition, conventionally, as a manufacturing method for field effect transistors, the fourth
A method described below with accompanying figures has been proposed.

That is, the semiconductor substrate 1 similar to the case described above in FIG.
Prepare in advance (Figure 4A).

Therefore, inside the semiconductor substrate 1, from the main surface 2 side,
A semiconductor layer 3 similar to that described above in FIG. 3 is formed (
Figure 4B).

Next, a laminate 23 is formed on the semiconductor substrate 1, in which a layer 21 made of an insulating material, a conductive material, etc., and a layer 22 made of a different material are layered f1 in that order (FIG. 4). C
).

Next, a mask layer 8 similar to that described above in FIG. 3 is formed on the laminate 23 (FIG. 4D).

Next, by etching the laminate 23 using the mask layer 8 as a mask, a layer 22' formed from the layer 22 of the laminate 23 and having the same pattern as the mask layer 8, and a layer 22 formed from the layer 21 are etched. A layer 21' having a smaller pattern around the circumference than that of the layer 21' forms a cross-section T-shaped laminate 23' in which the layers 21' and 22' are laminated in this order (the fourth
Figure E).

Next, the mask layer 8 is removed from above the T-section U-shaped stack 23', and then a mask layer 1o having windows 9 similar to those described above in FIG. 3 is formed on the semiconductor substrate 1 ( Figure 4 F)
.

Next, the mask layer 10 and the NHtJi body 23' having a T-shaped cross section are formed.
A conductive layer 11 similar to that described in FIG. At the same time, the conductor layer 11 and the T-section U-shaped stack 23' are stacked to form a T-shaped stack 24,
Above, at both positions sandwiching the cross-section T-shaped laminate 24,
Conductor layers 12 and 13 similar to those described above in FIG. 3 are formed (FIG. 4G). In this case, the third layer is also placed on the mask layer 10.
A conductor layer 14 similar to that shown in the figure is formed.

Next, as in the case of FIG. 3, the mask layer 10 and the conductor layer 14 formed thereon are removed from the semiconductor substrate 1 (FIG. 4H).

Next, on the semiconductor substrate 1, a layer 25 made of, for example, a photoresist, in which the T-shaped cross-sectional laminated layer 24 and the conductor layers 12 and 13 are completely buried, is formed with a substantially flat upper surface. (Figure 4 I).

Next, by etching the layer 25 from above, the conductor layers 12 and 13 are buried from the layer 25, and the conductor layers 12 and 13 are buried below the top surface of the layer 21' of the T-shaped laminate 24 in cross section. Layer 2 of a U-shaped laminate 24 with a U-shaped cross section
a mask layer 25' with a window 26 defined by 1';
(Fig. 4 J).

Next, by dissolving the layer 21' of the laminate 24 having a square cross section, the layer 21' is removed from the semiconductor substrate 1, and the layer 22' and the conductor layer 11 formed on the FFJ 2i are removed. Finally, the T-shaped cross-section laminated layer 24 is removed from the semiconductor substrate 1 (FIG. 4K).

Next, a Schottky junction 27 is formed between the semiconductor layer 3 and the semiconductor layer 3 at a position facing the window 26 of the mask layer 25' on the semiconductor layer 3 from vertically above the semiconductor substrate 1, for example, by vapor deposition of a metal material. form the conductor IFi28 (
Figure 4L).

In this case, a conductor layer 29 made of the same material as the conductor M28 is also formed on the mask layer 25'.

Next, by dissolving the mask layer 25', the mask layer 25' is removed from the semiconductor substrate 1, and at the same time, the conductor layer 25' formed on the mask layer 25' is removed.
(Fig. 4 M).

As described above, the semiconductor layer 3 is an active layer, the conductor layer 28 is a gate electrode forming a Schottky junction 27 with the semiconductor layer 3, and the electric field is formed using the conductor layers 12 and 13 as a source electrode and a drain electrode, respectively. Manufacture effect transistors.

Furthermore, a method for manufacturing a field effect transistor, which will be described below with reference to FIG. 5, has also been proposed.

That is, a semiconductor substrate 1 similar to that described above in FIG. 3 is prepared in advance (Δ in FIG. 5).

Therefore, inside the semiconductor substrate 1, from the main surface 2 side,
A semiconductor layer 3 similar to that described above in FIG. 3 is formed (
Figure 5B).

Next, a conductor If! is placed on the semiconductor substrate 1. i31 and a layer 32 made of a conductive material or an insulating material different from it form a laminate 33 which is laminated in that order (fifth layer).
Figure C).

Next, a mask layer 8 similar to that described above in FIG. 3 is formed on the Wi layer suspension 3 (FIG. 5D).

Next, by etching the laminate 33 using the mask layer 8 as a mask, a layer 32' formed from the FVI 32 of the laminate 23 and having the same pattern as the mask layer 8 is etched.
and a layer 31' formed from the layer 31 and having a smaller pattern around the layer 32' than the layer 32'.
A cross-section T-shaped laminate 33' is formed by laminating in the order of (
Figure 5F).

Next, the mask layer 8 is removed from above the T-section U-shaped stacked body 33' (FIG. 5F).

Next, a mask layer 10 having windows 9 similar to those described above in FIG. 3 is formed on the semiconductor substrate 1 (FIG. 5G).

Next, by implanting N-type impurity ions using the T-shaped cross-section U-shaped stack 33' and the mask layer 10 as masks, the semiconductor layer 3 is implanted at both positions with the T-shaped U-shaped stack 33' sandwiched therebetween. In this step, ion implantation regions 34 and 35 having a higher N-type impurity concentration than the semiconductor layer 3 are formed at a depth that reaches the semiconductor substrate 1 (FIG. 5('')).

Next, the layer 32' of the U-shaped laminate 33' with a T cross section is
Then, ion implantation regions 34 and 35 are activated by heat treatment to form semiconductor regions 36 and 37 having a high N-type impurity concentration (FIG. 5I).

Next, conductor layers 36 and 37 are formed on the semiconductor regions 36 and 37, respectively, using a mask layer (not shown) having a window that exposes them to the outside (FIG. 5J).

As described above, the semiconductor layer 3 is an active layer, the conductor layer 31 is a gate electrode in ohmic contact with the semiconductor layer 3, the semiconductor regions 36 and 37 are a source region and a drain region, respectively, and the conductor layers 36 and 37 are a source region, respectively. A field effect transistor having electrodes and drain electrodes is manufactured.

The above is the conventionally proposed method for manufacturing a field effect transistor.

According to such a conventional manufacturing method of a field effect transistor, a first layer (conductor layer 4' in the case of FIG. 3, layer 4' in the case of FIG. 4) having a gate electrode pattern is formed on the semiconductor/body substrate 1. 2
1', conductor layer 31' in the case of FIG. A second layer (conductor layer 5' in the case of FIG. 3, layer 22' in the case of FIG. In the case of FIG. 5, a T-shaped laminate with a T-shaped cross section (layer 6' in FIG. 3, and in the case of FIG. A process of forming a laminate 23' (in the case of FIG. 5, a laminate 33') and a deposition process using the above-described T-shaped laminate in cross section as a mask on the semiconductor substrate 1 (in the case of FIGS. 3 and 4). ) and an ion implantation process (in the case of FIG. 5) to manufacture a field effect transistor.

Problems to be Solved by the Invention However, in the conventional manufacturing method of the field effect transistor described above, the above-mentioned T-cube-shaped stacked body has a symmetrical cross-section with respect to the center line of its vertical extension. Therefore, the source electrode or source region and the drain electrode or drain region are formed at symmetrical positions with the gate electrode in between.

For this reason, all of the conventional methods for manufacturing field effect transistors described above have the disadvantage that the field effect transistors are manufactured with low drain breakdown voltage and high drain conductance.

By means of solving the problem, the present invention seeks to propose a new method for manufacturing field effect transistors, which does not have the above-mentioned drawbacks.

The method for manufacturing a field effect transistor according to the present invention is shown in FIG.
As in the case of the conventional field effect transistor manufacturing method described above with reference to FIGS. 4 and 5, a first layer having a pattern of a gate electrode is formed on a semiconductor substrate, and a first layer is formed on the first layer. A first side end surface that determines the end surface of the drain electrode or drain region on the gate electrode side; and a second side end surface that is opposite to the first side end surface that determines the end surface of the source electrode or source region on the gate electrode side. a step of forming a T-shaped laminate with a T-shaped cross section extending in a stripe shape, and a deposition treatment on the semiconductor substrate using the T-shaped laminate with the T-shaped cross-section as a mask; A field effect transistor is manufactured for ¥J including processes such as ion implantation.

However, the electric field effects 1 to 1 according to the first invention of the present application
A method for manufacturing a transistor is that in the method for manufacturing a field effect transistor described above, a third layer, which becomes the first layer after W4 and has the same pattern as the second layer of the T-cube-shaped stacked body in cross section, is formed on the semiconductor substrate. and the second layer of the T-shaped cross-sectional U-shaped laminate are laminated in that order to form an N-sided U-shaped laminate, and a vapor deposition process from diagonally above the semiconductor substrate. On the semiconductor substrate, the cross section I
A first mask layer extending from a position away from the first side surface of the U-shaped laminate to the side opposite to the side of the U-shaped laminate in the above section I; 1 Continuously on the second side surface of the U-shaped laminate opposite to the first side surface and on the semiconductor substrate, on the semiconductor substrate, the cross section I is on the side opposite to the U-shaped laminate side. a step of simultaneously forming an extending second mask layer; and a first etching process for the third layer of the cross-section 1 U-shaped laminate using the first and second mask layers as masks. , a step of forming an inverted U-shaped laminate in cross section, in which a fourth layer formed from the third layer and which becomes the first layer, and the second layer are laminated in that order; , by removing the first and second mask layers, and performing a second etching process on the fourth layer of the inverted cross-section U-shaped laminate using the second layer as a mask, the fourth layer is removed. From layer to layer 1
An asymmetric cross section T in which the first layer formed in a small pattern around the periphery and the second layer are laminated in that order.
forming the asymmetrical T-shaped cross-section U-shaped laminate as the f15 layered body having a T-shaped cross section.

Further, the method for manufacturing a field effect transistor according to the second invention of the present application is such that, in the method for manufacturing the field effect transistor described above, the same pattern as that of the second layer of the T-shaped cross-sectional laminate is formed on the semiconductor substrate. forming a cross-section I U-shaped laminate in which a third layer that later becomes the first layer and the second layer of the T-CUT U-shaped laminate are laminated in that order; By vapor deposition treatment from diagonally above the semiconductor substrate, the semiconductor substrate has the cross section 1 extending from a position away from the first side surface of the U-shaped laminate to the side opposite to the U-shaped laminate side. The first mask layer is continuous on the cross-section I U-shaped stack, on the second side surface of the cross-section I U-shaped stack opposite to the first side surface, and on the semiconductor substrate. a step of simultaneously forming on the semiconductor substrate a second mask layer extending in the cross section opposite to the side of the U-shaped laminate; and the first and second mask layers;
and removing the first and second mask layers by etching the third layer of the cross-section I U-shaped laminate using the second layer as a mask, and removing the third layer from the third layer. forming an asymmetric cross-section T-shaped laminate in which the first layer formed in a pattern one circumference smaller than the first layer and the second layer are laminated in that order; A U-shaped laminate with a T cross section is formed as the above-described T U-shaped laminate with a T cross section.

Effects and Effects According to the method for manufacturing a field effect transistor according to the first aspect of the present invention, since the U-shaped stacked body with a T cross section is formed vertically, the source electrode or source region and the drain electrode or drain region are separated. are formed at symmetrical positions with the gate electrode in between, so that the field effect transistor is
Compared to the conventional manufacturing method of the field effect transistor described above with reference to FIGS.

Example 1 Next, an example of the method for manufacturing a field effect transistor according to the first invention of the present application will be described with reference to FIG.

The method for manufacturing a field effect transistor according to the first invention of the present application shown in FIG. 1 includes the following sequential steps to manufacture a field effect transistor.

That is, a semiconductor substrate 1 similar to that described above in FIG. 3 is prepared in advance (FIG. 1A).

Therefore, inside the semiconductor substrate 1, from the main surface 2 side,
A semiconductor layer 3 similar to that described above in FIG. 3 is formed (
Figure 1B).

Next, on the semiconductor substrate 1, a layer 41 made of an insulating material, a conductive material, etc., and a layer 42 made of a different insulating material, conductive copper, etc. are laminated in that order. 3
(Figure 1C).

Next, a mask layer 8 similar to that described above in FIG. 3 is formed on the laminate 43 (FIG. 1D).

Next, by etching the laminate 43 using the mask layer 8 as a mask, layers 41' and 42' having the same pattern as the mask layer 8 formed from the layers 41 and 42 of the laminate 43 are laminated in that order. has been,
Cross section 1 U-shaped laminate 4 having the same pattern as mask layer 8
3' (Fig. 1E).

Next, the mask layer 8' is dissolved away, and the cross-section 1 U-shaped laminate 43 is
Remove the mask layer 8' from above (FIG. 1F).

Next, a metal material such as A1 is deposited on the semiconductor substrate 1 from diagonally above the semiconductor substrate 1.
A mask layer 50 extends from a position away from the side surface 44a of the cross-section I U-shaped laminated body 43' to the side opposite to the cross-section I U-shaped laminated body 43' side, and a cross-section ■-shaped &! On the single layer body 43',
Section 1 Continuously between the side surface 44b opposite the side surface 44a of the U-shaped laminate 43' and the semiconductor substrate 1, the cross section 1 extends to the side opposite to the U-shaped laminate 43' side on the semiconductor substrate 1. A mask layer 51 is formed at the same time (FIG. 1G).

Next, by etching the layer 41' of the cross-sectional laminate 43' using the mask layers 50 and 51 as masks, ff141''s and layer 42' are formed from the layer 41'.
and are laminated in that order.
(Fig. 1H).

Next, the mask layers 50 and 51 are removed by elution.
Figure 1).

Next, by etching the layer 41'' of the U-shaped laminate 43'' with an inverted cross section, the layer 41'' is etched using the layer 42' as a mask.
ff141'', which is formed into a pattern one circle smaller than ``FF141'''', and layer 42' are laminated in that order to form an asymmetrical cross-section T-shaped laminate 43'' (FIG. 1 J). In this manner, the above-described asymmetric cross-section T-cube-shaped laminate 43'' is formed as the above-described T-cube-shaped laminate in the conventional field effect transistor manufacturing method shown in FIGS. 3, 4, and 5. do.

Next, using the asymmetric cross-section T-shaped laminate 43''
By taking a process similar to the manufacturing method of the conventional field effect transistor described in FIG. 1, FIG. 4, or FIG. Figure 3, Figure 4 or Figure 5, depending on whether the
A field effect transistor similar to that described above in the figures is manufactured.

The above is an embodiment of the method for manufacturing a field effect transistor according to the first invention of the present application.

According to the method for manufacturing a field effect transistor according to the first invention of the present application, the above-described T-shaped stacked body with a T-shaped cross section is formed into the asymmetrical T-shaped stacked body 43'', so that the source electrode or the source region Since the gate electrode and the drain electrode or the drain region are formed at symmetrical positions with the gate electrode in between, the gate electrode has the characteristics described above in the operation/effect section.

Embodiment 2 Next, an embodiment of a field effect transistor according to the second invention of the present application will be described with reference to FIG.

The field effect transistor according to the second invention of the present application shown in FIG. 2 is manufactured as follows.

That is, a semiconductor substrate 1 similar to that described above in FIG. 3 is prepared in advance (FIG. 2A).

Then, a semiconductor layer 3 similar to that described above in FIG. 3 is formed in the semiconductor substrate 1 from the main surface 2 side (FIG. 2B).

Next, a laminate 63 is formed on the semiconductor substrate 1, in which a layer 61 made of an insulating material, a conductive material, etc., and an MB2 made of a different insulating material, a conductive material, etc. are laminated in that order. (Figure 2C).

Next, a mask layer 8 similar to that described above in FIG. 3 is formed on the laminate 63 (FIG. 2D).

Next, by etching the laminate 63 using the mask layer 8 as a mask, the grooves 61' and 62' formed from the layers 61 and 62 of the laminate 43 and having the same pattern as the mask layer 8 are formed in that order. A laminated tank layer body 63' having a single-shaped cross section and having the same pattern as the mask layer 8 is formed (FIG. 2E).

Next, the mask layer 8' is dissolved away, and the tank layer body 43 is shaped like a square in cross section.
Remove the mask layer 8' from above (FIG. 2F).

Next, a metal material such as AI is deposited on the semiconductor substrate 1 from diagonally above the semiconductor substrate 1.
Cross section■ letter shape fi! A mask layer 70 extending from a position away from the side surface 64a of the i-layer body 63' to the side opposite to the side of the tank layer body 63' having a straight-shaped cross section, and on the tank layer body 63' having a straight-shaped cross section; A side surface 64b opposite to the side surface 64a of the I-shaped cross-section tank layer body 63' is continuous with the semiconductor substrate 1, and a side surface opposite to the side surface 63' of the I-shaped cross-section tank layer body 63' is formed on the semiconductor substrate 1. At the same time, a mask layer 71 extending from the top to the bottom is formed (FIG. 2G).

Next, the mask layers 70 and 71 and the cross-section I U-shaped laminate 6
The mask layers 70 and 71 are removed by an etching process on the layer 61 of 3' using the groove 62' as a mask, and the layer 61'' is formed in a small pattern around the layer 61'. , l7i62' are laminated in that order to form an asymmetrical cross-section T-cuboid laminate 63'' (FIG. 1J).

Next, using the asymmetric cross-section T-shaped laminate 43''
3, 4, or 5, using the process similar to the conventional field effect transistor manufacturing method described above in FIG. 3, FIG. 4, or FIG. Field effects similar to (- produce transistors.

The above is an embodiment of the method for manufacturing a field effect transistor according to the second invention of the present application.

It is clear that the manufacturing method of the field effect transistor according to the first invention of the present application has the same excellent characteristics as the field effect transistor 1 to transistor according to the first invention of the present application described above in FIG. be.

In addition, in the above description, only a few examples have been described for each of the methods for manufacturing field effect transistors according to the first invention of the present application and the second invention of the present application, and various modifications may be made without departing from the spirit of the present invention. Variations and changes may be made.

[Brief explanation of the drawing]

FIG. 1 is a line cross-sectional view of sequential steps showing an embodiment of a method for manufacturing a field effect transistor according to the first invention of the present application. FIG. 2 is a line cross-sectional view of sequential steps showing an embodiment of a method for manufacturing a field effect transistor according to the second invention of the present application. FIG. 3, FIG. 4, and FIG. 5 are sectional views showing sequential steps, respectively, showing an example of a conventional method for manufacturing a field effect transistor. 1... Semiconductor substrate 2...
......Main surface 3 of semiconductor substrate...
...... Semiconductor layer 8 ......
...Mask layer /11,42.41', /1
2' , 41' ″ , ・・・・・・・・・・・・
...Layer 43.63 ......Laminated body 43', 6
3' ・・・・・・・・・・・・Single-shaped cross section 43
″・・・・・・Reverse section U-shaped laminate 43′ ″
, 63' ″ ・・・・・・・・・・・・Asymmetric cross section T-shaped laminated hole 448.44b ・・・・・・・・・・・・・・・Side 50.51.70 .71

Claims (1)

[Scope of Claims] 1. A first layer having a gate electrode pattern on a semiconductor substrate, and a drain electrode formed on the first shoulder or a first layer that determines the end surface of the drain region on the gate electrode side. 1
and a second layer having a side end surface opposite to the first side end surface that defines the end surface of the source electrode or the source region on the gate electrode side. and a step of performing a process such as a deposition process, an ion implantation process, etc. on the semiconductor substrate using the T-shaped cross-section stack as a mask. In the manufacturing method, on the semiconductor substrate, the first layer having the same pattern as the second layer of the T-shaped laminate in cross section;
and the second layer of the T-shaped cross-section laminate are laminated in that order to form an I-shaped laminate in cross-section, diagonally above the semiconductor substrate. A first layer extending from a position away from the first side surface of the I-shaped laminate to a side opposite to the I-shaped laminate is formed on the semiconductor substrate by a vapor deposition process from . a mask layer, on the I-shaped cross-section laminate, and the first layer of the I-shaped cross-section laminate;
a second mask layer extending on the semiconductor substrate to a side opposite to the I-shaped cross-sectional laminate side, continuously on a second side surface facing the side surface of the semiconductor substrate and on the semiconductor substrate; and a first etching process for the third layer of the I-shaped cross-sectional laminate using the first and second mask layers as masks. forming an inverted L-shaped laminate in cross section, in which a fourth layer, which will later become the first layer, and the second layer are laminated in that order; and the first and second masks. By removing the layer, and performing a second etching process on the fourth layer of the inverted L-shaped cross-sectional laminate using the second layer as a mask, the fourth layer is removed by one circle from the fourth layer. forming an asymmetric cross-section T-shaped laminate in which the first layer formed in a small pattern and the second layer are laminated in that order; A method for manufacturing a field effect transistor, characterized in that the body is formed as the above-mentioned T-shaped laminate in cross section. 2. A first layer having a gate electrode pattern on a semiconductor substrate, and a first layer that determines the end surface of the drain electrode or drain region on the gate electrode side formed on the first layer.
and a second layer having a side end surface opposite to the first side end surface that defines the end surface of the source electrode or the source region on the gate electrode side. and a step of performing a process such as a deposition process, an ion implantation process, etc. on the semiconductor substrate using the T-shaped cross-section stack as a mask. In the manufacturing method, on the semiconductor substrate, the first layer having the same pattern as the second layer of the T-shaped laminate in cross section;
and the second layer of the T-shaped cross-section laminate are laminated in that order to form an I-shaped laminate in cross-section, diagonally above the semiconductor substrate. A first layer extending from a position away from the first side surface of the I-shaped laminate to a side opposite to the I-shaped laminate is formed on the semiconductor substrate by a vapor deposition process from . a mask layer, on the I-shaped cross-section laminate, and the first layer of the I-shaped cross-section laminate;
a second mask layer extending on the semiconductor substrate to a side opposite to the I-shaped cross-sectional laminate side, continuously on a second side surface facing the side surface of the semiconductor substrate and on the semiconductor substrate; and etching the first and second mask layers and the third layer of the cross-sectional I-shaped laminate using the second layer as a mask. The second mask layer is removed and the third layer is formed into a pattern one circle smaller than the third layer, and the first layer and the second layer are laminated in that order. A method for manufacturing a field effect transistor, comprising the step of forming a laminate with a T-shaped cross section, the asymmetrical T-shaped laminate being formed as the T-shaped laminate.