JPH0715913B2 - Manufacturing method of field effect transistor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a field effect transistor.

[Prior Art] As a method for manufacturing a field effect transistor, the following method has been conventionally proposed with reference to FIG.

That is, the semiconductor substrate 1 having high resistance is prepared in advance (FIG. 3A).

Then, an N-type semiconductor layer 3 having a predetermined width is formed in the semiconductor substrate 1 from the main surface 2 side, for example, by implanting N-type impurity ions (FIG. 3B).

Next, on the semiconductor substrate 1, a laminated body 6 in which a conductor layer 4 made of, for example, a metal material, which will be the gate electrode after that, and a conductor layer 5 made of a material different from the conductor layer 4 are laminated in that order, is formed. To form a Schottky junction 7 with the semiconductor layer 3 (FIG. 3C).

Next, a mask layer 8 made of, for example, a photoresist that extends in a stripe shape across the semiconductor layer 3 in the width direction when viewed from above is formed on the stacked body 6 (FIG. 3D).

Next, by etching the laminated body 6, a conductor layer 5 ′ having the same pattern as the mask layer 8 formed from the conductor layer 5 of the laminated body 6 and a conductor layer 4 are formed.
The conductor layer 4'having a pattern that is one size smaller than the conductor layer 5'forms a laminated body 6'having a T-shaped cross section in which the conductor layers 4'and 5'are laminated in this order (FIG. 3E). .

Next, the mask layer 8 is removed from the T-shaped laminate 6 ′ in cross section, and then the semiconductor layer 3 is formed on the semiconductor substrate 1 so as to have substantially the same pattern as the semiconductor layer 3 formed therein. A mask layer 10 made of, for example, a photoresist having a window 9 for exposing the film to the outside is formed (FIG. 3F).

Next, the conductor layer 11 is formed on the T-shaped cross-section stack 6'by vapor deposition of a conductive material from above the semiconductor substrate 1 vertically using the mask layer 10 and the T-shaped cross-section stack 6'as a mask. And a conductor layer 11 and a T-shaped laminate 6 ′ in cross section are laminated to form a T-shaped laminate 15 in cross section, and at the same time, the T-shaped laminate 15 in cross section is sandwiched on the semiconductor layer 3. In both positions,
Conductor layers 12 and 13 are formed (FIG. 3G). In this case, the conductor layer 14 made of the same material as the conductor layers 11 to 13 is also formed on the mask layer 10.

Next, by removing the mask layer 10, the mask layer 10 is removed from the semiconductor substrate 1, and at the same time, the conductor layer 14 formed on the mask layer 10 is removed (FIG. 3H). ).

As described above, the semiconductor layer 3 is the active layer, the T-shaped cross-section laminate 15 is the gate electrode forming the Schottky junction 7 with the semiconductor layer 3, and the conductor layers 12 and 13 are the source electrode and the drain, respectively. A field effect transistor having an electrode is manufactured.

In addition, conventionally, as a method of manufacturing a field effect transistor,
The method described below with reference to the drawings has also been proposed.

That is, the semiconductor substrate 1 similar to the case described above in FIG.
Are prepared in advance (FIG. 4A).

Then, in the semiconductor substrate 1, the semiconductor layer 3 similar to the case described above with reference to FIG. 3 is formed from the main surface 2 side (FIG. 4B).

Next, on the semiconductor substrate 1, a layered body 23 in which a layer 21 made of an insulating material, a conductive material and the like and a layer 22 made of a different material are laminated in that order is formed (FIG. 4C). ).

Next, the mask layer 8 similar to that described above with reference to FIG. 3 is formed on the stacked body 23 (FIG. 4D).

Next, the layer 23 of the stacked body 23 is formed by etching the stacked body 23 using the mask layer 8 as a mask.
A layer 22 'having the same pattern as the mask layer 8 and a layer 21' having a pattern slightly smaller than the layer 22 'formed from the layer 21 are laminated in this order on the layers 21' and 22 '. The letter-shaped laminate 23 'is formed, and then the mask layer 8 is removed from the T-shaped laminate 23' in cross section (Fig. 4E).

Next, a mask layer 10 having a window 9 similar to that described above with reference to FIG. 3 is formed on the semiconductor substrate 1 (FIG. 4F).

Next, by a vapor deposition process of a conductive material from above the semiconductor substrate 1 vertically using the mask layer 10 and the T-shaped laminated body 23 'as a mask, the T-shaped laminated body 23' shown in FIG. A conductor layer 11 similar to the one described above is formed, and the conductor layer 11 and the section T
At the same time that a T-shaped laminated body 24 having a cross-section is formed by stacking with the L-shaped laminated body 23 ′, a T-shaped laminated body 24 having a T-shaped cross section is formed on the semiconductor layer 3.
Conductor layers 12 and 13 similar to those described above with reference to FIG. 3 are formed at both positions sandwiching (FIG. 4G). In this case, the conductor layer 14 similar to that in the case of FIG. 3 is also formed on the mask layer 10.

Next, the mask layer 10 and the conductor layer 14 formed thereon are removed from the semiconductor substrate 1 as in the case of FIG. 3 (FIG. 4H).

Next, on the semiconductor substrate 1, a T-shaped cross-section laminate 24 and a layer 25 made of, for example, photoresist in which the conductor layers 12 and 13 are completely embedded are formed as a layer having a substantially flat upper surface. (Fig. 4I).

Next, the conductor layer 12 and 13 are buried from the layer 25 by etching the layer 25 from above, but the T-shaped laminate 23 ′ having the T-shaped cross section is formed. A mask layer 25 'is formed having a top surface slightly below the top surface of layer 21' and having a window 26 defined by layer 21 'of T-shaped cross-section stack 24 (Fig. 4J).

Next, the layer 21 ′ of the T-shaped laminate 24 in cross section is removed by evaporation to remove the layer 21 ′ from the semiconductor substrate 1, and the layer 22 ′ and the conductor formed on the layer 21 ′. Layer 11
And finally, from the semiconductor substrate 1, a laminate having a T-shaped cross section is removed.
Remove 24 (Fig. 4K).

Next, the window 26 of the mask layer 25 'is formed on the semiconductor layer 3 from above the semiconductor substrate 1 by, for example, vapor deposition of a metal material.
A conductive layer 28 forming a Schottky junction 27 with the semiconductor layer 3 is formed at a position facing the surface (FIG. 4L).
In this case, the conductor layer 29 made of the same material as the conductor layer 28 is also formed on the mask layer 25 '.

Then, the mask layer 25 'is removed by melting away the mask layer 25' from the semiconductor substrate 1, and at the same time, the conductor layer 29 formed on the mask layer 25 'is removed (first step). (Fig. 4 M).

As described above, an electric field using the semiconductor layer 3 as an active layer, the conductor layer 28 as a gate electrode forming a Schottky junction 27 with the semiconductor layer 3, and the conductor layers 12 and 13 as a source electrode and a drain electrode, respectively. Manufacture effect transistors.

Further, conventionally, a method of manufacturing a field effect transistor, which will be described below with reference to FIG. 5, has also been proposed.

That is, the same semiconductor substrate 1 as described above with reference to FIG. 3 is prepared in advance (FIG. 5A).

Then, in the semiconductor substrate 1, the semiconductor layer 3 similar to the case described above with reference to FIG. 3 is formed from the main surface 2 side (FIG. 5B).

Next, on the semiconductor substrate 1, a conductor 33 and a layer 32 made of a conductive material or an insulating material different from the conductor layer 31 are laminated in this order to form a laminate 33 (FIG. 5C). .

Next, the mask layer 8 similar to that described above with reference to FIG. 3 is formed on the stacked body 33 (FIG. 5D).

Next, the laminated body 33 is formed from the layers 32 of the laminated body 23 by an etching process using the mask layer 8 as a mask.
A layer 32 'having the same pattern as the mask layer 8 and a conductor layer 31
And a conductor layer 31 'having a pattern smaller than the layer 32' by one layer, form a T-shaped laminated body 33 'in which the conductor layer 31' and the layer 32 'are laminated in this order (first (Fig. 5E).

Next, the mask layer 8 is removed from the T-shaped laminated body 33 'in cross section (FIG. 5F).

Next, a mask layer 10 having a window 9 similar to that described above with reference to FIG. 3 is formed on the semiconductor substrate 1 (FIG. 5G).

Next, the T-shaped laminated body 33 'and the mask layer 10 are used as a mask to implant N-type impurity ions in the semiconductor layer 3 at both positions sandwiching the T-shaped laminated body 33'. At a depth reaching the semiconductor substrate 1, ion implantation regions 34 and 35 having a higher N-type impurity concentration than the semiconductor layer 3 are formed (FIG. 5H).

Next, the layer 32 'of the T-shaped cross-section laminate 33' is removed from the conductor layer 31 ', and then the ion implantation regions 34 and 35 are activated by heat treatment to have a high N-type impurity concentration. The semiconductor regions 36 and 37 are formed (FIG. 5I).

Next, a conductor layer 38 is formed on the semiconductor regions 36 and 37 by using a mask layer (not shown) having a window exposing them to the outside.
And 39 respectively (Fig. 5J).

As described above, the semiconductor layer 3 is the active layer, the conductor layer 31 'is the gate electrode in ohmic contact with the semiconductor layer 3, the semiconductor regions 36 and 37 are the source and drain regions, and the conductor layers 38 and 39 are the conductor layers 38 and 39, respectively. A field effect transistor having a source electrode and a drain electrode is manufactured.

The above is the conventionally proposed method for manufacturing the field effect transistor.

According to the above-described conventional method for manufacturing the field effect transistor shown in FIGS. 3, 4 and 5, the first layer (the conductor layer 4'in FIG. 3) having the pattern of the gate electrode is formed on the semiconductor substrate 1. (Conductor layer 21 'in FIG. 4, conductor layer 31' in FIG. 5)
And a first side end face that determines a gate electrode side end face of the drain electrode or the drain region formed on the first layer, and a second side end face that determines a gate electrode side end face of the source electrode or the source region. Stripes having a second layer (a conductor layer 5'in FIG. 3, a layer 22 'in FIG. 4, a layer 32' in FIG. 5) having opposite second side end faces. The T-shaped laminated body extending in the direction of
A laminated body 6 ', a laminated body 23' having a T-shaped cross section in the case of FIG.
In the case of FIG. 5, a step of forming a laminated body 33 '), a deposition process using the above-mentioned T-shaped laminated body having a cross section on the semiconductor substrate 1 as a mask (in the case of FIGS. 3 and 4), ion implantation The field effect transistor is manufactured by including a process of performing the process (in the case of FIG. 5).

[Problems to be Solved by the Invention] In the case of the above-described conventional method for manufacturing a field effect transistor, the above-mentioned T-shaped laminated body having a cross-section is a T-shaped laminated body having a symmetrical cross-section with respect to the center line of its vertical extension. Since it is formed, the source electrode or the source region and the drain electrode or the drain region are formed at symmetrical positions with the gate electrode in between.

Therefore, in the case of the above-described conventional method for manufacturing a field effect transistor, each of them has a drawback that the field effect transistor is manufactured as a low drain breakdown voltage and a high drain conductance.

Therefore, the present invention proposes a novel method for manufacturing a field effect transistor without the above-mentioned drawbacks.

[Means for Solving the Problem] A method for manufacturing a field effect transistor according to the present invention is described in FIG.
As in the case of the conventional field effect transistor manufacturing method described above with reference to FIGS. 4 and 5, a first layer having a pattern of a gate electrode and a first layer formed on the first layer are formed on a semiconductor substrate. The first side end face that determines the end face of the drain electrode or the drain region on the gate electrode side and the first side end face that determines the end face of the source electrode or the source region on the gate electrode side.
Forming a cross-section T-shaped laminated body extending in a stripe shape having a second layer having a side end surface opposite to the above and a second layer having a second side end surface facing the cross section, and the cross section T with respect to the semiconductor substrate. A field effect transistor is manufactured including a step of performing a deposition process using the letter-shaped laminate as a mask, an ion implantation process, and the like.

However, in the method for manufacturing a field effect transistor according to the first invention of the present application, in the method for manufacturing a field effect transistor, the same pattern as that of the second layer of the T-shaped cross-section laminate is provided on the semiconductor substrate. A step of forming a laminate having an I-shaped cross section in which a third layer, which will be the first layer afterwards, and the second layer of the T-shaped laminate having the cross section are laminated in that order; A vapor deposition process obliquely above the substrate extends to the semiconductor substrate from a position away from the first side surface of the I-shaped cross section laminate to a side opposite to the I-shaped cross section laminate side. No. 1 mask layer, on the I-shaped cross-section laminate, and on a second side surface of the I-cross section laminate facing the first side surface.
A step of continuously forming a second mask layer on the semiconductor substrate, the second mask layer extending on the side opposite to the side of the I-shaped cross section laminated body, and the I-shaped cross section laminated A fourth etching process, which is formed from the third layer, to become the first layer by a first etching process using the first and second mask layers as a mask for the third layer of the body.
Forming a reverse L-shaped cross-section laminate in which the first layer and the second layer are stacked in that order; removing the first and second mask layers; The first layer formed in a pattern smaller than the fourth layer by one second by a second etching process using the second layer as a mask with respect to the fourth layer of the character-shaped laminate; Forming the asymmetrical T-shaped laminated body having the asymmetrical cross-section, wherein the second layer and the second layer are laminated in that order to form the asymmetrical T-shaped laminated body. .

The method for manufacturing a field effect transistor according to the second invention of the present application is the same as the method for manufacturing a field effect transistor described above, wherein the semiconductor substrate has the same pattern as the second layer of the T-shaped cross-section laminate. Forming a third layer to be the first layer and the second layer of the T-shaped cross-section laminated body in that order in the order of I-shaped laminated body; and the semiconductor substrate. By a vapor deposition process from diagonally above the first substrate extending from the position away from the first side surface of the I-shaped cross-section laminated body to the side opposite to the I-shaped cross-sectional laminated body side. Of the mask layer, the I-shaped cross-section laminated body, the second side surface of the I-shaped cross-section laminated body facing the first side surface, and the semiconductor substrate, On the side opposite to the side of the laminate having the I-shaped cross section on the semiconductor substrate Forming an extended second mask layer at the same time, and forming a mask with the first and second mask layers and the second layer for the third layer of the I-shaped cross-section stack. By the etching process
The first and second mask layers are removed, and the first layer formed in a pattern smaller than the third layer by a size smaller than that and the second layer are laminated in that order. And a step of forming a T-shaped laminated body having an asymmetric cross-section, the T-shaped laminated body having an asymmetric cross-section is formed as the T-shaped laminated body having a cross-section.

[Operation / Effect] According to the manufacturing method of the field effect transistor of the first invention of the present invention according to the present invention, since the T-shaped cross-section laminate is formed asymmetrically, the source electrode or the source region and the drain electrode or the drain are formed. Since the region and the region are formed at asymmetrical positions with the gate electrode sandwiched therebetween, the field-effect transistor is drained more than the conventional field-effect transistor manufacturing method described above with reference to FIGS. 3, 4, and 5. As a high withstand voltage and high drain conductance,
It can be manufactured.

[Embodiment 1] Next, an embodiment of a method for manufacturing a field effect transistor according to the first invention of the present application will be described with reference to FIG.

In the manufacturing method of the field effect transistor according to the first invention of the present application shown in FIG. 1, the field effect transistor is manufactured by taking the following sequential steps.

That is, the same semiconductor substrate 1 as described above with reference to FIG. 3 is prepared in advance (FIG. 1A).

Then, in the semiconductor substrate 1, the semiconductor layer 3 similar to the case described above with reference to FIG. 3 is formed from the main surface 2 side (FIG. 1B).

Next, on the semiconductor substrate 1, a layer 41 made of an insulating material, a conductive material or the like, and a layer made of a different insulating material, a conductive material, or the like
42 and 42 form a laminated body 43 which is laminated in that order (FIG. 1C).

Next, the mask layer 8 similar to that described above with reference to FIG. 3 is formed on the stacked body 43 (FIG. 1D).

Next, the layer 41 ′ having the same pattern as the mask layer 8 formed from the layers 41 and 42 of the laminate 43 is subjected to an etching process for the laminate 43 using the mask layer 8 as a mask.
And 42 'are stacked in that order. A laminated body 43 'having an I-shaped cross section having the same pattern as the mask layer 8 is formed (FIG. 1E).

Next, the mask layer 8 is melted away, and the mask layer 8 is removed from the I-shaped laminate 43 'in cross section (FIG. 1F).

Next, by performing a vapor deposition process of a metal material such as A1 from diagonally above the semiconductor substrate 1, a section I-shaped is formed on the semiconductor substrate 1 from a position away from the side surface 44a of the section I-shaped laminated body 43 '. Layer 50 extending to the side opposite to the laminated body 43 'side, the I-shaped laminated body 43' in cross section, and the I-shaped laminated body in cross section
A laminated body having an I-shaped cross section is continuously formed on the semiconductor substrate 1 on the side face 44b facing the side face 44a of 43 'and on the semiconductor substrate 1.
At the same time, the mask layer 51 extending to the side opposite to the 43 'side is formed (FIG. 1G).

Next, the mask layer for the layer 41 'of the I-shaped laminate 43' in cross section
Layer 4 is formed by an etching process using 50 and 51 as a mask.
A layer 41 ″ formed from 1 ′ and a layer 42 ′ are laminated in that order to form a laminated body 43 ″ having an inverted L-shaped cross section (FIG. 1H).

Next, the mask layers 50 and 51 are removed by melting (FIG. 1I).

Next, the layer 42 'for the layer 41''of the inverted L-shaped laminated body 43''in cross section
A layer 41 ″ formed in a pattern smaller than that of the layer 41 ″ by an etching process using as a mask,
Form a non-symmetrical T-shaped stack 43 with layers 42 'stacked in that order (FIG. 1J).

As described above, the above-mentioned asymmetrical T-shaped laminated body 43
Is formed as the above-described T-shaped cross-section laminated body in the conventional method for manufacturing a field effect transistor shown in FIGS. 3, 4, and 5.

Next, using the asymmetrical T-shaped laminate 43 in FIG.
Whether the layer 41 of the T-shaped laminate 43 having an asymmetrical cross section is formed of a metal material in advance by taking steps according to the conventional method for manufacturing a field effect transistor described above with reference to FIG. 4 or FIG. A field effect transistor similar to that described above with reference to FIG. 3, 4, or 5 is manufactured, depending on whether it is formed of an insulating material.

The above is the embodiment of the method for manufacturing the field effect transistor according to the first invention of the present application.

According to the method for manufacturing a field effect transistor according to the first aspect of the present invention, since the above-described T-shaped cross-section laminated body is formed in the asymmetrical T-shaped laminated body 43, the source electrode or the source region and Since the drain electrode or the drain region can be formed at an asymmetrical position with the gate electrode sandwiched therebetween, it has the characteristics described above in the section of action and effect.

[Embodiment 2] Next, an embodiment of the field effect transistor according to the second invention of the present application will be described with reference to FIG.

The field effect transistor according to the second invention of the present application shown in FIG. 2 is manufactured as follows.

That is, the same semiconductor substrate 1 as described above with reference to FIG. 3 is prepared in advance (FIG. 2A).

Then, in the semiconductor substrate 1, from the main surface 2 side to the third
The semiconductor layer 3 similar to the case described above in the figure is formed (second
(Figure B).

Next, on the semiconductor substrate 1, a layer 61 made of an insulating material, a conductive material, or the like, and a layer made of an insulating material, a conductive material, or the like different from the layer 61.
62 and 62 form a laminated body 63 which is laminated in that order (FIG. 2C).

Next, the mask layer 8 similar to that described above with reference to FIG. 3 is formed on the laminated body 63 (FIG. 2D).

Next, the layer 6 having the same pattern as that of the mask layer 8 formed from the layers 61 and 62 of the layered body 43 by etching the layered body 63 using the mask layer 8 as a mask.
The I-shaped laminated body 63 'having the same pattern as the mask layer 8 is formed by laminating 1'and 62' in that order (FIG. 2E).

Next, the mask layer 8 is melted away, and the mask layer 8 is removed from the I-shaped cross-section laminated body 43 '(FIG. 2F).

Next, a metal material such as A1 is vapor-deposited from obliquely above the semiconductor substrate 1, and the I-shaped section 63a is formed on the semiconductor substrate 1 from a position away from the side surface 64a of the I-shaped laminated body 63 '. Layer 70 extending to the side opposite to the laminated body 63 'side, the I-shaped laminated body 63' in cross section, and the I-shaped laminated body in cross section
A laminated body having an I-shaped cross section is continuously formed on the semiconductor substrate 1 on the side surface 64b facing the side surface 64a of 63 'and on the semiconductor substrate 1.
At the same time, the mask layer 71 extending to the side opposite to the 63 'side is formed (FIG. 2G).

Next, the mask layers 70 and 71 are removed by the same etching process for the mask layers 70 and 71 and the layer 61 ′ of the I-shaped cross-section laminate 63 ′ using the layer 62 ′ as a mask.
From 1 to 6 layers smaller than that
1 ″ and the layer 62 ′ are laminated in that order to form a T-shaped laminate 63 ″ having an asymmetrical cross section (FIG. 2H).

Next, using the asymmetrical T-shaped laminate 63 ″ in FIG.
Similar to the case of FIG. 1, the same steps as those of FIG. 3, FIG. 4, or FIG. 5 are performed by taking steps in accordance with the conventional field effect transistor manufacturing method described above with reference to FIG. 4 or FIG. To manufacture the field effect transistor.

The above is the embodiment of the method for manufacturing the field effect transistor according to the second invention of the present application.

It is obvious that the method for manufacturing the field effect transistor according to the second invention of the present application has the same excellent characteristics as the case of the field effect transistor according to the first invention of the present application described above with reference to FIG.

It should be noted that, in the above description, only a few examples of the respective methods of manufacturing the field effect transistor according to the first invention of the present application and the second invention of the present application are described, and various modifications are possible without departing from the spirit of the present invention. Could be modified or changed.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view in a sequential process showing an embodiment of a method for manufacturing a field effect transistor according to the first invention of the present application. FIG. 2 is a schematic cross-sectional view in a sequential process showing an embodiment of a method for manufacturing a field effect transistor according to the second invention of the present application. 3, 4, and 5 are schematic cross-sectional views in sequential steps, each showing an embodiment of a conventional method for manufacturing a field effect transistor. 1 ... Semiconductor substrate 2 ... Main surface of semiconductor substrate 1 ... Semiconductor layer 4, 4 ', 5, 5' ... Conductor layer 6 ... Laminated body 6 '... T-shaped cross-sectioned laminated body 7 ... Schottky junction 8 ... Mask layer 9 ... Window of mask layer 10 ... Mask layer 11, 12, 13, 14 ... Semiconductor layer 15 ... T-shaped cross-section laminate 21, 21 ', 22, 22'23 ...... Laminate 23 ', 24 ...... T-shaped cross-section laminate 25 ...... Layer 25' ...... Mask layer 26 ...... Window 27 ...... Schottky junction 28,29,31 ...... Conductor layers 32,32 '...... Layer 33 ... Laminated body 33 '... T-shaped cross-sectioned laminated body 34, 35 ... Ion implantation region 36, 37 ... Semiconductor region 41, 41', 41 ", 41, 42, 42 '... Layer 43 , 63 ... Laminated body 43 ', 63' ... I-shaped cross-section laminated body 43 "... Inverted L-shaped cross-section laminated body 43, 63" ... Asymmetrical T-shaped laminated body 44a, 44b ... Side surface 50 , 51, 70, 71 …… Mask layer

Claims (2)

[Claims] 1. A first layer having a pattern of a gate electrode on a semiconductor substrate, and a first side for defining an end face on the gate electrode side of a drain electrode or a drain region formed on the first layer. A cross section extending in a stripe shape having an end surface and a second layer having a source electrode or a first side end surface that defines the end surface of the source region on the side of the gate electrode and a second side end surface facing the first side end surface. A method of manufacturing a field effect transistor, comprising: a step of forming a T-shaped laminated body; and a step of performing, on the semiconductor substrate, a treatment such as a deposition treatment using the above-mentioned T-shaped laminated body in cross section as a mask, an ion implantation treatment, or the like. The second layer of the T-shaped cross-section laminated body on the semiconductor substrate
And a second layer of the T-shaped cross-section laminated body having the same pattern as that of the above-mentioned layer and the second layer of the T-shaped cross-section laminated body are laminated in that order. The step of forming and the vapor deposition process from diagonally above the semiconductor substrate are performed on the semiconductor substrate from a position apart from the first side surface of the I-shaped cross-section laminated body, which is opposite to the I-shaped cross-section laminated body side. A first mask layer extending to the side, on the I-shaped cross section laminate, on a second side surface of the I-section cross section facing the first side surface, and the semiconductor. A step of continuously forming a second mask layer on the semiconductor substrate, the second mask layer extending on the side opposite to the side of the I-shaped cross-section laminated body, which is continuous with the substrate; The first to the third layer
And the first mask formed from the third layer by the first etching process using the second mask layer as a mask.
Forming a layered product having a reverse L-shaped cross section in which the fourth layer to be a layer and the second layer are stacked in that order; and removing the first and second mask layers. And the fourth layer of the inverted L-shaped cross-section laminated body is subjected to a second etching process using the second layer as a mask to form a pattern smaller than the fourth layer by one size. The step of forming a T-shaped laminated body having an asymmetrical cross section, in which the first layer and the second layer are laminated in that order, the T-shaped laminated body having an asymmetrical cross section,
A method of manufacturing a field effect transistor, which is characterized in that it is formed as a V-shaped laminated body. 2. A first layer having a pattern of a gate electrode on a semiconductor substrate, and a first side for defining an end face on the gate electrode side of a drain electrode or a drain region formed on the first layer. A cross section extending in a stripe shape having an end surface and a second layer having a source electrode or a first side end surface that defines the end surface of the source region on the side of the gate electrode and a second side end surface facing the first side end surface. A method of manufacturing a field effect transistor, comprising: a step of forming a T-shaped laminated body; and a step of performing, on the semiconductor substrate, a treatment such as a deposition treatment using the above-mentioned T-shaped laminated body in cross section as a mask, an ion implantation treatment, The second layer of the T-shaped cross-section laminated body on the semiconductor substrate
And a second layer of the T-shaped cross-section laminated body having the same pattern as that of the above-mentioned layer and the second layer of the T-shaped cross-section laminated body are laminated in that order. The step of forming and the vapor deposition process from diagonally above the semiconductor substrate are performed on the semiconductor substrate from a position apart from the first side surface of the I-shaped cross-section laminated body, which is opposite to the I-shaped cross-section laminated body side. A first mask layer extending to the side, on the I-shaped cross section laminate, on a second side surface of the I-section cross section facing the first side surface, and the semiconductor. A step of simultaneously forming, on the semiconductor substrate, a second mask layer extending on the side opposite to the side of the I-shaped cross section laminated body on the substrate, and the first and second masks A layer and a mask for the second layer with respect to the third layer of the I-shaped cross section. The first and second mask layers are removed by the same etching process as described above, and the first layer and the second layer are formed in a pattern smaller than the third layer by one size. And a step of forming a T-shaped laminated body having an asymmetric cross section in which
A method of manufacturing a field effect transistor, characterized in that a V-shaped laminated body is formed as the T-shaped laminated body in cross section.