JPS61193464A - Marking method in inspection of semiconductor device - Google Patents

Marking method in inspection of semiconductor device

Info

Publication number
JPS61193464A
JPS61193464A JP60031557A JP3155785A JPS61193464A JP S61193464 A JPS61193464 A JP S61193464A JP 60031557 A JP60031557 A JP 60031557A JP 3155785 A JP3155785 A JP 3155785A JP S61193464 A JPS61193464 A JP S61193464A
Authority
JP
Japan
Prior art keywords
semiconductor device
defective
pressure
inspection
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60031557A
Other languages
Japanese (ja)
Inventor
Masayoshi Kitamura
北村 昌良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP60031557A priority Critical patent/JPS61193464A/en
Publication of JPS61193464A publication Critical patent/JPS61193464A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To put a specifically-shaped mark accurately and surely on a defective semiconductor device by a method wherein a pressure-sensitive setting color- developing coating is applied and dried on the upper surface of a semiconductor device and a pressure is applied onto the part of the coating when a defect is found in the device by inspection. CONSTITUTION:A photoresist 10 as a coating which develops a color and sets under a pressure is applied on the upper surface of a semiconductor device except for the part of a window 10a for wire bonding. The photoresist 10 employed herein is prepared by mixing microcapsules packed with a setting agent and a color developer in a liquid of photosensitive synthetic resin such as epoxy. After applied on the whole surface and dried, the photoresist is removed from the parts of windows 9a, 10a and all other similar windows by photoetching. Then, the wafer concerned is set in an inspecting apparatus and subjected to an inspection as to whether it is defective or not, and the part of a semiconductor device determined to be defective is hammered. As the result, the microcapsules are destructed in the hammered part, the setting agent and the color developer inside the capsules ooze out for coloring and set, and thus a mark 11 is formed on said part.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、例えば同一のウェハに複数形成した半導体装
置(分割後に半導体チップとなる。)を検査する際に、
検査結果が不良の場合に選別用のマークを付けるマーキ
ング方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is applicable to, for example, when inspecting a plurality of semiconductor devices formed on the same wafer (which become semiconductor chips after being divided).
The present invention relates to a marking method for attaching a mark for sorting when an inspection result is defective.

集積回路等の半導体装置は、その生産の過程に(従来技
術) おいて各種の検査が行われるが、この検査の1種として
、同時に複数個の半導体装置が形成された1枚のウェハ
を検査装置にセットして、その各半導体装置の電極に触
針(プローブ)を接触させ、各々の半導体装置の電気的
性能の良否を判別する検査がある。
Semiconductor devices such as integrated circuits are subjected to various inspections during the production process (prior art), and one type of inspection is to simultaneously inspect a single wafer on which multiple semiconductor devices are formed. There is an inspection in which the electrical performance of each semiconductor device is determined by setting it in a device and bringing a probe into contact with the electrode of each semiconductor device.

この検査では、不良品と判断された半導体装置にインキ
でマークを付けて、分割後の選別プロセスにおいて選別
できるようにしている。
In this inspection, semiconductor devices determined to be defective are marked with ink so that they can be sorted out in the sorting process after division.

ところが、この検査方法はインキを付着させるインカー
のインキ付着量の調整が困難で、マークした形状が不揃
いとなって選別が正確にできなくなる恐れがあり、また
インキが飛散して良品の半導体装置をも汚染させるとい
う問題がある。
However, with this inspection method, it is difficult to adjust the amount of ink adhered to the ink, and there is a risk that the marked shapes may become irregular, making it impossible to sort accurately.In addition, the ink may scatter, causing non-defective semiconductor devices to be rejected. There is also the problem of contamination.

(発明の目的) 本発明ばかがる点に鑑みて成されたもので、その目的は
、不良品の半導体装置に正確1」、つ確実に特定形状の
マークを付+Jることかでき、また良品を汚染させるこ
ともないようにしたマーキング方7 法を提(J(する
ごとである。
(Object of the Invention) The present invention has been made in view of the disadvantages of the present invention, and its purpose is to be able to accurately and reliably mark a defective semiconductor device with a specific shape; We propose a marking method that does not contaminate non-defective products.

(発明の構成) このために本発明のマーキング方法は、半導体装置の良
否を検査し、不良の場合にマークする方法において、感
圧硬化発色塗料を半導体装置の上面に電極部を残して塗
布乾燥させるプロセスと、その半導体装置の検査結果が
不良の場合にその半導体装置の上記塗料の部分に圧力を
印加するプロセスとを具備するようにしている。
(Structure of the Invention) For this purpose, the marking method of the present invention is a method for inspecting the quality of a semiconductor device and marking it if it is defective. and a process of applying pressure to the paint portion of the semiconductor device if the test result of the semiconductor device is defective.

(実施例) 以下、本発明の実施例について説明する。図ばその一実
施例を示すものである。本実施例は、その検査の対象を
、複数のLSI等の半導体装置が形成され、ワイヤボン
ディング用の電極を残して他の面を保護膜で覆うプロセ
スまでを完了したウェハとしている。
(Example) Examples of the present invention will be described below. The figure shows an example of this. In this embodiment, the inspection target is a wafer on which a plurality of semiconductor devices such as LSIs are formed, and the process of covering the other surfaces with a protective film except for wire bonding electrodes is completed.

第1図は、このようにして形成されたウェハの内のある
半導体装置のトランジスタ部分を示すものである。1は
p型の半導体基板(各半導体装置に共1ffll)、2
はn型のエピタキシャル成長層、3は高濃度のp型(p
”)の分離領域、4はnpn型のトランジスタ領域部分
で、4bはp型のヘース拡散領域、4eば高濃度のn型
(n+)のエミッタ拡散領域、4cはn型のコレクタ領
域、4aば高濃度のn型の埋込領域である。
FIG. 1 shows a transistor portion of a semiconductor device on a wafer formed in this manner. 1 is a p-type semiconductor substrate (1ffll for each semiconductor device), 2
3 is an n-type epitaxial growth layer, 3 is a high concentration p-type (p
4 is an npn type transistor region, 4b is a p type heath diffusion region, 4e is a high concentration n type (n+) emitter diffusion region, 4c is an n type collector region, 4a is a This is a high concentration n-type buried region.

5は酸化膜、6はヘース引出し電極、7はエミッタ引出
し電極、8はコレクタ引出し電極であり、その各々は、
当該半導体装置のアクティブ領域からl1itlれたワ
イヤボンディング領域にまで引き出されている。9は保
護膜であり、コレクタ引出し電極8のワイヤボンディン
グ領域8aにおける部分に窓9aか形成され、その電極
8の上記領域8aが露出している。他の電極6.7につ
いても同様にワイヤボンディング領域で露出するように
窓が形成されている(図示せず)。
5 is an oxide film, 6 is a Heath extraction electrode, 7 is an emitter extraction electrode, and 8 is a collector extraction electrode, each of which is as follows:
It is drawn out to a wire bonding region located at a distance from the active region of the semiconductor device. A protective film 9 has a window 9a formed in the wire bonding region 8a of the collector lead-out electrode 8, and the region 8a of the electrode 8 is exposed. Similarly, windows are formed for the other electrodes 6.7 so as to be exposed in the wire bonding area (not shown).

本実施例では、このような半導体装置の上面に、第2図
に示すように、上記ワイヤボンディング用の窓fOaの
部分を残して、圧力印加による発色硬化する塗料(感圧
硬化発色塗料)としてのフォトレジスト10を塗布する
。このフォトレジスト10には、硬化剤と発色剤(例え
ば黒色)を充填したマイクロカプセルをエポキシ等の感
光合成樹脂液に混合させたものを使用する。塗布に当た
っては、まず半導体装置の上面の全面に塗IHil、て
乾燥させた後、窓9a、10a及び他の全ての同様の窓
の部分をフォトエツチングにより目抜きする。
In this embodiment, as shown in FIG. 2, the window fOa for wire bonding is left on the top surface of such a semiconductor device, and a paint that is colored and hardened by applying pressure (pressure-sensitive hardening color paint) is applied. A photoresist 10 is applied. This photoresist 10 is made by mixing microcapsules filled with a curing agent and a coloring agent (for example, black) in a photosensitive synthetic resin liquid such as epoxy. In coating, first, the entire upper surface of the semiconductor device is coated with IHil and dried, and then the windows 9a, 10a and all other similar windows are cut out by photoetching.

そして、次にヰ★査装置にセットして、当該ウェハの良
否検査を行い、不良と判別された半導体装置部分に、ハ
ンマによって打撃を与える。この結果、打撃を与えられ
た部分は、第3図に示すように、そこにおけるマイクロ
カプセルが破壊されて、内部の硬化剤と発色剤が滲み出
て、その部分に特定の色(例えば黒色)が着色され、且
つ硬化して、そこにマーク11が付けられる。
Then, the wafer is placed in an inspection device to inspect the quality of the wafer, and parts of the semiconductor device determined to be defective are struck with a hammer. As a result, as shown in Figure 3, the microcapsules in the hit area are destroyed, and the curing agent and color former ooze out, giving the area a specific color (for example, black). is colored and cured, and a mark 11 is attached thereto.

このようにして、当該ウェハの各半導体装置についての
検査及び不良品への打撃が完了した後は、そのウェハを
覗り外して、上記硬化していないフォトレジスト部分を
溶剤(例えばエポキシに対する場合はアセトン、フロン
系の溶剤)により除去して、第4図に示すように、不良
品と判別された半導体装置上のマーク11のみが残るよ
うにする。
In this way, after each semiconductor device on the wafer has been inspected and any defective devices have been damaged, the wafer is removed and the uncured photoresist portion is removed using a solvent (for example, in the case of epoxy). As shown in FIG. 4, only the mark 11 on the semiconductor device determined to be defective remains as shown in FIG.

この結果、ハンマ部の可動部のδIN整は、ハンマが所
定の圧力を発揮するように調整するのみで済むので、そ
の作業が容易であり、またマーク11はハンマの先端の
打撃する部分の形状となるので、正確な形状となり、後
のプロセスでの良品と不良品との選別も確実に行われる
ようになる。
As a result, the adjustment of δIN of the movable part of the hammer part is easy because it is only necessary to adjust the hammer so that it exerts a predetermined pressure. As a result, the shape is accurate, and it is possible to reliably distinguish between good and defective products in the subsequent process.

(発明の効果) 以上から本発明によれば、不良品の半導体装置に正確且
つ確実に特定形状のマークを付けることができ、また良
品を汚染させることt)なく、よって従来のインキを使
用する場合に比較して、その取扱が容易となり、また良
品と不良品の選別も確実に行われるようになるという特
徴がある。
(Effects of the Invention) As described above, according to the present invention, it is possible to accurately and reliably mark a defective semiconductor device with a specific shape, without contaminating good products, and therefore, conventional ink can be used. Compared to conventional methods, handling is easier, and good and defective products can be reliably sorted.

【図面の簡単な説明】[Brief explanation of drawings]

第1乃至第4図は本発明のマーキングカ法を説明するた
めの半導体装置の一部の断面図である。 ■・・・半導体基板、2・・・エピタキシャル成長層、
3・・・分離領域、4・・・トランジスタ領域、5・・
・酸化膜、6〜8・・・電極、9・・・保護膜、10・
・・フォトレジスト、11・・・マーク。 特許出願人 新日本無線株式会社 代 理 人 弁理士  長尾常明 −へ 脈       脈 口      口 1寸 wK脈
1 to 4 are cross-sectional views of a portion of a semiconductor device for explaining the marking method of the present invention. ■...Semiconductor substrate, 2...Epitaxial growth layer,
3... Isolation region, 4... Transistor region, 5...
・Oxide film, 6-8... Electrode, 9... Protective film, 10.
...Photoresist, 11...mark. Patent applicant New Japan Radio Co., Ltd. Agent Patent attorney Tsuneaki Nagao - He pulse Pulse mouth Mouth 1 inch wK pulse

Claims (3)

【特許請求の範囲】[Claims] (1)、半導体装置の良否を検査し、不良の場合にマー
クする方法において、 感圧硬化発色塗料を上記半導体装置の上面に電極部を残
して塗布乾燥させるプロセスと、上記半導体装置の検査
結果が不良の場合に上記半導体装置の上記塗料の部分に
圧力を印加するプロセスとを具備することを特徴とする
マーキング方法。
(1) A method for inspecting the quality of a semiconductor device and marking it if it is defective, which includes a process of applying and drying a pressure-sensitive curing coloring paint on the top surface of the semiconductor device leaving an electrode portion, and an inspection result of the semiconductor device. and applying pressure to the paint portion of the semiconductor device when the semiconductor device is defective.
(2)、上記感圧硬化発色塗料が、硬化剤と特定の色の
発色剤を充填したマイクロカプセルを感光樹脂と混合し
たフォトレジストで成ることを特徴とする特許請求の範
囲第1項記載のマーキング方法。
(2) The pressure-sensitive curing coloring paint is made of a photoresist in which microcapsules filled with a curing agent and a coloring agent of a specific color are mixed with a photosensitive resin. marking method.
(3)、上記圧力を、ハンマの打撃により印加するよう
にしたことを特徴とする特許請求の範囲第1項記載のマ
ーキング方法。
(3) The marking method according to claim 1, wherein the pressure is applied by striking with a hammer.
JP60031557A 1985-02-21 1985-02-21 Marking method in inspection of semiconductor device Pending JPS61193464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60031557A JPS61193464A (en) 1985-02-21 1985-02-21 Marking method in inspection of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60031557A JPS61193464A (en) 1985-02-21 1985-02-21 Marking method in inspection of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61193464A true JPS61193464A (en) 1986-08-27

Family

ID=12334478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60031557A Pending JPS61193464A (en) 1985-02-21 1985-02-21 Marking method in inspection of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61193464A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008001997A1 (en) * 2006-06-28 2008-01-03 Jt Corporation Apparatus for marking and vision inspection of the semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008001997A1 (en) * 2006-06-28 2008-01-03 Jt Corporation Apparatus for marking and vision inspection of the semiconductor device

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