JPH036819A - Method for inspecting etching state and structure of pattern to be inspected - Google Patents

Method for inspecting etching state and structure of pattern to be inspected

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Publication number
JPH036819A
JPH036819A JP14178689A JP14178689A JPH036819A JP H036819 A JPH036819 A JP H036819A JP 14178689 A JP14178689 A JP 14178689A JP 14178689 A JP14178689 A JP 14178689A JP H036819 A JPH036819 A JP H036819A
Authority
JP
Japan
Prior art keywords
junction
electron beam
etching
inspected
induced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14178689A
Other languages
Japanese (ja)
Inventor
Toru Koyama
徹 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14178689A priority Critical patent/JPH036819A/en
Publication of JPH036819A publication Critical patent/JPH036819A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To quantitatively inspect the residual film state in a contact hole after etching by radiating a region to be etched with an electron beam, and detecting an electron beam induced current induced at a P-N junction. CONSTITUTION:An N-type diffused layer 7 is extended directly from under a contact hole 3, and a pattern to be inspected having electrode pads 8 is formed thereon. When a reverse bias is applied between the pad 8 and a silicon substrate 1 and the hole 3 is irradiated with an electron beam 4, electron-hole pairs 5 are induced in the vicinity of the P-N junction, drawn to regions, and detected by an ammeter 9 as an external current. The degree of the external current varying according to the residual film degree in the hole 3 can be quantitatively obtained by regulating an acceleration voltage of the beam 4, a current level of a sample, and a voltage application level of a variable power source 10, thereby accurately obtaining the residual film state.

Description

【発明の詳細な説明】 〔産業上の利用分計〕 この発明は、半導体装置の製造工程であるエツチング処
理後のエツチング状態の検査方法および被検査パターン
の構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Applications] The present invention relates to a method for inspecting an etching state after etching processing, which is a manufacturing process of a semiconductor device, and a structure of a pattern to be inspected.

〔従来の技術〕[Conventional technology]

第4図に、n型MO3+−ランジスタのコンタクトホー
ルのエツチング処理後の断面模式図を示す。
FIG. 4 shows a schematic cross-sectional view of the contact hole of the n-type MO3+- transistor after etching.

この図において、1はシリコン基板、2は前記シリコン
基板1上に形成された単層あるいは多層の無機ガラス族
、3は前記無機ガラス膜2にレジストをマスクとするエ
ツチングにより形成されたコンタクトホールを示す。
In this figure, 1 is a silicon substrate, 2 is a single layer or multilayer inorganic glass group formed on the silicon substrate 1, and 3 is a contact hole formed in the inorganic glass film 2 by etching using a resist as a mask. show.

コンタクトホール3では、次工程で形成する金属配線と
、シリコン基板1とをオーミック接合させなければなら
ないため、エツチング不足のために、コンタクトホール
3内部に−様な残膜が少しでも残っていると接合不良に
なってしまう。したがって、コンタクトホール3のエツ
チング状況の検査は非常に重要である。
In the contact hole 3, it is necessary to make an ohmic contact between the metal wiring to be formed in the next step and the silicon substrate 1. Therefore, if even a small amount of --like residual film remains inside the contact hole 3 due to insufficient etching, it is necessary to make an ohmic contact with the silicon substrate 1. This will result in poor bonding. Therefore, inspection of the etching condition of the contact hole 3 is very important.

従来、エツチング処理後のコンタクトホール3内部の検
査は、光学顕微鏡あるいは電子顕微鏡による上面からの
n察によって行っていた。光学顕微鏡の場合には、無機
ガラス膜2の残膜状況を色の変化から判断し、電子顕1
m鏡の場合には、コントラストの変化から判断していた
Conventionally, the inside of the contact hole 3 after the etching process has been inspected from above using an optical microscope or an electron microscope. In the case of an optical microscope, the remaining film condition of the inorganic glass film 2 is judged from the change in color, and then an electron microscope 1 is used.
In the case of the m-mirror, judgment was made based on changes in contrast.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記のような従来のエツチング状態の検査方法は、素子
の微細化に伴うコンタクトホール3径の縮小化およびア
スペク1−比の増大に対応できなくなってきており、コ
ンタク1−ホール3内の残膜状況を検査することは非常
に困難になってきている。
The conventional etching state inspection method described above is no longer able to cope with the reduction in the diameter of contact hole 3 and the increase in aspect ratio 1 due to the miniaturization of devices, and the remaining film inside contact hole 3 is It is becoming very difficult to inspect the situation.

この発明は、上記のような問題点を解消するためになさ
れたもので、エツチング後のコンタクトホール内部の残
膜状況を正確、かつ定量的に検査できる検査方法および
その検査に用いる被検査l<ターンの構造を得ることを
目的とする。
The present invention has been made to solve the above-mentioned problems, and includes an inspection method that can accurately and quantitatively inspect the state of remaining film inside a contact hole after etching, and an inspection method used for the inspection. The purpose is to obtain the structure of the turn.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係るエツチング状態の検査方法は、pn接合
を構成する拡散層上のエツチング処理が行われた領域に
、電子ビームを照射し、pn接合部にて誘起される電子
ビーム誘起電流を検出することにより、エツチング後の
残膜状態を検査するものである。
The etching state inspection method according to the present invention irradiates an etched region on a diffusion layer constituting a pn junction with an electron beam, and detects an electron beam induced current induced at the pn junction. This allows the state of the remaining film after etching to be inspected.

また、この発明に係る被検査パターンの構造は、pn接
合を構成し、被エツチング部直下から延長させた拡散層
上に電極パッドを形成したものである。
Further, the structure of the pattern to be inspected according to the present invention constitutes a pn junction, and electrode pads are formed on a diffusion layer extending from directly below the part to be etched.

〔作用〕[Effect]

この発明のエツチング状態の検査方法においては、pn
接合部にて誘起される電子ビーム誘起電流から残膜の程
度が検査されろ。
In the etching state inspection method of this invention, pn
The degree of residual film is inspected from the electron beam induced current induced at the junction.

また、この発明の被検査パターンの構造においては、拡
散層上の電極パッドを用いて電子ビーム誘起電流が検出
される。
Further, in the structure of the pattern to be inspected according to the present invention, the electron beam induced current is detected using the electrode pad on the diffusion layer.

〔実施例〕〔Example〕

まず、この発明の原理について説明する。 First, the principle of this invention will be explained.

第3図は電子ビームによってpn接合面に誘起される電
子−正孔対の様子を表したn型コンククトホールの断面
模式図であり、第3図(a)はコンタクトホールのエツ
チングが完全に行われている場合を示し、第3図(b)
はエツチングが不完全でコンタクトホール内部に残膜が
ある場合を示す。
Fig. 3 is a schematic cross-sectional view of an n-type contact hole showing the state of electron-hole pairs induced at the pn junction surface by an electron beam, and Fig. 3(a) shows that the etching of the contact hole has been completely etched. Figure 3(b) shows the case where this is done.
indicates a case where etching is incomplete and there is a residual film inside the contact hole.

これらの図において、1,2,3は第4図と同様のもの
を示し、4は電子ビーム、5はpn接合面近傍で誘起さ
れる電子−正孔対、6はエツチングの残膜を示す。
In these figures, 1, 2, and 3 are similar to those in Figure 4, 4 is an electron beam, 5 is an electron-hole pair induced near the pn junction, and 6 is a residual film from etching. .

Siに電子ビームを照射すると、3.75eV当たり一
対の電子−正孔対が発生する。拡散領域では、発生した
電子−正孔対は再結合してしまい、外部電流に寄与しな
い。一方、pn接合面近傍で発生した電子−正孔対は、
pn接合に逆バイアスを印加することにより、電子はn
領域へ、正孔はp領域へ分離して流れ、外部電流として
観測される。Si面に照射された電子ビームは、Sl内
部での吸収によりエネルギーを減衰しながらpn接合面
に達するが、第3図(b)のようにコントクトホール3
の内部に無機ガラスの残膜が存在すると、残膜を透過す
る際にエネルギーの減衰が有り、接合面で誘起される電
子−正孔対の発生程度が減少する。また、エツチングが
過剰に行われ、下地の81基板自体も若干エツチングさ
れれば、基板表面からpn接合面までの距離が短くなり
、pn接合面で誘起される電子−正孔対の発生程度は増
加する。このように、残膜の程度に応じてpn接合面近
傍で誘起される電子−正孔対の発生程度が変化すること
から、外部電流をg測することにより、残膜のレベルを
定量的に検査することができろ。
When Si is irradiated with an electron beam, one electron-hole pair is generated per 3.75 eV. In the diffusion region, the generated electron-hole pairs are recombined and do not contribute to external current. On the other hand, the electron-hole pair generated near the pn junction is
By applying a reverse bias to the pn junction, electrons
The holes flow separately into the p region and are observed as an external current. The electron beam irradiated onto the Si surface reaches the p-n junction surface while attenuating its energy due to absorption inside the silicon, but as shown in FIG. 3(b), the electron beam reaches the p-n junction surface.
If there is a residual film of inorganic glass inside, the energy is attenuated when passing through the residual film, and the degree of generation of electron-hole pairs induced at the bonding surface is reduced. Furthermore, if excessive etching is performed and the underlying 81 substrate itself is slightly etched, the distance from the substrate surface to the pn junction will become shorter, and the degree of generation of electron-hole pairs induced at the pn junction will be reduced. To increase. In this way, the degree of generation of electron-hole pairs induced near the pn junction surface changes depending on the level of the remaining film, so by measuring the external current in g, the level of the remaining film can be quantitatively determined. Can you test it?

以下、この発明の一実施例を図面について説明する。An embodiment of the present invention will be described below with reference to the drawings.

第1図はこの発明における最も基本的な被検査パターン
の構造および検査方法を示す図で、第1図(a)は断面
模式図、第1図(b)は、第1図(a)に対応した上面
パターン図である。
FIG. 1 is a diagram showing the most basic structure and inspection method of the pattern to be inspected in this invention. FIG. 1(a) is a schematic cross-sectional view, and FIG. It is a corresponding top pattern figure.

これらの図において、1〜5は第3図、第4図と同様の
ものを示し、7はn型拡散層、8はリンを拡散した多結
晶シリコンの電極パッド、9は電子ビーム誘起電流を検
出する電流計、10はpn接合に印加するバイアス電圧
を供給する可変電源装置を示す。
In these figures, 1 to 5 are similar to those in FIGS. 3 and 4, 7 is an n-type diffusion layer, 8 is a polycrystalline silicon electrode pad with phosphorus diffused, and 9 is an electrode pad for electron beam induced current. A detecting ammeter 10 indicates a variable power supply device that supplies a bias voltage to be applied to the pn junction.

まず、検査を行うために、第1図(a)に示すようにコ
ンタクトホール3の直下からn型拡散層7を延長させ、
その上に電極パッド8を有する被検査パターンを形成す
る。次いで、電極パッド8とシリコン基板1との間に逆
バイアスを印加し、コンタクトホール3に電子ビーム4
を照射すると、pn接合面近傍に電子−正孔対5が誘起
され、この電子−正孔対5は各々の領域に引き込まれ、
外部電流として電流計9にて検知される。この際、コン
タクトホール3内の残膜程度によって変化する外部電流
の程度は、電子ビーム4の加速電圧、試料電流のレベル
および可変電源装置10による電圧印加レベル等の調整
により定量的に求めることができ、残膜状況を正確に知
ることができる。
First, in order to perform the inspection, as shown in FIG. 1(a), the n-type diffusion layer 7 is extended from directly below the contact hole 3,
A pattern to be inspected having electrode pads 8 is formed thereon. Next, a reverse bias is applied between the electrode pad 8 and the silicon substrate 1, and an electron beam 4 is applied to the contact hole 3.
When irradiated with
It is detected by the ammeter 9 as an external current. At this time, the degree of external current that changes depending on the degree of film remaining in the contact hole 3 can be quantitatively determined by adjusting the accelerating voltage of the electron beam 4, the level of the sample current, the voltage application level by the variable power supply 10, etc. This allows you to accurately know the remaining film status.

また、この実施例では、電極パッド8にリンを拡散した
多結晶シリコン膜を使用しているが、リン拡散の多結晶
シリコン膜は、通常MO3型半導体装置のゲート配線材
として使用されており、デー1−配線形成工程は、通常
コンタクトホール3のエツチング工程以前に行われる。
Furthermore, in this embodiment, a phosphorus-diffused polycrystalline silicon film is used for the electrode pad 8, but a phosphorus-diffused polycrystalline silicon film is normally used as a gate wiring material for MO3 type semiconductor devices. Day 1 - The wiring forming step is normally performed before the contact hole 3 etching step.

したがって、第1図の被検査パターンの構造は、本番の
半導体装置の製造工程において、特に処理工程を追加す
ることなく、コンタクトホール3のエツチング工程以前
のマスクパターンを若干追加変更することにより、通常
の製造工程中で形成することができる。
Therefore, the structure of the pattern to be inspected in FIG. 1 can be obtained by making slight additional changes to the mask pattern before the contact hole 3 etching process in the actual manufacturing process of the semiconductor device, without adding any special processing steps. can be formed during the manufacturing process.

そのため、実際の製品基板内の空き領域に形成すること
が可能である。
Therefore, it is possible to form it in an empty area within an actual product substrate.

なお、上記実施例では、コンタクトホール3の1個を検
査対象とした最も基本的な構造の例を示したが、第2図
に示すような多数のコンタクトホール3を検査対象とし
てもよく、電子ビーム4の走査領域は任意に変更できろ
ため、コンタクトホール3の1つ1つにビームを照射し
て個々の検査をする乙ともできる。− また、このような被検査パターンを基板上に複数個形成
しておけば、基板面内の分布を採ることもできる。
In addition, in the above embodiment, an example of the most basic structure was shown in which one of the contact holes 3 was inspected, but a large number of contact holes 3 as shown in FIG. 2 may be inspected, and electronic Since the scanning area of the beam 4 can be changed arbitrarily, it is also possible to irradiate each contact hole 3 with the beam for individual inspection. - Furthermore, by forming a plurality of such patterns to be inspected on a substrate, it is possible to obtain a distribution within the plane of the substrate.

さらに、上記実施例と同様の方法および同様の被検査パ
ターンを使用して拡散層内部や、pn接合の近傍におけ
る結晶欠陥の発生程度を同時に評価することができる。
Furthermore, the degree of occurrence of crystal defects inside the diffusion layer and in the vicinity of the pn junction can be simultaneously evaluated using the same method and the same pattern to be inspected as in the above embodiment.

これば、結晶欠陥が存在すればそこにエネルギーの局在
準位が生じ、電子ビム4により誘起された電子−正孔対
5が捕捉されて外部電流を増加させることになる。した
がって、コンタクトホール3内のエツチングの残膜6の
程度が同じであれば、電流量から欠陥の発生程度を検出
することができる。
In this case, if a crystal defect exists, a local energy level is generated there, and the electron-hole pair 5 induced by the electron beam 4 is captured, thereby increasing the external current. Therefore, if the degree of the etching residual film 6 in the contact hole 3 is the same, the degree of occurrence of defects can be detected from the amount of current.

〔発明の効果〕〔Effect of the invention〕

この発明のエツチング状態の検査方法は、以上説明した
とおり、pn接合を構成する拡散層上のエツチング処理
が行われた領域に、電子ビームを照射し、pn接合部に
て誘起される電子ビーム誘起電流を検出することにより
、エツチング後の残膜状態を検査するので、微細な領域
に対してもpn接き部にて誘起される電子ビーム誘起電
流から、定量的、かつ正確に残膜程度を測定できるとい
う効果がある。
As explained above, the etching state inspection method of the present invention irradiates the etched region on the diffusion layer constituting the pn junction with an electron beam to detect the electron beam induced at the pn junction. Since the state of the remaining film after etching is inspected by detecting the current, the extent of the remaining film can be quantitatively and accurately determined from the electron beam induced current induced at the pn junction even in minute areas. It has the effect of being measurable.

また、この発明による被検査パターンに構造は、pn接
合を構成し、被エツチング部直下から延長させた拡散層
上に電極パッドを形成するだけなので、・特に処理工程
を追加することなく、エツチング工程以前のマスクパタ
ーンを若干変更するt!けで、空き領域に容易に形成で
き、上記検査方法の実施に最適である。
In addition, the structure of the pattern to be inspected according to the present invention constitutes a pn junction, and the electrode pad is simply formed on the diffusion layer extended from directly below the part to be etched. Change the previous mask pattern slightly! Therefore, it can be easily formed in a vacant area and is ideal for implementing the above inspection method.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の被検査パターンの構造および検査方
法の一実施例を示す図、第2図は被検査パターンの構造
の他の実施例を示す図、第3図はこの発明の基本原理を
示す断面模式図、第4図はエツチング処理後のコンタク
)・ホール部の断面模式図である。 図において、1はシリコン基板、2は無機ガラス膜、3
ばコンタクトホール、4は電子ビーム、5はpn接合面
近傍で誘起された電子−正孔対、6はエツチングの残膜
、7はれ型拡散層、8ば電極パッド、9は電流計、1o
は可変電源装置を示す。 なお、各図中の同一符号は同一または相当部分を示す。
FIG. 1 is a diagram showing an embodiment of the structure of the pattern to be inspected and the inspection method of the present invention, FIG. 2 is a diagram showing another embodiment of the structure of the pattern to be inspected, and FIG. 3 is the basic principle of the invention. FIG. 4 is a schematic cross-sectional view of the contact hole portion after etching treatment. In the figure, 1 is a silicon substrate, 2 is an inorganic glass film, and 3 is a silicon substrate.
4 is a contact hole, 4 is an electron beam, 5 is an electron-hole pair induced near the pn junction surface, 6 is a remaining film after etching, 7 is a flaky diffusion layer, 8 is an electrode pad, 9 is an ammeter, 1o
indicates a variable power supply. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

【特許請求の範囲】[Claims] (1)pn接合を構成する拡散層上のエッチング処理が
行われた領域に、電子ビームを照射し、前記pn接合部
にて誘起される電子ビーム誘起電流を検出することによ
り、エッチング後の残膜状態を検査することを特徴とす
るエッチング状態の検査方法。
(1) By irradiating the etched region on the diffusion layer constituting the pn junction with an electron beam and detecting the electron beam induced current induced in the pn junction, the remaining after etching can be removed. An etching state inspection method characterized by inspecting a film state.
(2)pn接合を構成し、被エッチング部直下から延長
させた拡散層上に電極パッドを形成したことを特徴とす
る被検査パターンの構造。
(2) A structure of a pattern to be inspected that constitutes a pn junction and is characterized in that an electrode pad is formed on a diffusion layer extending from directly below the portion to be etched.
JP14178689A 1989-06-02 1989-06-02 Method for inspecting etching state and structure of pattern to be inspected Pending JPH036819A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14178689A JPH036819A (en) 1989-06-02 1989-06-02 Method for inspecting etching state and structure of pattern to be inspected

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14178689A JPH036819A (en) 1989-06-02 1989-06-02 Method for inspecting etching state and structure of pattern to be inspected

Publications (1)

Publication Number Publication Date
JPH036819A true JPH036819A (en) 1991-01-14

Family

ID=15300130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14178689A Pending JPH036819A (en) 1989-06-02 1989-06-02 Method for inspecting etching state and structure of pattern to be inspected

Country Status (1)

Country Link
JP (1) JPH036819A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100478231B1 (en) * 2003-06-19 2005-03-23 한정호 Plastic glove and manufacturing method thereof
JP2010287778A (en) * 2009-06-12 2010-12-24 Shin Etsu Handotai Co Ltd Method of evaluating silicon substrate, and method of manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100478231B1 (en) * 2003-06-19 2005-03-23 한정호 Plastic glove and manufacturing method thereof
JP2010287778A (en) * 2009-06-12 2010-12-24 Shin Etsu Handotai Co Ltd Method of evaluating silicon substrate, and method of manufacturing semiconductor device

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