JPS63261843A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63261843A JPS63261843A JP9774987A JP9774987A JPS63261843A JP S63261843 A JPS63261843 A JP S63261843A JP 9774987 A JP9774987 A JP 9774987A JP 9774987 A JP9774987 A JP 9774987A JP S63261843 A JPS63261843 A JP S63261843A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- defective
- elements
- defective element
- semiconductor wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 42
- 230000002950 deficient Effects 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000005259 measurement Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 4
- 230000001419 dependent effect Effects 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 239000003550 marker Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
崖1」J■旧1氷肛
本発明は半導体装置の製造方法に関し、詳しくは半導体
ウェーハに多数の素子を形成し、その特性チェック後、
不良素子にマーキングする方法に関するものである。[Detailed Description of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a semiconductor device, in which a large number of elements are formed on a semiconductor wafer, and after checking their characteristics,
The present invention relates to a method for marking defective elements.
従来互技工
IC等の半導体装置の製造工程において、第7図に示す
ように、半導体ウェーハ(1)に多数の素子(2)(2
)・・・が形成されると、まずウェーハ状態で各素子(
2)(2)・・・の特性をチェックして不良素子(2a
)・・・にマーキングする。上記各素子(2)(2)・
・・の特性をチェックするに際しては、第8図に示すよ
うに、半導体ウェーハ(1)の全面に絶縁膜(3)を形
成して素子表面を保護した後、各素子(2)の測定電極
部分を窓明けし、この窓明は部(3a)より測子(4)
を測定電極に接触させて特性をチェックする。そして、
チェック後、不良素子(2a)があると、その素子表面
にマーカ(5)にてマーキングする。上記マーキングは
、マーカ(5)にて不良素子表面にインクを滴下したり
、ダイヤモンド針やピアノ線等をマーカ(5)として不
良素子表面に傷打点を付けたり、更にレーザ光源をマー
カ(5)として不良素子表面にその熔融打点を付ける。Conventionally, in the manufacturing process of semiconductor devices such as ICs, a large number of elements (2) (2) are placed on a semiconductor wafer (1), as shown in FIG.
)... is formed, first each element (
2) Check the characteristics of (2)... and find the defective element (2a
)... mark. Each of the above elements (2) (2)
When checking the characteristics of..., as shown in Figure 8, after forming an insulating film (3) on the entire surface of the semiconductor wafer (1) to protect the element surface, Open the window, and this window brightness is from the part (3a) to the gauge (4).
Check the characteristics by touching the measuring electrode. and,
After checking, if a defective element (2a) is found, the surface of the element is marked with a marker (5). The above marking can be done by dropping ink onto the surface of the defective element using a marker (5), by making scratches on the surface of the defective element using a diamond needle or piano wire as a marker (5), or by using a laser light source as a marker (5). The melting point is marked on the surface of the defective element.
八 く ゝ しよ゛と る目
ところで、近年、半導体装置は集積度が上がり、素子寸
法が小さくなる傾向にあるが、特にこの時、上述したよ
うに半導体ウェーハ(1)に素子(2)を形成してその
特性をチェックした後、不良素子(2a)にマーキング
する際、まず不良素子表面にインクを滴下してマーキン
グすると、インクが周辺に飛び散って良品素子までイン
クが付着して不良と判定されたり、又、インクが付着す
ることによって不良と判定されなくても特性が変化する
ことがあり、更に不良素子が連続せずインクの滴下も不
連続になると、インクの粘度が高くなってマーキング不
良になることもある6次に、不良素子表面に傷打点を付
けてマーキングした場合、角度によっては傷打点が見え
ず、又、素子寸法が小さくなると、傷自体が付きにくく
なることがある。又、レーザ光によって不良素子表面に
溶融打点を付ける場合、ダストが生じて周辺に飛び散り
外観不良や特性不良が生じることがあり、又レーザ設備
は高価である。In recent years, the degree of integration of semiconductor devices has increased and the element dimensions have become smaller. After forming and checking its characteristics, when marking the defective element (2a), first drop ink on the surface of the defective element and mark it, the ink will scatter around the area and the ink will adhere to the non-defective element, which will determine it as defective. In addition, the characteristics may change due to ink adhesion even if it is not determined to be defective.Furthermore, if the defective elements are not continuous and the ink drips discontinuously, the viscosity of the ink increases and marking 6. If the surface of a defective element is marked with flaw points, the flaw points may not be visible depending on the angle, and as the element size becomes smaller, the flaws themselves may become difficult to form. Furthermore, when a laser beam is used to make a melting point on the surface of a defective element, dust may be generated and scattered around the device, resulting in poor appearance and poor characteristics, and laser equipment is expensive.
゛ るための
本発明は半導体ウェーハに多数の素子を形成しウェーハ
状態で各素子の特性をチェックして不良素子にマーキン
グするにあた椎、各素子表面の測定電極部分を除くウェ
ーハ表面にポジ型第1フォトレジストを塗布し各素子特
性をチェックした後、不良素子表面の第1のフォトレジ
ストを部分的に露光する工程と、上記第1フォトレジス
ト露光部を窓明けした後、上記測定電極部分の第1フォ
トレジスト窓明は部分に第2フォトレジストを塗布する
工程と、上記第1、第2フォトレジストで被覆されてい
ない不良素子をエツチングして表面にマーキングする工
程とを含むことを特徴とする。The present invention is designed to form a large number of devices on a semiconductor wafer, check the characteristics of each device in the wafer state, and mark defective devices. After coating the first photoresist and checking the characteristics of each element, there is a step of partially exposing the first photoresist on the surface of the defective element, and after opening the exposed area of the first photoresist, the measurement electrode is removed. The first photoresist window coating of the portion includes the steps of applying a second photoresist to the portion and marking the surface by etching defective elements not covered with the first and second photoresists. Features.
務里
半導体ウェーハに多数の素子を形成し測定電極部分を除
(ウェーハ表面にポジ型第1フォトレジストを塗布し各
素子特性をチェックした後、不良素子表面の第1フォト
レジストを露光し窓明けし、その後、測定電極部分の第
1フォトレジスト窓明は部分に第2フォトレジストを塗
布し、更に第1、第2フォトレジストで覆われていない
不良素子表面をエツチングすると、素子が破壊される。A large number of elements are formed on a Muzato semiconductor wafer, and the measurement electrode part is removed (after coating the wafer surface with a positive type first photoresist and checking the characteristics of each element, the first photoresist on the surface of the defective element is exposed and a window is opened). After that, a second photoresist is applied to the first photoresist window of the measurement electrode portion, and the surface of the defective element that is not covered with the first and second photoresists is further etched, resulting in destruction of the element. .
尖五匹
本発明に係る半導体装置の製造方法を第1図乃至第6図
を参照しその通用順に以下説明する、図において、(6
)は多数の素子が形成されている半導体ウェーハ、(7
)は半導体ウェーハ(6)上に形成され、各素子表面を
保護する5i02 、SiN等の絶縁膜、(8)は絶縁
FJ (7)上に塗布されたポジ型第1フォトレジスト
、(9)は第1フォトレジスト(8)上に塗布された第
2フォトレジスト、(10)は上記素子の特性チェック
用プローブ、(11)は露光用光ファイバである。5 Points In the figures, (6
) is a semiconductor wafer on which many elements are formed, (7
) is formed on the semiconductor wafer (6) and protects the surface of each element with 5i02, an insulating film such as SiN, (8) is the positive type first photoresist coated on the insulating FJ (7), (9) 1 is a second photoresist coated on the first photoresist (8), (10) is a probe for checking the characteristics of the above-mentioned element, and (11) is an optical fiber for exposure.
上記構成に基づき本発明の動作を次に示す。The operation of the present invention based on the above configuration will be described below.
まず第1図に示すように、半導体ウェーハ(6)に多数
の素子を形成すると、その表面に絶縁膜(7)を形成し
て素子を保護し、更に絶縁膜(7)上にポジ型第1フォ
トレジスト(8)を塗布して各素子表面の測定電極部分
を窓明けする0次に、第2図に示すように、第1フォト
レジスト(8)をマスクとしてエツチングしその窓明は
部(8a)の絶縁膜(7)を除去した後、第3図に示す
ように、窓明は部(8a)よりプローブ(10)を素子
測定電極に接触させて特性をチェックする。そして、特
性チェックの結果、不良素子に対して、第3図に示すよ
うに、不良素子表面の第1フォトレジスト(8)を遮蔽
筒(12)を介し光ファイバ(11)にて露光する。First, as shown in FIG. 1, when a large number of elements are formed on a semiconductor wafer (6), an insulating film (7) is formed on the surface of the semiconductor wafer (7) to protect the elements. 1 Apply photoresist (8) to open a window in the measurement electrode portion on the surface of each element.Next, as shown in FIG. After removing the insulating film (7) of (8a), as shown in FIG. 3, the probe (10) is brought into contact with the element measurement electrode from the window part (8a) to check the characteristics. As a result of the characteristic check, as shown in FIG. 3, the first photoresist (8) on the surface of the defective element is exposed to light through the optical fiber (11) through the shield tube (12).
そうすると、第1フォトレジスト(8)はポジ型である
ので、現像すると第4図に示すように、第1フォトレジ
スト(8)の露光部が除去されて窓明は部分(8b)が
形成され、不良素子表面が露出される6次に、第1フォ
トレジスト(8)上にネガ又はポジ型の第2フォトレジ
スト(9)を塗布した後、第5図に示すように、良、不
良によらず各素子毎に測定電極部分を除いて一様に第2
フォトレジスト(9)を窓明けすると、上記測定電極に
対応する第1フォトレジスト(8)の窓明は部分(8b
)が第2フォトレジスト(9)で被覆される。そして、
第2フォトレジスト(9)をマスクとして各素子表面を
一様にエツチングすると、良品素子の表面は第1フォト
レジスト(8)で被覆され(図示せず)、不良素子の表
面は第1フォトレジスト(8)で覆われていないため、
不良素子表面が絶縁膜(7)を経て素子領域までエツチ
ングされ不良素子が破壊される。その後、第6図に示す
ように、第1及び第2フォトレジスト(8)(9)を除
去すると、不良素子表面の絶縁膜(7)の窓明は部(7
a)が残ってマーキングされる。Then, since the first photoresist (8) is positive type, when developed, the exposed part of the first photoresist (8) is removed and a window portion (8b) is formed as shown in FIG. , the surface of the defective element is exposed 6 Next, after applying a negative or positive second photoresist (9) on the first photoresist (8), as shown in FIG. The second electrode is uniformly applied to each element, excluding the measurement electrode part.
When the photoresist (9) is opened, the window of the first photoresist (8) corresponding to the measurement electrode is exposed at a portion (8b).
) is coated with a second photoresist (9). and,
When the surface of each element is uniformly etched using the second photoresist (9) as a mask, the surface of the good element is covered with the first photoresist (8) (not shown), and the surface of the defective element is covered with the first photoresist (8). Because it is not covered by (8),
The surface of the defective element is etched through the insulating film (7) to the element region, and the defective element is destroyed. After that, as shown in FIG. 6, when the first and second photoresists (8) and (9) are removed, the window brightness of the insulating film (7) on the surface of the defective element is reduced to part (7).
a) remains and is marked.
11Fと九果
本発明によれば、半導体ウェーハに多数の素子を形成し
ウェーハ状態で各素子の特性をチェックした後、不良素
子表面にエツチングにてマーキングするようにしたから
、マーキングによる異物が発生せず、しかもマークの大
きさが均“−で認識し易い。しかも、マーキングによっ
て不良素子の素子領域までエツチングされて素子が破壊
されるため、信頼性の乏しい素子の混入を防止でき素子
寸法によらずマーキングと良、不良の判別を確実に行え
る。According to the present invention, after forming a large number of devices on a semiconductor wafer and checking the characteristics of each device in the wafer state, the surface of the defective device is marked by etching, which prevents the generation of foreign matter due to the marking. Moreover, the mark size is uniform and easy to recognize. Moreover, the marking etches into the element area of the defective element and destroys the element, which prevents the contamination of unreliable elements and reduces the element size. It is possible to reliably distinguish between good and bad markings without depending on the marking.
第1図乃至第6図は本発明に係る半導体装置の製造方法
を示すその工程順の各断面図である。
第7図は素子が形成された半導体ウェーハの平面図、第
8図は半導体ウェーハに形成された素子の特性チェック
と従来の不良素子のマーキング方法を示す断面図である
。
(6)・・・半導体つ、−ハ、
(8)・・・第1フォトレジスト、
(8b)・・・第1フォトレジスト窓明は部分。
(9)・・・第2フォトレジスト。FIGS. 1 to 6 are cross-sectional views illustrating the method of manufacturing a semiconductor device according to the present invention in the order of steps. FIG. 7 is a plan view of a semiconductor wafer on which elements are formed, and FIG. 8 is a sectional view showing a conventional method for checking characteristics of elements formed on a semiconductor wafer and marking defective elements. (6)...Semiconductor, -c, (8)...First photoresist, (8b)...First photoresist window is a portion. (9)...Second photoresist.
Claims (1)
態で各素子の特性をチェックして不良素子にマーキング
するにあたり、 各素子表面の測定電極部分を除くウェーハ表面にポジ型
第1フォトレジストを塗布し各素子特性をチェックした
後、不良素子表面の第1フォトレジストを部分的に露光
する工程と、 上記第1フォトレジスト露光部を窓明けした後、上記測
定電極部分の第1フォトレジスト窓明け部分に第2フォ
トレジストを塗布する工程と、 上記第1、第2フォトレジストで被覆されていない不良
素子をエッチングして表面にマーキングする工程とを含
むことを特徴とする半導体装置の製造方法。(1) When forming a large number of devices on a semiconductor wafer, checking the characteristics of each device in the wafer state, and marking defective devices, a positive type first photoresist is applied to the wafer surface excluding the measurement electrode portion on the surface of each device. After checking the characteristics of each element, there is a step of partially exposing the first photoresist on the surface of the defective element, and after opening the first photoresist exposed area, opening the first photoresist window on the measurement electrode part. A method for manufacturing a semiconductor device, comprising the steps of: applying a second photoresist to a portion; and etching and marking a defective element not covered with the first and second photoresists on the surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9774987A JPS63261843A (en) | 1987-04-20 | 1987-04-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9774987A JPS63261843A (en) | 1987-04-20 | 1987-04-20 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63261843A true JPS63261843A (en) | 1988-10-28 |
Family
ID=14200533
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9774987A Pending JPS63261843A (en) | 1987-04-20 | 1987-04-20 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63261843A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7629228B2 (en) | 2004-08-02 | 2009-12-08 | Panasonic Corporation | Manufacturing method for semiconductor devices, and formation apparatus for semiconductor wafer dicing masks |
-
1987
- 1987-04-20 JP JP9774987A patent/JPS63261843A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7629228B2 (en) | 2004-08-02 | 2009-12-08 | Panasonic Corporation | Manufacturing method for semiconductor devices, and formation apparatus for semiconductor wafer dicing masks |
EP1782464B1 (en) * | 2004-08-02 | 2012-04-11 | Panasonic Corporation | Manufacturing method for semiconductor devices |
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