JPH04240745A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04240745A
JPH04240745A JP2407191A JP2407191A JPH04240745A JP H04240745 A JPH04240745 A JP H04240745A JP 2407191 A JP2407191 A JP 2407191A JP 2407191 A JP2407191 A JP 2407191A JP H04240745 A JPH04240745 A JP H04240745A
Authority
JP
Japan
Prior art keywords
electrode pad
protective film
film
pad portion
resist film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2407191A
Other languages
Japanese (ja)
Inventor
Kazuhiko Nakahama
和彦 中浜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Motor Corp
Original Assignee
Toyota Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Motor Corp filed Critical Toyota Motor Corp
Priority to JP2407191A priority Critical patent/JPH04240745A/en
Publication of JPH04240745A publication Critical patent/JPH04240745A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • H01L2224/05557Shape in side view comprising protrusions or indentations

Abstract

PURPOSE:To provide a manufacturing method for a semiconductor device in which marking ink adhered on a protective film in a probe test is inhibited to flow to an electrode pad. CONSTITUTION:A semiconductor device having an electrode pad 11a formed on a semiconductor substrate 10 and a protective film 12 made of an insulating material at least on the surface of the part except the pad 11a, is formed. A resist film is formed on the device, and the pad 11a and at least partial resist film of other part except the peripheral edge of the pad are removed. With the remaining film as a mask the film 12 exposed on the removed part of the film is so etched to a predetermined depth as not to expose its lower layer to remove the remaining film. Thus, a recess 12a of a desired depth is formed on the film 12 part.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体装置の製造方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

【0002】0002

【従来の技術】従来、半導体装置の製造工程においては
、半導体基板上に形成した電極パッド部を除いた部分の
表面に保護膜を形成している。この保護膜の電極パッド
部の周縁と重なる部分は略電極パッド部の高さ分程度高
くなり、電極パッド部の周縁部において保護膜に段差が
形成される(例えば特開平2―181429号公報参照
)。
2. Description of the Related Art Conventionally, in the manufacturing process of semiconductor devices, a protective film is formed on the surface of a semiconductor substrate except for an electrode pad portion. The portion of this protective film that overlaps with the periphery of the electrode pad portion is approximately as high as the height of the electrode pad portion, and a step is formed in the protective film at the periphery of the electrode pad portion (for example, see Japanese Patent Application Laid-Open No. 2-181429). ).

【0003】0003

【発明が解決しようとする課題】しかし、上記保護膜の
段差は通常1ミクロン程度である。このため、保護膜形
成後の半導体装置が、プロ―ブ試験において不良と判定
され、保護膜上に一定量のマ―キング用インクが付され
ると、図9に示したように、インクが保護膜上を広がり
上記段差部分を越えて電極パッド部まで流れ込み、測定
用プロ―ブに付着することがある。かかるインクの付着
した測定用プロ―ブで測定を続けると、測定用プロ―ブ
に付着したインクのため測定用プロ―ブと電極パッド部
間に接触不良を生じ、このため良品が不良品と誤って判
定される場合が生じ、プロ―ブ試験の信頼性が損なわれ
る。この問題を回避するためインクの吐出量を減少させ
ることが考えられるが、インクの吐出量は、マ―キング
を明確にすること及びインク吐出機構からのインクの吐
出を円滑にさせること等の理由により上記一定量以下に
することはできない。本発明の目的は、かかる問題に対
処するために、プロ―ブ試験において保護膜上に吐出さ
れたインクが電極パッド部へ流れないような半導体装置
を製造する方法を提供することにある。
However, the level difference in the protective film is usually about 1 micron. For this reason, if the semiconductor device after the protective film is formed is determined to be defective in the probe test and a certain amount of marking ink is applied on the protective film, the ink will disappear as shown in FIG. It spreads over the protective film, flows over the step portion to the electrode pad portion, and may adhere to the measurement probe. If measurements are continued with a measuring probe that has such ink attached, the ink that has adhered to the measuring probe will cause poor contact between the measuring probe and the electrode pad, which may cause a non-defective product to become a defective product. Misjudgment may occur, and the reliability of the probe test is impaired. It is possible to reduce the amount of ink ejected to avoid this problem, but the amount of ink ejected is determined for reasons such as making the marking clear and ensuring smooth ink ejection from the ink ejection mechanism. Therefore, it is not possible to reduce the amount below the above-mentioned certain amount. SUMMARY OF THE INVENTION In order to solve this problem, an object of the present invention is to provide a method for manufacturing a semiconductor device in which ink ejected onto a protective film during a probe test does not flow to an electrode pad portion.

【0004】0004

【課題を解決するための手段】本発明の特徴は、半導体
装置の製造方法として、半導体基板上に形成した電極パ
ッド部を含み、少なくとも前記電極パッド部を除く表面
部分に絶縁材料からなる保護膜を有する半導体装置上に
レジスト膜を形成する工程と、前記電極パッド部及びそ
の周縁部を除く他の部分の少なくとも一部のレジスト膜
を除去する工程と、残されたレジスト膜をマスクとして
前記保護膜をその下層が露出しない所定の深さまでエッ
チングする工程と、前記残されたレジスト膜を除去する
工程とを含むようにしたことにある。
[Means for Solving the Problems] A feature of the present invention is to provide a method for manufacturing a semiconductor device including an electrode pad portion formed on a semiconductor substrate, and a protective film made of an insulating material on at least a surface portion excluding the electrode pad portion. a step of forming a resist film on a semiconductor device having a structure, a step of removing at least a part of the resist film on other parts except the electrode pad part and its peripheral part, and a step of removing the resist film on the semiconductor device having the remaining resist film as a mask. The method includes the steps of etching the film to a predetermined depth so that the underlying layer is not exposed, and removing the remaining resist film.

【0005】[0005]

【作用】上記した半導体装置の製造方法においては、半
導体基板上に形成した電極パッド部を含み、少なくとも
電極パッド部を除く表面部分に保護膜を有する半導体装
置上にレジスト膜を形成する。このレジスト膜のうち電
極パッド部及びその周縁部を除く他の部分の少なくとも
一部を除去し、残されたレジスト膜をマスクとして保護
膜の露出した部分をその下層が露出しない所定の深さま
でエッチングし、その後残されたレジスト膜を除去する
。このようにして半導体装置の電極パッド部およびその
周縁部を除く他の保護膜部分の少なくとも一部に所定深
さの凹部が形成される。
In the method for manufacturing a semiconductor device described above, a resist film is formed on a semiconductor device that includes an electrode pad portion formed on a semiconductor substrate and has a protective film on at least a surface portion excluding the electrode pad portion. At least a portion of this resist film other than the electrode pad portion and its periphery is removed, and using the remaining resist film as a mask, the exposed portion of the protective film is etched to a predetermined depth so that the underlying layer is not exposed. Then, the remaining resist film is removed. In this way, a recessed portion having a predetermined depth is formed in at least a portion of the protective film portion other than the electrode pad portion and the peripheral portion thereof of the semiconductor device.

【0006】[0006]

【発明の効果】このため、本発明により製造した半導体
装置においては、プロ―ブ試験において不良と判定され
保護膜上にマ―キング用インクを付されても、インクは
凹部内に流れ込み外側への広がりが妨げられるので、電
極パッド部にまで流れ込まない。従って、測定用プロ―
ブにインクが付着することがなく、プロ―ブと電極間の
電気的接触が適正に維持されるので、良品が誤って不良
品と判定されることはなく、プロ―ブ試験の信頼性を高
めることができる。
[Effects of the Invention] Therefore, even if the semiconductor device manufactured according to the present invention is determined to be defective in the probe test and marking ink is applied to the protective film, the ink will flow into the recess and go outside. Since the spread of the liquid is prevented, it does not flow into the electrode pad portion. Therefore, the measurement pro-
This prevents ink from adhering to the probe and maintains proper electrical contact between the probe and the electrodes, which prevents good products from being incorrectly judged as defective and improves the reliability of probe tests. can be increased.

【0007】[0007]

【実施例】以下、本発明の第1実施例を図面により説明
する。 図1は、半導体装置の一例である半導体集積回路の製造
工程及びプロ―ブ試験工程の流れを示す。 図2は、半導体素子形成工程1において半導体基板10
上にトランジスタ等の半導体素子11が形成され、その
後、保護膜形成工程2において、半導体素子11の形成
された半導体基板10上にCVD技術等によりリンシリ
カガラス等の保護膜12が形成され、さらに電極パッド
部11a上の保護膜12が除去され電極パッド部11a
の開口が設けられた半導体集積回路Aの断面を示す。こ
の半導体集積回路Aは半導体基板10上に所定のパタ―
ンにて複数個形成される。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the flow of a manufacturing process and a probe testing process of a semiconductor integrated circuit, which is an example of a semiconductor device. FIG. 2 shows a semiconductor substrate 10 in a semiconductor element forming process 1.
A semiconductor element 11 such as a transistor is formed thereon, and then, in a protective film forming step 2, a protective film 12 such as phosphor silica glass is formed on the semiconductor substrate 10 on which the semiconductor element 11 is formed by CVD technology or the like. The protective film 12 on the electrode pad portion 11a is removed and the electrode pad portion 11a is removed.
2 shows a cross section of a semiconductor integrated circuit A provided with an opening. This semiconductor integrated circuit A has a predetermined pattern on a semiconductor substrate 10.
Multiple pieces are formed at the same time.

【0008】次にレジスト膜形成工程3においては、図
3に示すように、保護膜12及び電極パッド部11aの
表面全体にスピナ―等の手段によりポジ型あるいはネガ
型のフォトレジストが塗布され、適温で乾燥してレジス
ト膜13が形成される。フォトリソグラフィ工程4にお
いては、図4に示すように、レジスト膜13の保護膜1
2上に位置しかつ電極パッド部11aの周囲を除く部分
に位置する所定の部分が、所定のフォトマスクを用いて
フォトリソグラフィ手段により選択的に除去される。
Next, in the resist film forming step 3, as shown in FIG. 3, a positive or negative photoresist is applied to the entire surface of the protective film 12 and the electrode pad portion 11a using a spinner or the like. A resist film 13 is formed by drying at an appropriate temperature. In the photolithography process 4, as shown in FIG.
A predetermined portion located on the electrode pad portion 2 and excluding the periphery of the electrode pad portion 11a is selectively removed by photolithography using a predetermined photomask.

【0009】エッチング工程5においては、図5に示す
ように、フォトリソグラフィ工程において選択的にレジ
スト膜13が除去されて表面の露出した部分の保護膜1
2が、残されたレジスト膜13をマスクとしてドライあ
るいはウエットエッチング手段によりその下層が露出し
ない所定の深さにエッチングされ、凹部12aが形成さ
れる。この場合に、この凹部12aの形状及び配列は、
後述するマ―キング用インクが電極パッド部11aに流
れ込まないように保護膜12の面積及び膜厚,電極パッ
ド部11aの配置等を考慮して予め設計される。この設
計結果に応じて、上記フォトリソグラフィ工程4におけ
るフォトマスクのパタ―ン形状及びエッチング工程5に
おけるエッチング条件が定められる。レジスト膜除去工
程6においては、エッチング工程5後に電極パッド部1
1a及び保護膜12上に残されたレジスト膜13が除去
され、図6に示すように、電極パッド部11aの周囲を
除いて保護膜12上に複数個の凹部12aが形成される
In the etching step 5, as shown in FIG. 5, the resist film 13 is selectively removed in the photolithography step and the protective film 1 is removed from the exposed portion of the surface.
2 is etched by dry or wet etching means using the remaining resist film 13 as a mask to a predetermined depth so that the underlying layer is not exposed, thereby forming a recess 12a. In this case, the shape and arrangement of the recesses 12a are as follows:
The area and thickness of the protective film 12, the arrangement of the electrode pad portions 11a, etc. are designed in advance so that marking ink, which will be described later, does not flow into the electrode pad portions 11a. Depending on this design result, the pattern shape of the photomask in the photolithography process 4 and the etching conditions in the etching process 5 are determined. In the resist film removal step 6, the electrode pad portion 1 is removed after the etching step 5.
1a and the resist film 13 remaining on the protective film 12 is removed, and as shown in FIG. 6, a plurality of recesses 12a are formed on the protective film 12 except around the electrode pad portion 11a.

【0010】以上の工程を経て半導体基板10上に複数
個製造された半導体集積回路Bは、プロ―ブ試験工程7
において、図9に示す従来例と同様に、電極パッド部1
1aに測定用プロ―ブ20を電気的に接触させることに
より順次その特性が測定される。その結果、半導体集積
回路Bは良品と不良品に選別され、不良品の場合は保護
膜12の上面にマ―キング用インク21が付される。こ
のとき、保護膜12には複数個の凹部12aが設けられ
ているので、インク21の一部は凹部12aに流れ込み
外方への広がりが止められるので電極パッド部11a内
にまで流れ込むことはない。したがって、インク21が
測定用プロ―ブ20に付着することもなく、以後の測定
において、測定用プロ―ブ20と電極パッド部11a間
の電気的接触が良好に維持されので、良品が不良品と誤
って判定されることはなく、上記プロ―ブ試験の信頼性
が保証される。
A plurality of semiconductor integrated circuits B manufactured on the semiconductor substrate 10 through the above steps are subjected to a probe test step 7.
In this case, as in the conventional example shown in FIG.
By electrically contacting the measuring probe 20 to 1a, its characteristics are sequentially measured. As a result, the semiconductor integrated circuits B are sorted into good and defective products, and if the semiconductor integrated circuits B are defective, marking ink 21 is applied to the upper surface of the protective film 12. At this time, since the protective film 12 is provided with a plurality of recesses 12a, a portion of the ink 21 flows into the recesses 12a and is prevented from spreading outward, so that it does not flow into the electrode pad portion 11a. . Therefore, the ink 21 does not adhere to the measuring probe 20, and good electrical contact between the measuring probe 20 and the electrode pad portion 11a is maintained in subsequent measurements, so that good products are replaced by defective ones. The reliability of the above probe test is guaranteed.

【0011】上記第1実施例においては、電極パッド部
11aの周囲を除いて保護膜12上に複数個の凹部12
aを形成するようにしたが、第2実施例として、以下に
示すように凹部を形成しても良い。すなわち、フォトリ
ソグラフィ工程4において、図7に示すように、電極パ
ッド部11a及びその周囲を除いた保護膜12上の全体
のレジスト膜13を除去し、表面の露出した部分の保護
膜12をエッチング工程5において、図8に示すように
、3〜5ミクロン程度の深さエッチング除去し、残りの
レジスト膜13を除去して電極パッド部11aの周囲を
除いた保護膜12部分に従来の製造工程によっては形成
できない深さの凹部12bを形成するようにしても良い
。上記第2実施例のように凹部12bを形成することに
よっても上記第1実施例と同様に、保護膜12上に付さ
れたマ―キング用インク21が、深い凹部12b内に止
められるので電極パッド部11aに流れ込むことはなく
、プロ―ブ試験の信頼性が保証される。
In the first embodiment, a plurality of recesses 12 are formed on the protective film 12 except around the electrode pad portion 11a.
In the second embodiment, a recessed portion may be formed as shown below. That is, in the photolithography step 4, as shown in FIG. 7, the entire resist film 13 on the protective film 12 except for the electrode pad portion 11a and its surroundings is removed, and the exposed portion of the protective film 12 on the surface is etched. In step 5, as shown in FIG. 8, the remaining resist film 13 is removed by etching to a depth of about 3 to 5 microns, and the protective film 12 excluding the area around the electrode pad portion 11a is subjected to a conventional manufacturing process. The recess 12b may be formed at a depth that cannot be formed depending on the case. By forming the recess 12b as in the second embodiment, the marking ink 21 applied on the protective film 12 is stopped in the deep recess 12b, as in the first embodiment. It does not flow into the pad portion 11a, and the reliability of the probe test is guaranteed.

【0012】なお、上記第1実施例及び第2実施例にお
いては、保護膜形成工程2において電極パッド部11a
上部の保護膜12を除去し電極パッド部11aに開口を
形成しているが、かかる電極パッド部11aの開口を保
護膜12に凹部12aあるいは12bを設けた後すなわ
ち図1のレジスト膜除去工程6の後に形成しても良い。
[0012] In the first and second embodiments described above, in the protective film forming step 2, the electrode pad portion 11a
Although the upper protective film 12 is removed and an opening is formed in the electrode pad portion 11a, the opening of the electrode pad portion 11a is removed after the recess 12a or 12b is provided in the protective film 12, that is, in the resist film removal step 6 in FIG. It may be formed after.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】半導体集積回路の製造工程及びプロ―ブ試験工
程の流れの一例を示すフロ―チャ―トである。
FIG. 1 is a flowchart showing an example of the flow of a semiconductor integrated circuit manufacturing process and a probe testing process.

【図2】保護膜の形成された半導体集積回路の断面図で
ある。
FIG. 2 is a cross-sectional view of a semiconductor integrated circuit on which a protective film is formed.

【図3】保護膜及び電極パッド部の表面にレジスト膜が
形成された半導体集積回路の断面図である。
FIG. 3 is a cross-sectional view of a semiconductor integrated circuit in which a resist film is formed on the surfaces of a protective film and an electrode pad portion.

【図4】レジスト膜の所定部分が除去された半導体集積
回路の断面図である。
FIG. 4 is a cross-sectional view of the semiconductor integrated circuit with a predetermined portion of the resist film removed.

【図5】エッチングにより保護膜に凹部の形成された半
導体集積回路の断面図である。
FIG. 5 is a cross-sectional view of a semiconductor integrated circuit in which a recess is formed in a protective film by etching.

【図6】エッチング後に、レジスト膜が除去された半導
体集積回路の断面図である。
FIG. 6 is a cross-sectional view of the semiconductor integrated circuit from which the resist film has been removed after etching.

【図7】第2実施例に係るレジスト膜の所定部分が除去
された半導体集積回路の断面図である。
FIG. 7 is a cross-sectional view of a semiconductor integrated circuit from which a predetermined portion of a resist film has been removed according to a second embodiment.

【図8】第2実施例に係るエッチングにより保護膜に凹
部の形成された半導体集積回路の断面図である。
FIG. 8 is a cross-sectional view of a semiconductor integrated circuit in which a concave portion is formed in a protective film by etching according to a second embodiment.

【図9】従来の技術による半導体集積回路に対するプロ
―ブ試験の概略図である。
FIG. 9 is a schematic diagram of a probe test on a semiconductor integrated circuit according to a conventional technique.

【符号の説明】[Explanation of symbols]

10 …半導体基板、11…半導体素子、11a…電極
パッド部、12…保護膜、12a,12b…凹部、13
…レジスト膜、20…プロ―ブ、21…マ―キング用イ
ンク、A,B…半導体集積回路。
DESCRIPTION OF SYMBOLS 10... Semiconductor substrate, 11... Semiconductor element, 11a... Electrode pad part, 12... Protective film, 12a, 12b... Recessed part, 13
...Resist film, 20...Probe, 21...Marking ink, A, B...Semiconductor integrated circuit.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  半導体基板上に形成した電極パッド部
を含み、少なくとも前記電極パッド部を除く表面部分に
絶縁材料からなる保護膜を有する半導体装置上にレジス
ト膜を形成する工程と、前記電極パッド部及びその周縁
部を除く他の部分の少なくとも一部のレジスト膜を除去
する工程と、残されたレジスト膜をマスクとして前記保
護膜をその下層が露出しない所定の深さまでエッチング
する工程と、前記残されたレジスト膜を除去する工程と
を含むことを特徴とする半導体装置の製造方法。
1. A step of forming a resist film on a semiconductor device including an electrode pad portion formed on a semiconductor substrate and having a protective film made of an insulating material on at least a surface portion excluding the electrode pad portion; etching the protective film to a predetermined depth so that the underlying layer is not exposed using the remaining resist film as a mask; 1. A method for manufacturing a semiconductor device, comprising the step of removing a remaining resist film.
JP2407191A 1991-01-24 1991-01-24 Manufacture of semiconductor device Pending JPH04240745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2407191A JPH04240745A (en) 1991-01-24 1991-01-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2407191A JPH04240745A (en) 1991-01-24 1991-01-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04240745A true JPH04240745A (en) 1992-08-28

Family

ID=12128196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2407191A Pending JPH04240745A (en) 1991-01-24 1991-01-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04240745A (en)

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