JPS6119176A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a device with a double-layer gate electrode, at a stepped section thereof a pattern is not disconnected and which has high reliability, by forming an N type poly Si electrode on a gate oxide film in a P type Si substrate, coating only a side section with an oxide film and superposing N type poly Si again. CONSTITUTION:A field oxide film 102 and a gate oxide film 103 are formed to a P type Si substrate 101, N type poly Si 104 and Si3N4 105 are superposed, and a resist mask 106 is shaped and a gate electrode 104' is formed through etching. The resist 106 is removed, the side wall of the electrode 104' is coated with a thermal oxide film 107, and CVDSiO2 108 is deposited. B ions are implanted, etching rates are made different in response to film thickness, and SiO2 108' is left only on the side surface of the electrode 104' through etching by diluted hydrofluoric acid. Si3N4 5 is removed, the surface is coated with SiO2 109, and N type poly Si 110 and further a high melting- point metal 111 are superposed and a second layer gate electrode is shaped. According to the constitution, the oxide film can be thickened at the corner section of the gate electrode in a lower layer and sufficient dielectric withstanding voltage is obtained, an eave shape through etching is not generated at the lower edge of the electrode, and a disconnection at a stepped section of a gate electrode in an upper section is not generated, thus acquiring a device having high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device having two or more layers of gate electrodes.

[Technical background of the invention and its problems] A semiconductor device having two or more layers of gate electrodes, e.g.
The 0-ting gate type EPROM is shown in Figure 2(a)~
It is manufactured through the steps shown in (d). That is, first, a field oxide film 2 is formed on a semiconductor substrate 1 made of silicon or the like to separate element regions into islands, and then a gate oxide film 3 is formed on the surface of the element region of the substrate 1. Next, a first polycrystalline silicon film 4 is deposited over the entire surface (as shown in FIG. 2(a)).

Next, this polycrystalline silicon film 4 is buttered to form a first gate electrode (floating gate electrode) 4- in a desired shape, and then a silicon oxide film (S
i02 film) is formed. As a result, an oxide film 5 is formed on the surface of the first gate electrode 4' (as shown in FIG. 2(b)).

Next, a second polycrystalline silicon film 6 is deposited on the entire surface (as shown in FIG. 2C), and then this second polycrystalline silicon film 6 is etched using a resist pattern (not shown) to form an oxide film 5. A second gate electrode 6- (control gate electrode) is formed on the first gate electrode 4' via the gate electrode 4'. At this time, the wiring of the second gate electrode 6- is also patterned. Next, a resist pattern (not shown) in which the source/drain regions are to be formed is opened over the entire surface, and impurity ions are implanted using this as a mask. Next, heat treatment is performed to activate the implanted ions to form source and drain regions 7.8, and then an interlayer insulating film 9 is deposited on the entire surface (as shown in FIG. 2(d)). Here, FIG. 3 is a sectional view taken along the line AA in FIG. 2(d).

Next, using a well-known technique, contact holes are opened in the source and drain regions 7 and 8 of the interlayer insulating film 9, and then aluminum is deposited on the entire surface and then buttered to connect the source and drain regions through the contact holes. , a wiring connected to the drain region 7.8 is formed to complete the semiconductor device.

By the way, in such a conventional technique, when forming the first gate electrode 4' as described above, the first polycrystalline silicon film 4 deposited on the entire surface of the substrate 1 is selectively etched away and the butter is removed. Because of this, the end face of the first gate electrode 4' becomes vertical as indicated by symbol a, and therefore the corner becomes steep.

This steep corner is caused by the fact that when the oxide film 5 is formed on the surface of the first gate electrode 4-, the oxide film grows slowly at this corner due to the nature of oxide film growth, as shown in FIG. The film thickness in this area becomes thinner. Furthermore, because the shape of the formed oxide film forms a sharp edge b at this portion of the gate electrode 4', electric field concentration occurs there, further deteriorating the dielectric strength.

Further, the vertical surface portion of the first gate voltage tf+4- is
In a severe case, the upper side of the first gate electrode 4' protrudes like an eaves compared to the lower part, as shown by the dashed line C in the figure, resulting in a so-called overhanging state.

After growing the oxide film 5 on the first gate electrode 4-, a polycrystalline silicon film for the second gate electrode is deposited on the entire surface, and when this is buttered, in the part to be removed, The polycrystalline silicon film 6 under the overhang portion of the first gate electrode 4- could not be removed completely, and unnecessary polycrystalline silicon remained in this portion after the removal step. If such a situation occurs, an unnecessary portion will be added to the second gate electrode 6', and this residual polycrystalline silicon film may peel off during the subsequent manufacturing process, resulting in various problems. This causes inconvenience and adversely affects the reliability of the semiconductor device.

Furthermore, in order to improve the operating speed of the device in EPROMs, etc., a high melting point metal or silicide of a high melting point metal may be deposited on the upper surface of the second gate electrode 6' and its wiring to lower the resistance. However, in the conventional structure, the nearly vertical step on the side wall surface of the first gate electrode 4' leads to a significant decrease in the reliability of the device.

In other words, even after forming the oxide film 5 in such a stepped portion, the wall surface is still almost vertical, and the refractory metal material film in such a steep stepped structure is not easily removed during the deposition process. There are areas where the film thickness varies locally, reducing mechanical strength. Furthermore, although these high melting point materials are generally said to be thermally stable, in reality they tend to break at the stepped portion during heat treatment in subsequent steps. Therefore, in this case,
The reduction in electrical resistance cannot be measured, and reliability also deteriorates.

[Purpose of the Invention] The present invention has been made in view of the above-mentioned circumstances, and in order to improve the dielectric strength voltage of the insulating film of the first gate electrode and reduce the electrical resistance, the second gate oxide film and its An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent pattern breakage of the high melting point metal material due to a step on the side of a first gate electrode when m piles of the high melting point metal material are placed on wiring. do.

[Summary of the Invention] That is, in order to achieve the above object, the present invention forms a field oxide film separating element regions into islands on the surface of a semiconductor substrate of one conductivity type, and a field oxide film is formed on the surface of the element region. After forming a first gate oxide film, forming a first polycrystalline silicon film on the entire surface, and forming a protective film for the first polycrystalline silicon film on the entire surface, these two layers are buttered. a step of growing an oxide film over the entire surface and removing it by etching to leave the oxide film only on the sides of the gate electrode; After removing the film, the first
a step of forming a second gate insulating film on the exposed surface of the gate electrode; and a step of depositing a conductive film on the entire surface and patterning these to form a second gate electrode. shall be. According to the present invention, a polycrystalline silicon film is formed, a protective film for the polycrystalline silicon film is formed on the upper surface of the polycrystalline silicon film, and then these two layers are patterned to form a first gate electrode. By growing an oxide film on the entire surface and removing it by etching, the oxide film is left only on the sides of the first gate electrode, thereby ensuring the thickness of the oxide film on the sides of the first gate electrode. , 1st
The surface of the first gate electrode is exposed by removing the protective film on the gate electrode, and then thermal oxidation is performed to remove the protective film on the first gate electrode.
After forming a second gate insulating film on the exposed surface of the gate electrode, a polycrystalline silicon film is deposited to form the second gate electrode, thereby reducing the oxide film at the corners of the first gate electrode. The thickness is increased so that sufficient dielectric strength can be obtained, and even if the side wall of the first gate electrode overhangs due to etching, the overhang is filled with the oxide film on the thick side, thereby making it possible to , second gate
After patterning the electrode, no unnecessary polycrystalline silicon film remains on the side of the first gate electrode, and a high melting point metal material is deposited on the second gate electrode to lower the resistance. In this case, the remaining oxide film on the side of the first gate electrode causes the step on the side to have a gentle slope, so that the pattern of the high melting point metal material does not break.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described using a nonvolatile memory (EPROM) as an example, with reference to manufacturing process diagrams shown in FIGS. 1(a) to (0).

First, a field oxide film 102 is formed on a p-type silicon substrate 101 to separate device regions into islands, and then a field oxide film 102 is formed on the substrate 101.
A first gate oxide film 103 was formed on the exposed surface of 1. Next, a first polycrystalline silicon layer 11104 is applied to the entire surface of the substrate 101.
After depositing, the first polycrystalline silicon film 104 is doped with, for example, arsenic as an impurity to make it conductive. Next, a silicon nitride film 105 was formed on the entire surface (as shown in FIG. 1(a)). This silicon nitride film 105 serves as a stopper for maintaining the thickness of the first gate electrode when etching the first polycrystalline silicon film 104. However, this stopper is not limited to silicon nitride film;
Any film may be used as long as it functions as a protective film for etching the polycrystalline silicon film 104 in the next step, but a silicon nitride film is used here because it is easy to remove.

Next, a resist was applied to the entire surface, and a resist pattern 106 was formed in the area where the first gate electrode was to be formed in the element region by photolithography (as shown in FIG. 1(b)). Next, using the resist pattern 106 as a mask, the silicon nitride film 1 is
05 and the polycrystalline silicon film 104 were sequentially etched away to form a first gel electrode 104' (Fig. 1(C)).
(Illustrated).

Next, after removing the resist pattern 106, thermal oxidation was performed to form an oxide film 107 on the sidewall surface of the first gate electrode 104'. Next, the entire surface of the substrate 101 (7) 1.
mCVD method niyo V) S i 02 M! After depositing 108, poron was ion-implanted into the entire surface of S+0211108, for example, about 1×10”Cm4 (Fig. 1(d)
). This ion implantation allows the oxide 11108 to be etched quickly. Comparing the film thickness between the step part and the flat part, since the step part is thicker, the impurity concentration in the step part is deeper than the flat part, and the impurity concentration is lower than in the shallower area. The etching rate can be set lower in a region deeper than the equivalent film thickness than in a shallower region.

Next, the SiO2 film 108 was removed by etching using dilute hydrofluoric acid or the like. At this time, the flat part of the SiO2 film 108 has a high boron impurity concentration, while in the step part, the impurity concentration is lower in a region deeper than the flat part.
When etching 5102M1108, the SiO2 film 108' remained only on the sides of the first gate electrode 104' (
(Illustrated in FIG. 1(e)). Since the side surface of the remaining SiO2 film 108' has a curved surface, the stepped portion forms a smooth slope.

Next, the silicon nitride film 10 on the first gate electrode 104-
After removing the first gate electrode 1, thermal oxidation is performed to form the first gate electrode 1.
A second gate oxidation wA109 was formed on the upper surface of 04- (as shown in FIG. 1(f)). Subsequently, a second polycrystalline silicon film was deposited on the entire surface of the substrate 101, and then doped with, for example, phosphorus to provide conductivity (as shown in FIG. 1(Q)).

Thereafter, in accordance with the conventional technique, the second polycrystalline silicon film is buttered using a resist pattern to form the second gate electrode 110 and its wiring, and the resist pattern is removed. N-type impurity ions were implanted into the mask, and then the implanted ions were activated to form source/drain regions. Next, an interlayer insulating film is deposited on the entire surface, and contact holes are opened at the source and drain regions of the interlayer insulating film. Next, aluminum is deposited on the entire surface, and then this is buttered and the source is connected through the contact holes. Then, wiring connected to the drain region was formed to complete the semiconductor device.

In the semiconductor device manufactured in this way, since the oxide film can be formed thickly on the sidewall portions of the first gate electrode 104-, the oxide film thickness at the corners of the first gate electrode 104' can be kept thick. In addition to being able to obtain a sufficient dielectric strength voltage, since the oxide film on the side wall portion of the first gate electrode 104- is thick, the overhang portion is filled with this side wall oxide film, and the overhang portion is filled with the side wall oxide film. The effect of overhang is eliminated. Moreover, the first gate electrode 104'
Since the oxidized WA 108- left on the side wall portion of the oxide exhibits a curved surface, the second polycrystalline silicon film deposited thereon for forming the second gate electrode 110 is The disadvantage of depositing under the overhang of the gate electrode 104' and easily remaining in this area during etching of the second polycrystalline silicon film is eliminated. Since the over-etching time required to remove the residual polycrystalline silicon film becomes almost unnecessary, erosion of the field oxide film 102 under the first layer gate electrode 104 can be prevented.

Note that in the above embodiment, S is used as the second gate insulating film material.
i 02 II was used, but the first gate electrode 104
Considering the dielectric strength between the gate electrode 110 and the second gate electrode 110, it is better to form a silicon nitride film on the 5i02 film and then heat-treat the surface of the silicon nitride film in an oxidizing atmosphere, rather than using only the 5iOz film. , Some of them are S i 02 * / Shiko > Nitriding! ! It is desirable to have a three-layer structure of /8102 film. In addition, the etching rate of the 5if2 film 108 is adjusted by performing ion implantation in FIG.
Although we tried to leave the O2 film, the thickness of the SiO2 film is thicker on the stepped parts than on the flat parts, so etching due to the introduction of impurities
Even if etching is simply performed using RIE without rate adjustment, the 5102 film can be left only on the sidewalls of the stepped portions.

Example 2 In Example 1, the second gate electrode 110 and its wiring are composed of a single layer of polycrystalline silicon film, and in this case,
There is a limit to the operating speed of the element. Therefore, in order to improve the operating speed of the element, a high melting point metal material 111 made of a high melting point metal or a high melting point metal silicide is deposited on the second polycrystalline silicon film 110a by sputter deposition to form a two-layer structure.

That is, in Example 2, after going through the same manufacturing steps as those shown in FIGS. 1(a) to 1(f), a high melting point metal material 111 is formed on the second polycrystalline silicon film 110a. The high melting point metal material 111 and the second polycrystalline silicon film 110a are deposited by sputter deposition and then patterned to form a second gate with a two-layer structure of the high melting point metal material 111 and the second polycrystalline silicon film 110. The electrode 112 and its wiring (as shown in FIG. 6) are formed into a two-layer structure to achieve low resistance.

In this case, in the conventional structure, there was a nearly vertical step on the side wall surface of the first gate electrode, so even if an attempt was made to deposit a high melting point metal material on the second gate electrode to lower the resistance, this step would be removed. However, according to the present invention, due to the residual oxide film 108' on the side wall of the first gate electrode 104',
Since the step at the side portion exhibits a gentle slope, stress does not occur in the high melting point metal material, and therefore, the high melting point metal material 111 constituting the second gate electrode 112
The pattern breakage at the step part no longer occurs, and it is sufficient.
Moreover, it becomes possible to reliably reduce the resistance.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to increase the thickness of the oxide film at the corners of the first gate electrode, and to obtain sufficient dielectric strength. In addition, it is possible to prevent the oxide film under the first gate electrode from being etched and the lower edge of the gate electrode becomes overhang, and to reduce the resistance by depositing a high melting point metal material on the second gate electrode. In this case, the remaining oxide film on the side of the first gate electrode causes the step on the side to become a gentle slope, which prevents pattern breakage of the high-melting point metal material, resulting in a highly reliable semiconductor device. A manufacturing method can be provided.

[Brief explanation of the drawing]

FIGS. 1(a) to (g) are manufacturing process diagrams for explaining Example 1 of the present invention, FIGS. 2(a) to (d) are manufacturing process diagrams for explaining the conventional method, and FIG. The figure is A- in Figure 2(d).
A sectional view, FIG. 4 is a diagram for explaining the corrosion state of the field oxide film surface near the first gate electrode that occurs during etching of the first polycrystalline silicon film in the conventional method, and FIG. FIG. 6 is a cross-sectional view showing the structure of Example 2 of the present invention. 101...p-type silicon substrate, 102...field oxide film, 103...first gate oxide film, 104...
...First polycrystalline silicon film, 104'...First gate electrode, 105...Silicon nitride film, 106...
Resist pattern, 107... Oxide film, 108.1
08"...Silicon oxide film, 109...Second gate oxide film, 110, 112...Second gate electrode, 1
10a... Second polycrystalline silicon film, 111... High melting point metal material. Figure 1 Figure 1 Figure 2 Figure A' Figure 3

Claims (4)

[Claims] (1) A step of forming a field oxide film separating element regions into islands on the surface of a semiconductor substrate of one conductivity type, forming a first gate insulating film on the surface of the element region, and forming a first multilayer film on the entire surface. After forming a crystalline silicon film and forming a protective film of the first polycrystalline silicon film on the entire surface, patterning these two layers to form a first gate electrode, and growing an oxide film on the entire surface. a step of etching away this to leave an oxide film only on the sides of the gate electrode; and a step of forming a second gate insulating film on the exposed surface of the first gate electrode after removing the protective film. A method for manufacturing a semiconductor device, comprising the steps of: depositing a conductive film over the entire surface and patterning the conductive film to form a second gate electrode. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the second gate electrode is a polycrystalline silicon film. (3) The method of manufacturing a semiconductor device according to claim 1, wherein the second gate electrode has a two-layer structure of a polycrystalline silicon film and a high melting point metal material film deposited on the upper surface of the second gate electrode. (4) The method of manufacturing a semiconductor device according to claim 1, wherein the second gate electrode has a two-layer structure of a polycrystalline silicon film and a high melting point metal silicide film deposited on the upper surface of the second gate electrode.