JPS6092615A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6092615A JPS6092615A JP58201320A JP20132083A JPS6092615A JP S6092615 A JPS6092615 A JP S6092615A JP 58201320 A JP58201320 A JP 58201320A JP 20132083 A JP20132083 A JP 20132083A JP S6092615 A JPS6092615 A JP S6092615A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- crystal silicon
- silicon film
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 16
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 4
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 7
- 239000011574 phosphorus Substances 0.000 abstract description 7
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract description 3
- 239000000155 melt Substances 0.000 abstract description 2
- 239000005380 borophosphosilicate glass Substances 0.000 abstract 1
- 230000035515 penetration Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に関し、特に配線のコン
タクトホールの形り一方法の改良に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for forming a contact hole for wiring.
例えば１、ＭＯａ型半導体装（至）の製造においては、
Ｖリコン基数上にｆｆ−）酸化ｌ１ｉｉ！！を介してｒ
−計電極を形成した後、このｆ−１１ＬｔＭをマスクと
するイオン注入によりソース、ドレイン領域を形成し、
更に全面に不純物を含む絶縁膜。For example, 1. In the production of MOa type semiconductor devices,
ff-) oxidation l1ii on the V recon radical! ! via r
- After forming the meter electrode, form the source and drain regions by ion implantation using this f-11LtM as a mask,
Furthermore, the insulating film contains impurities over the entire surface.
例えばＰ８Ｇｌｌｌ（リンシリク−トガラス膜〕。For example, P8Gll (phosphorus silicate glass membrane).
ＢＰ８Ｇｌｌ（ボロン−りンシリケートガラス膜）を堆
積し、その後写真蝕刻法を用い、レジストをマスクとし
て前記絶縁８ａをエツチングする。ことによりコンタク
トボールを開孔している。BP8Gll (boron-phosphorus silicate glass film) is deposited, and then the insulation 8a is etched using a photolithography method using a resist as a mask. As a result, the contact ball is opened.
従来、上述したコンタクトホールの開孔罠ついては弗散
會含む浴液を用いたウェットエツチング管灯なっていた
。しかし、このウエントエツテングは等方性であり、素
子の微細化にとっては不利である。Conventionally, the method for trapping the above-mentioned contact hole has been a wet etching tube using a bath solution containing fluorophore. However, this wet etching is isotropic, which is disadvantageous for miniaturization of devices.
そこで、郁近では異方性エツチングであるドライエツチ
ング法が採用されている。このドライエンチングでコン
タクトホールを形成すると、レジストとのパターン皺換
差がないためＸ子の微細化にとっては有利である。しか
し、異方性エツチングであるため、コンタクホールがｂ
ｈ孔された絶縁膜の端部の形状はほぼ直角となる。Therefore, at Ikuchika, a dry etching method, which is anisotropic etching, is adopted. Forming a contact hole by this dry etching is advantageous for miniaturization of X particles because there is no difference in pattern wrinkling from the resist. However, since it is anisotropic etching, the contact hole is b
The shape of the end of the insulating film with the hole formed is almost a right angle.
この結果、配線が形成された場合、絶縁膜の端部では配
線が非常に薄いため、配線が断線してオープン不良が生
じることかあυ、信頼性上極めて好ましくない。As a result, when a wiring is formed, the wiring is very thin at the end of the insulating film, so the wiring may be disconnected and an open failure may occur, which is extremely undesirable from a reliability standpoint.
一方、最近の素子の微細化に伴い、ソース。On the other hand, with the recent miniaturization of elements, the source
ドレイン領域等の不純物領域のシャロー・ソヤンクレヨ
ン化が進み、翼ｊは０．３μｍ以下となっている。従来
、ｘｊが浅くなった場合、熱処理時における／ｌと８１
との合金化によるｐｎ接合の破壊、いわゆるＡＪの突き
抜けを防止するには、Ａｄに２〜３％程度のシリコンを
含有させたＡＪ−８１１９を配線とし１用いることが有
効であった。しかし、スｊが０．３μｍ以下と非常に浅
くなった場合には、Ａｄ−８１１％を用いたとしても突
き抜けを防止できなくなるおそれが大となってくる。The impurity regions such as the drain region have become shallow and soyan, and the blade j has become 0.3 μm or less. Conventionally, when xj becomes shallow, /l and 81 during heat treatment
In order to prevent destruction of the pn junction due to alloying with Ad, so-called AJ penetration, it was effective to use AJ-8119, which contains Ad with about 2 to 3% silicon, as the wiring. However, when the thickness j becomes very shallow, such as 0.3 μm or less, there is a great possibility that penetration cannot be prevented even if Ad-811% is used.
本発明は上記事情に鑑みてなされたものであり、配線の
断線を防止するとともにシャローノヤンクション化によ
るＡＪの欠き抜けを防止し。The present invention has been made in view of the above circumstances, and prevents disconnection of the wiring and also prevents the AJ from being cut out due to shallow yunction.
素子の微細化を達成し得る半導体装置の製造方法を提供
しようとするものである。The present invention aims to provide a method for manufacturing a semiconductor device that can achieve miniaturization of elements.
本発明の半導体装置の製造方法は、素子が形成された半
導体基板の全面に絶縁膜を堆積し。In the method for manufacturing a semiconductor device of the present invention, an insulating film is deposited on the entire surface of a semiconductor substrate on which elements are formed.
その所定位置にコンタクトホールを開孔した後、コンタ
クトホール内の露出した基板表面に酸化膜を形成し１次
いで全面に非単結晶シリコン膜を堆積した後、異方性エ
ツチングによりコンタクトホール側壁部に非単結晶１７
ＩＪコンＰＩＡを残存させ、残存した非単結晶シリコ
ン膜をマスクとして前記酸化膜をエンチングし、更に全
曲に配線相料を堆積した後、パターニングして所定の配
線を形成することを骨子とするものである。After opening a contact hole at a predetermined position, an oxide film is formed on the exposed substrate surface inside the contact hole, and then a non-single crystal silicon film is deposited on the entire surface, and then anisotropic etching is performed to form a non-single crystal silicon film on the side wall of the contact hole. Non-single crystal 17
The main idea is to leave the IJ controller PIA, etch the oxide film using the remaining non-monocrystalline silicon film as a mask, and then deposit a wiring phase material over all the songs, followed by patterning to form a predetermined wiring. It is.
このような方法によれは、コンタクトホール側壁部に非
単結晶シリコン膜が残存しているので、コンタクトオー
ルの形状がなだらかになり。When using this method, the shape of the contact hole becomes gentle because the non-single crystal silicon film remains on the side wall of the contact hole.
配線の断線を防止することができる。また、配線材料と
してＡＮｔ４１いた場合、熱処理時にＡ／と残存した非
単結晶シリコンとが合金化し。Wiring breakage can be prevented. Further, when ANt41 is used as the wiring material, A/ and remaining non-single crystal silicon become alloyed during heat treatment.
基板シリコンの溶は込みが少なくなるので、ｘｊが浅く
なってもＡｄの突き抜けを防止することができる。Since the melt penetration of the substrate silicon is reduced, penetration of Ad can be prevented even if xj becomes shallow.
′ 以下１本発明の実施例を第１図（−）〜（ｆ）及び
抛２図（ａ） 、 （ｂ）を翻照して説明する。' An embodiment of the present invention will be described below with reference to FIGS. 1(-) to (f) and FIGS. 2(a) and (b).
実施例１
まず１通常の工程に従い、Ｐ型ｙ ＩＪコン基板１表面
にフィールド酸化膜２を形成し、フィールド酸化膜２に
囲まれた素子領域表面にｙ−ト酸化膜３會介してｙ−ト
ｗ極４ｆｆ形成し、更にダート電極４をマスクとして例
えば砒素をイオン注入した後、熱処理してｎ４型ソース
、ドレイン領域５．６を形成する。次に、全面に厚さ８
０００λのＢＰ８Ｇ膜２を堆積する。つづいて１図示し
ないホトレジストパターンをマスクとしてＢＰ８Ｇｌ１
％７ｔ？反応性イオンエツチング（ＲＩＥ）によりエツ
チングし、コンタクトホール８・・・を開孔する（第１
図（ａ）図示〕。 ”次いで、前記ホトレジストパター
ンを除去した後５９００℃、のドライ酸素中で熱処理し
て。Example 1 First, according to a normal process, a field oxide film 2 is formed on the surface of a P-type y-IJ converter substrate 1, and a y-t oxide film 3 is interposed on the surface of the element region surrounded by the field oxide film 2. After ion implantation of, for example, arsenic using the dirt electrode 4 as a mask, heat treatment is performed to form n4 type source and drain regions 5.6. Next, apply a thickness of 8 on the entire surface.
A BP8G film 2 of 000λ is deposited. Next, BP8Gl1 was prepared using a photoresist pattern (not shown) as a mask.
%7t? Etching is performed by reactive ion etching (RIE) to open contact holes 8 (first
Figure (a) illustrated]. ``Next, after removing the photoresist pattern, it was heat-treated in dry oxygen at 5900°C.
コンタクトホール８・・・内の露出したソース、ドレイ
ン領域５，６の表面に厚さ５００人の熱酸化膜９・・・
を形成する（同図（ｂ）図示）。つづいて。A thermal oxide film 9 with a thickness of 500 nm is formed on the exposed surfaces of the source and drain regions 5 and 6 in the contact holes 8...
(Illustrated in Figure (b)). Continuing.
ＬＰ−ＣＶＤ法ＫＩＤ全面１目４ｏｏｏλの多結晶シリ
コン映１０に堆積した後、、９００″Ｃ。LP-CVD method KID was deposited on the entire surface of polycrystalline silicon film 10 of 4oooλ, then heated to 900″C.
で３０分間リン拡散全行なう（同図（ｃ）図示）。The entire phosphorus diffusion was carried out for 30 minutes (as shown in the same figure (c)).
次いで１反応性イオンエツチング（ＲＩＢ）により多結
晶シリコン膜ＪＯをエツチングし。Next, the polycrystalline silicon film JO is etched by reactive ion etching (RIB).
コンタクトホール８・・・の側壁部に残存多結Ｊ＆νリ
コンルに７ ｏ ／・・・を形成する（同図（ｄ）図ボ
）。7o/... is formed in the remaining multi-contact J&ν recontour on the side wall of the contact hole 8 (see the box in FIG. 4(d)).
ツツイで、残存多結晶シリコン膜１０’・・・をマスク
としてＲＩ ｌ’ｉヌは弗酸ヲ含むエッテンダ液ケ用い
てｒＡ酸化膜９・・・の露出した部分をエツチング除去
する（同図（ｅ）図示〕。つづいて、全面に厚さ約８０
（１０λのＡｌ膜を蒸物した後、バターニングケ行な
い、Ａ／配、Ｉｉ！ｉｉ・・・を形成する。つついて、
フォーミングガス中、４５（１゜で３０分曲シリクリン
グを行７ｚう（同図（ｆ）図ンＪ＜ ） 。Then, using the remaining polycrystalline silicon film 10' as a mask, RI etching removes the exposed portion of the rA oxide film 9 using an etchant containing hydrofluoric acid (see the same figure). e) As shown]. Next, the thickness of about 80 mm is applied to the entire surface.
(After vaporizing a 10λ Al film, perform buttering to form A/Ii!ii...
In the forming gas, perform 7 cycles of bending at 45° (1°) for 30 minutes (FIG. 7(f)).
以下、）’８Ｇ等の保護膜を堆積し、ｎチャイル間０８
トクンソスタを製造する。Hereinafter, a protective film such as )'8G is deposited, and between the n-chills 08
Manufactures Tocun Sosta.
しかして、上記方法によれば第１図（ｄ）の工程でＲＩ
ＩＪによシ形飲、されたコンタクトηさ−ル８・・・
の側壁部に残任多結晶シリコン膜１０′・・・を形成し
′ているので、コンタクトホール８・・・の形状がなだ
らかとなり、同図（ｆ）の工程で形成されるＡｄ配線１
１・・・の断＠を防止することができる。また、シンタ
リングの際には、ＡＪ膜は残存多結晶シリコン膜１０′
・・・と合金化し、基板１のシリコンの溶は込みは少な
くなるので、ソース、ドレイン領域６，６か浅くとも／
ｌの突き抜けを防止することができる。However, according to the above method, in the step of FIG. 1(d), RI
Contact η circle 8...
Since the remaining polycrystalline silicon film 10' is formed on the side wall of the contact hole 8, the shape of the contact hole 8 becomes gentle, and the Ad wiring 1 formed in the process shown in FIG.
It is possible to prevent the disconnection of 1. Also, during sintering, the AJ film is removed from the remaining polycrystalline silicon film 10'.
..., and the penetration of the silicon in the substrate 1 is reduced, so that the source and drain regions 6, 6 are at least shallowly /
It is possible to prevent l from penetrating.
実ぬ例２
上記実施例１の第１図＋（ｃ）の工程におりるリン拡散
を行なわない以外は第１図１（ａ）〜（ｅ）とほぼ同様
な工程を経て、コンタクトホール８・・・の側壁部に形
成された残存多結晶シリコン１％ ７ ｏ ’・・・全
マスクとして熱酸化Ｉｌｌ？・・・の露出した部分をエ
ツチング除去した後、９００ｕ、で３０分間リン拡散を
行ない、ソース、ドレインｆａ域ｔｓ＋ｅ内部にソース
、ドレイン領域５，６よシ深いｎ＋型接合ＦｆＩ Ｊ
ｚ 、 Ｊ ２を形成すると同時に残存多結晶シリコン
膜ｚ ｏ ／ 、 ７ ｏ ／にもリンをドーグする（
第２図（ａ）図示）。次いで、全面ＫＡ／膜倉椎積した
後、パターニングして／ｌ配線ＩＩ・・・ン・ノヒ、成
する。つついて、フォーミングガスＥ４Ｊ、４５０ ｔ
；、で３０／Ｉｊ間シンタリングを行なう （同 図（
ｂ）しｌ 示 ） 。Practical Example 2 A contact hole 8 was formed through almost the same steps as in FIGS. 1(a) to 1(e) except that the phosphorus diffusion in the steps in FIG. 1+(c) of Example 1 was not performed. 1% of residual polycrystalline silicon formed on the sidewalls of... 7 o '... Thermal oxidation Ill as the entire mask? After removing the exposed portions by etching, phosphorus is diffused at 900μ for 30 minutes to form an n+ type junction FfIJ deeper than the source and drain regions 5 and 6 inside the source and drain fa regions ts+e.
At the same time as forming z, J2, phosphorus is also doped into the remaining polycrystalline silicon films z o /, 7 o / (
FIG. 2(a) diagram). Next, after applying KA/membrane lamination on the entire surface, patterning is performed to form wiring II. Peck, forming gas E4J, 450 t
Perform sintering between 30/Ij with ; (same figure (
b) Shown).
以７’、ｐｓｏ等の保δ色膜を形成し、ｎチャネルＭ
ＯＳ ）ランジスタに製造する。7', forming a δ color retention film such as pso, and forming an n-channel M
OS) Manufactured into transistors.
［７かして、上舵方法によれば実施例１と同様にＡｌ配
Ｖツノ・・・の１線な・防止できるうえに。[7] According to the upper rudder method, as in the first embodiment, it is possible to prevent the Al-arranged V-horns from forming in one line.
躯２ ［ｍｌ （ａ）の１程で深いｎ４″ 沢接合層１
２・・・全形成しているので、Δｇの朶き抜１／ｊなよ
り確火に防止することかできる。この場合、多結晶シリ
コン膜はシリコン酸化膜と異なシ・リン拡散Ｖこよる開
孔部の敦形や膜隘りかないため、コンタクトツ：−ルＶ
Ｃ関しｔはＲＩＥＫよる制御性のよいフ［・・状を・維
持１°ることかできる。なお、コンタクトホール８・・
・の側壁部に残存多結晶シリコン膜１０′・・・を形成
し７ない従来の方法においで、実 ・施例２と同様にＨ
′、い１１４壓接合層Ｊ２・・・を形成しようとすると
、不純物の横方向への拡散ｒ（よ゛つてショートチャオ
ル効果を大きくおそれがわるが、実施例２の方法では残
存多結晶シリコン５７１０’・・・がある程度の幅をも
っているので。Body 2 [ml (a) about 1 deep n4'' Sawa bonding layer 1
2... Since it is completely formed, it is possible to prevent a fire from occurring more easily than by removing 1/j of Δg. In this case, the polycrystalline silicon film does not have the shape of the opening or the film thickness due to the silica diffusion V, which is different from the silicon oxide film.
Regarding C, t can be maintained by 1 degree with good controllability by RIEK. In addition, contact hole 8...
・In the conventional method in which a residual polycrystalline silicon film 10' is not formed on the side wall of ・H as in Example 2.
', 114-layer junction layer J2..., there is a great fear that the impurities will be diffused in the lateral direction (therefore, the short chaol effect will occur), but in the method of Example 2, the remaining polycrystalline silicon 5710'... has a certain width.
こうした危検性を避けることができる。These risks can be avoided.
なお、上記実施例１及び２ではいずれもリン拡散を行な
ったが、イオン注入法を用いてもよいことは勿論である
。Note that in both Examples 1 and 2, phosphorus diffusion was performed, but it goes without saying that ion implantation may also be used.
また、上記実施例１及び２では配線材料としてＡＩを用
いているが、これに限らず多結晶シリコン等を用いたダ
イレクトコンタクト形成にも同様に適用できる。Furthermore, although AI is used as the wiring material in the first and second embodiments, the present invention is not limited to this, and can be similarly applied to direct contact formation using polycrystalline silicon or the like.
以上詳述した如く１本発明の半導体装置の製造方法によ
れば、配線の１切線を防止するとともにＶキロ−ジャン
クシ１ン化によるＡｄの矢き抜けを防止し、素子の微細
化を達成できる等顕著な効果を奏するものである。As described in detail above, according to the method for manufacturing a semiconductor device of the present invention, it is possible to prevent one line breakage in the wiring, prevent Ad from passing through due to the formation of a V kilojunction, and achieve miniaturization of the device. It has a remarkable effect.
第１図（ａ）〜（ｆ）は本発明の実施例１におけるｎチ
ャネルＭＯ８トランジスタの製造方法を示す断面図、第
２図（−）及び（ｂ）は本発明の実施例２におｈ’ルｎ
チャネルＭＯ８）ランソスタの製造方法を示す断面図で
ある。
Ｊ・・・Ｐ型シリコン基板、Ｚ・・・フィールド酸化膜
、３・・・ダート酸化膜、４・・・ダート電極、５゜６
・・・ｎ◆型ソース、ト９レインｍ域、７・・・ＢＰ８
Ｇ膜、８・・・コンタクトポール、９・・・熱酸化膜。
１０・・・多結晶シリコン膜、ｌＯ′・・・残存多結晶
シリコン膜、１１・・・／ｌ配線、ノ２・・・ｎ４型接
合層。FIGS. 1(a) to (f) are cross-sectional views showing a method of manufacturing an n-channel MO8 transistor according to a first embodiment of the present invention, and FIGS. 'le n
FIG. 8 is a cross-sectional view showing a method of manufacturing a channel MO8) lansostar. J: P-type silicon substrate, Z: field oxide film, 3: dirt oxide film, 4: dirt electrode, 5°6
... n◆ type source, train 9 m region, 7...BP8
G film, 8... contact pole, 9... thermal oxide film. 10...Polycrystalline silicon film, lO'...Remaining polycrystalline silicon film, 11.../l wiring, 2...N4 type junction layer.
Claims (1)
堆積する工程と、該絶に膜の所定位ｒＩｔ、ＶＣコンタ
クトホール會開孔する工程と、該コンタクトホール内の
露出した基板表面に酸化膜を形成する工程と、全面に非
単結晶シリコン膜を堆積する工程と、異方性エツチング
によりコンタクトホール側壁部に非単結晶シリコン膜を
残存芒ゼる１程と、残存した非単結晶シリコン１ａをマ
スクとして前記酸化膜をエツチングする工程と、全面忙
配線材料を堆積した後、パターニングして所定の配線を
形成する工程とを具備したことを特徴とする半導体装ｂ
゛の製造方法。 （２１全面に非単結晶シリコン膜會堆積した後。 該非単結晶シリコン膜に不純物をドーグすることを特徴
とする特許請求の範囲第１項記載の半導体装置の製造方
法。 （３１コンタクトホール側壁部に残存した非単結晶シリ
コン膜をマスクとして酸化膜をエツチングした後、残存
した非単結晶シリコン膜及び露出した基板に不純物をド
ーグすることを特徴とする特ＩＦｌ−細求の範囲第１Ｊ
ｌｊｌ＋記載の半導体装置の製造方法。(1) A step of depositing an insulating film on the entire surface of the semiconductor substrate on which a dielectric layer has been formed, a step of opening a contact hole at a predetermined position of the film, and a step of forming an exposed substrate surface inside the contact hole. A step of forming an oxide film on the contact hole, a step of depositing a non-single crystal silicon film on the entire surface, a step of leaving a non-single crystal silicon film on the side wall of the contact hole by anisotropic etching, and a step of removing the remaining non-single crystal silicon film. A semiconductor device b characterized by comprising a step of etching the oxide film using crystalline silicon 1a as a mask, and a step of depositing a wiring material over the entire surface and then patterning it to form a predetermined wiring.
゛ manufacturing method. (After depositing a non-single-crystal silicon film on the entire surface of 21. The method for manufacturing a semiconductor device according to claim 1, characterized in that the non-single-crystal silicon film is doped with an impurity. (31 Contact hole side wall part After etching the oxide film using the remaining non-single crystal silicon film as a mask, the remaining non-single crystal silicon film and the exposed substrate are doped with impurities.
A method for manufacturing a semiconductor device according to ljl+.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58201320A JPS6092615A (en) | 1983-10-27 | 1983-10-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58201320A JPS6092615A (en) | 1983-10-27 | 1983-10-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6092615A true JPS6092615A (en) | 1985-05-24 |
Family
ID=16439049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58201320A Pending JPS6092615A (en) | 1983-10-27 | 1983-10-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6092615A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02224226A (en) * | 1988-11-21 | 1990-09-06 | Nippondenso Co Ltd | Manufacture of semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060114168A1 (en) * | 2004-11-30 | 2006-06-01 | Kathrein-Werke Kg | Antenna, in particular a mobile radio antenna |
| JP2012104982A (en) * | 2010-11-09 | 2012-05-31 | Hitachi Cable Ltd | Mobile communication base station antenna, and mobile communication base station antenna system |
| US20130093641A1 (en) * | 2010-07-19 | 2013-04-18 | Laird Technologies, Inc. | Multiple-Antenna Systems With Enhanced Isolation and Directivity |
| US8462071B1 (en) * | 2010-05-26 | 2013-06-11 | Exelis Inc. | Impedance matching mechanism for phased array antennas |
-
1983
- 1983-10-27 JP JP58201320A patent/JPS6092615A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060114168A1 (en) * | 2004-11-30 | 2006-06-01 | Kathrein-Werke Kg | Antenna, in particular a mobile radio antenna |
| US8462071B1 (en) * | 2010-05-26 | 2013-06-11 | Exelis Inc. | Impedance matching mechanism for phased array antennas |
| US20130093641A1 (en) * | 2010-07-19 | 2013-04-18 | Laird Technologies, Inc. | Multiple-Antenna Systems With Enhanced Isolation and Directivity |
| JP2012104982A (en) * | 2010-11-09 | 2012-05-31 | Hitachi Cable Ltd | Mobile communication base station antenna, and mobile communication base station antenna system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02224226A (en) * | 1988-11-21 | 1990-09-06 | Nippondenso Co Ltd | Manufacture of semiconductor device |
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