JPS61180357A - デ−タラツチ回路 - Google Patents

デ−タラツチ回路

Info

Publication number
JPS61180357A
JPS61180357A JP1987885A JP1987885A JPS61180357A JP S61180357 A JPS61180357 A JP S61180357A JP 1987885 A JP1987885 A JP 1987885A JP 1987885 A JP1987885 A JP 1987885A JP S61180357 A JPS61180357 A JP S61180357A
Authority
JP
Japan
Prior art keywords
latch
data
control signal
register
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987885A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0560134B2 (enrdf_load_stackoverflow
Inventor
Shigeki Kumagai
熊谷　茂樹
Yoshito Nakamura
義人 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Priority to JP1987885A priority Critical patent/JPS61180357A/ja
Publication of JPS61180357A publication Critical patent/JPS61180357A/ja
Publication of JPH0560134B2 publication Critical patent/JPH0560134B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
JP1987885A 1985-02-06 1985-02-06 デ−タラツチ回路 Granted JPS61180357A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987885A JPS61180357A (ja) 1985-02-06 1985-02-06 デ−タラツチ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987885A JPS61180357A (ja) 1985-02-06 1985-02-06 デ−タラツチ回路

Publications (2)

Publication Number Publication Date
JPS61180357A true JPS61180357A (ja) 1986-08-13
JPH0560134B2 JPH0560134B2 (enrdf_load_stackoverflow) 1993-09-01

Family

ID=12011463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987885A Granted JPS61180357A (ja) 1985-02-06 1985-02-06 デ−タラツチ回路

Country Status (1)

Country Link
JP (1) JPS61180357A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06129253A (ja) * 1992-10-13 1994-05-10 Fuji Heavy Ind Ltd シーケンシャルターボエンジンの過給圧制御方法
US6978391B2 (en) 2000-11-01 2005-12-20 Nec Electronics Corporation Asynchronous bus interface circuit, method of controlling the circuit, microcomputer, and device controlling method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06129253A (ja) * 1992-10-13 1994-05-10 Fuji Heavy Ind Ltd シーケンシャルターボエンジンの過給圧制御方法
US6978391B2 (en) 2000-11-01 2005-12-20 Nec Electronics Corporation Asynchronous bus interface circuit, method of controlling the circuit, microcomputer, and device controlling method

Also Published As

Publication number Publication date
JPH0560134B2 (enrdf_load_stackoverflow) 1993-09-01

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term