JPS61180357A - Data latch circuit - Google Patents

Abstract

PURPOSE:To transfer surely the data outputted from the transmission side to the reception side by adding plural latch registers and latch control circuits to a system where data are transferred from the transmission side without detecting the reception timing of the reception side. CONSTITUTION:The 1st latch register 21 latches temporarily the data which are transferred to a peripheral device 20 from a transmission register 11 of a CPU10 serving as the transmission side. In such a case, the latching operation is performed synchronously with the transmission control signal WR outputted from an MPU 14 of the CPU 10 via an I/O port 15. While the 2nd latch register 22 latches the data outputted from the register 21 and outputs them to the device 20. Here the latching operation is carried out synchronously with the latch control signal L outputted from a latch control circuit 23. Thus the CPU 10 can transfer surely the transmission data synchronous with the signal WR to the reception side without detecting the reception timing of the device 20.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a data latch circuit used in a data transmission/reception system.

[Technical Background of the Invention and Problems Therewith] Conventionally, when transferring data from a host computer to a peripheral device, there is a transfer method (handshake method) using a data latch circuit as shown in FIG. In this method, the data ★ output from the transmission register 11 on the transmission side, which is the host computer (hereinafter referred to as CPLI) 10, is
It is temporarily latched in the latch register 12. CPU 1
0 is a microprocessor (hereinafter referred to as MPU) 14 that creates data to be transferred to the peripheral device 13 on the receiving side.
It is equipped with

The MPU 14 outputs transfer data to the transmission register 11 and also outputs a transmission control signal (write control signal) A through the I10 port 15a. The latch register 12 synchronizes with the transmission control signal A (“0” is a significant signal) output from the I10 port 15a.
Latch the data output from 1.

At this time, the transmission 5i output from the I10 boat 15a
IIWJ signal @A is also applied to the reset terminal of flip-flop 16. The flip-flop 16 receives a data reception completion signal (“0” is a significant signal) from the peripheral device t13.
Until E is output, the M P LJ 14 heavy signal B on the transmitting side is output to the I10 boat 15b. At the same time, a busy signal B is also output to the peripheral device to confirm the presence or absence of data in the latch register. As a result, the MPU 14 outputs the next data from the transmission register 11 to the latch register 12 when the reception completion signal E is output from the peripheral device @13. In this way, the data sent from the CP LJ 10 will be transferred to the peripheral location 13 through the latch register 12.

The purpose of implementing the above-described transfer method is to prevent the peripheral device 13 on the receiving side from receiving data from the latch register 12 before the data transmission from the transmitting side to the latch register 12 is completed. It is. Therefore, the problem of the peripheral device 13 on the receiving side receiving data different from the original data can be avoided. However, in this method, c p u i
When data is transferred from o, the operation of the peripheral device 13 is temporarily stopped until the data transfer is completed. For this reason, the peripheral device 13 enters a state in which its operation is not constant.

In addition, as shown in FIG. 9, the CPU on the transmitting side
There is a method in which data is transferred from the transmitting side through the latch register 12 without the peripheral device 10 detecting the receiving state of the peripheral device 13. However, in the above-described transfer method, before data transmission from the transmitting side to the latch register 12 is completed, the peripheral device t13 on the receiving side transfers data to the latch register 12.
Data may be received from. Therefore, a problem arises in that the peripheral device 13 on the receiving side receives data different from the original data.

[Object of the Invention] An object of the present invention is to provide data that can reliably transfer data output from the transmitting side to the receiving side in a transmitting/receiving system in which the transmitting side transfers data without detecting the reception timing of the receiving side. The purpose of the present invention is to provide a latch circuit.

[Summary of the Invention] The present invention includes first and second latch registers, and the first latch register is configured to latch transmission data in synchronization with a transmission control signal from the transmission side. . Further, the second latch register is configured to latch data output from the first latch register in synchronization with the latch 1lilJIll signal from the latch control circuit. Based on the transmission υIII signal, the latch control circuit outputs a latch control signal corresponding to the latch timing set by the receiving side when data is not being transmitted. Further, the latch control circuit outputs a latch control signal that is changed so as to delay the latch timing set by the receiving side in the data transmission state.

like this'! The I4 data latch circuit makes it possible to reliably transfer data transmitted from the transmitting side at a predetermined timing to the receiving side.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing the configuration of a transmitting/receiving system according to an embodiment. In FIG. 1, a first latch register 21 is connected to a CPU (host computer) 1 on the sending side.
The data transferred from the 0 transmission register 11 to the peripheral device 20 is temporarily latched.

The first latch register 21 is the MP of CP Ll 10.
IJ (microprocessor) 14 to I10 boat 15
The latch operation is performed in synchronization with the transmission control signal WR outputted through the latch control signal WR. The second latch register 22 latches the data output from the first latch register 21 and outputs it to the peripheral device 20. The second latch register 22 is a latch #IJIl output from the latch control circuit 23.
The latch operation is executed in synchronization with the l signal.

Based on the transmission control signal WR output from the CPU 10, the latch control circuit 23 outputs a latch control signal synchronized with the reception control signal R output from the peripheral device 20 when data is not being transmitted. Furthermore, in the data transmission state, the latch control circuit 23 outputs a latch control signal that is changed to delay the launch timing of the reception control signal R based on the timing change signal CH output from the link @20. do.

FIG. 3 is a block diagram showing a specific example of the configuration of the data latch circuit and its peripheral circuits in the same embodiment. In FIG. 3, the first latch register 21 is a D-type latch circuit 30-1 that latches, for example, 8-bit data D1 to D8.
~30-8. D-type latch circuit 30-1 to 30-
8, a transmission control signal WR output from the CPU 10 of FIG. 1 is supplied to each clock terminal CP through inverters 31 to 33. Data D1 to D8 latched by the first latch register 21 are output to the second latch register 22 in synchronization with the transmission control signal WR. The second latch register 22 similarly consists of D-type latch circuits 34-1 to 34-8 that latch 8-bit data.

D-type latch circuit 34-1 of the second latch register 22
34-8, a latch control signal output from the latch control circuit 23 is supplied to each clock terminal CP.

The data latched by the D-type latch circuits 34-1 to 34-8 are output to the peripheral device 20 in synchronization with the latch control signal. The latch control circuit 23 includes a D-type flip 70 tube 35, a NAND circuit 36, and inverters 37 and 38. The flip-flop 35 has a data terminal input with the transmission control signal WR inverted by the inverter 31, and outputs an output signal Q to one input terminal of the NAND circuit 36. The other input terminal of the NAND circuit 36 receives the reception control signal R from the peripheral device 20, and outputs a latch control signal R. The reception control signal R is connected to the clock terminal CP of the flip-flop 35 by the inverter 37.
．． 38.

The peripheral device 20 includes shift registers 40 to 43, inverters 44 and 45, a NAND circuit 46, and a NOR circuit 47. The shift registers 40 to 43 operate according to the cycle of the repetitive operation signal fcy and the clock signal GK. The output signal Q1 of the shift register 40 is outputted to one input terminal of the NAND circuit 46 through the inverter 44. The NAND circuit 46 has its other input terminal supplied with the output signal Q2 of the shift register 41, and outputs the reception control signal R from its output terminal.

On the other hand, the NOR circuit 47 has a first input terminal supplied with the output signal @Q3 of the shift register 42, and a second input terminal supplied with the output signal @Q4 of the shift register 43.
5 and is given inverted. The NOR circuit 47 transmits the timing change signal CH, which is an output signal, to the latch control circuit 2.
It is output to the set input terminal of the flip 70 knob 35 of No. 3.

In the data latch circuit configured as described above, the operation of the same embodiment will be explained. First, M P LJ shown in FIG.
14 creates transmission data D and outputs it to the transmission register 11. Transmission data D stored in the transmission register 11 is output to the first latch register 21. At this time, a transmission control signal WR as shown in FIG.
Output from 0. The first latch register 21 is I1
Transmission control signal WR (rOJ
Data is taken in at the "0" level of the signal (significance signal), and the transmission data D is latched in synchronization with the rising edge of the signal. Latch data LD1 in the first latch register 21 is output to the second latch register 22. The second latch register 22 latches the data from the first latch register 21 in synchronization with the latch control signal output from the latch control circuit 23 as shown in FIG.

Latch data LD2 latched by second latch register 22 will be output to peripheral device 1120.

By the way, when the transmission control signal @WR is output from the CPU 10, the latch control circuit 23 detects the transmission state of the transmission data D from the transmission register 11. Transmission data D
is in the non-transmission state, the latch control circuit 23 outputs the reception i111111 signal R(rO
A latch control signal synchronized with J is a significant signal) is output. This latch control signal causes the second latch register 22 to latch the data from the first latch register 21. Specifically, when the transmission data D is in a non-transmission state, the transmission control signal WR of "1" is supplied to the data terminal of the 7-lip 70-tube 35 of the latch control circuit 23 shown in FIG. ing. At this time, when the reception control signal R as shown in FIG. 4 is supplied to the latch control circuit 23 from the NAND circuit 46 of the peripheral device 20, the latch control circuit 23 receives the second latch control signal R as shown in FIG. It will be output to the latch register 22 of.

Next, there is a case where the latch control circuit 23 receives the reception control signal R from the peripheral device 20 while the transmission data D is being transmitted. That is, as shown in FIG. 2, when the transmission control signal WR is rOJ, the reception control signal R is also rOJ.

The latch control circuit 23 outputs a falling latch control signal that is synchronized with the reception control signal R, and further outputs a rising latch control signal that is extended for a predetermined period from the rise of the reception control signal R. In this case, the extension period of the latch control signal is set based on the timing change signal CH output from the peripheral device 20. The second latch register 22 is connected to the first latch register 2 in synchronization with a latch control signal that is extended from the normal latch timing.
Latch data from 1.

Specifically, when the reception control signal R (rOJ) is output from the peripheral device 20 shown in FIG. 3 to the latch control circuit 23, the transmission control signal WR is output to the latch control circuit 23 as shown in FIG. Suppose that In the latch control circuit 23,
Since the timing change signal @CH is input to the set input terminal of the flip-flop 35 in advance, the output signal Q of the flip-flop 35 is "1". Therefore, the NAND circuit 36 outputs a latch control signal that rises in synchronization with the fall of the reception control signal R. When the reception control signal R rises, the transmission control signal WR is "0" as shown in FIG. That is, when the second latch register 22 latches in synchronization with the reception control signal R, the first latch register 21 performs a data latching operation in synchronization with the transmission control signal WR. The output signal Q of the flip-flop 35 determines the level of the transmission control signal WR when the reception control signal R rises, and since the transmission control signal WR is rOJ, it falls to rOJ. Therefore, the latch control signal falls once in synchronization with the rise of the reception control signal R, but continues to be in the "1" state again due to the output signal Q. The output signal Q of the flip-flop 35 rises to "1" in synchronization with the rise of the timing change signal CH output from the peripheral device 20. As a result, the latch control signal output from the latch control circuit 23 is output as a latch timing signal that is extended by the period Tr shown in FIG. 5 from the latch timing period determined by the received control signal @R. It turns out. In this case, the timing change signal C
The extension period Tr determined by H is longer than the pulse width TW1 of the transmission control signal WR as shown in FIG.
The period is shorter than 2.

In addition, the latch control circuit 23 outputs a latch control signal of a pulse that rises again for an extended period immediately after falling in synchronization with the reception control signal R, but the latch control signal is continuously extended by the pulse width Tr. A circuit that outputs pulses may also be used.

In this way, the sender C P Ll 10:
Transmission data synchronized with the transmission control signal WR can be reliably transferred to the reception side without detecting the reception timing of the peripheral device 20 on the reception side. In this case, when the timings of the transmission control signal WR and the reception control signal R from the peripheral device 20 overlap, the second latch register 22 latches the data at the latch timing changed so that the latch timing by the reception control signal R is delayed. do. therefore,
The second latch register 22 is the first latch register 2
1, the data is not latched before the transfer of the transmission data is completed, but the data that has been completely transferred is latched and output to the peripheral device 20.

FIG. 6 is a block diagram showing a specific circuit to which the data latch circuit of the present invention is applied, and FIG. 7 is a timing chart showing the operation of the circuit.

The circuit shown in FIG. 6 is a variable duty output circuit that generates a duty signal according to an external input signal.

This variable duty output circuit is connected to the second receiving register 6.
A comparison circuit 63 compares the value of 1 and the count value of the counter 62, and outputs a pulse signal with a pulse width corresponding to the period until the comparison results match. Second receive register 6
The timing to change the value of 1 is when all the values of the counter 62 are O, and the repetition cycle is constant.

The first receiving register 60 stores an external input signal according to the timing of the write signal WR. The signal stored in the first reception register 60 is transferred to the second reception register 61 at the timing of the latch control signal from the latch control circuit 23.

When the present invention is applied to such a variable duty output circuit, the external input signal will be reliably stored in the second receiving register 61. Therefore, it is possible to prevent the data from changing inside the variable duty circuit, so that when changing the duty value continuously, it is possible to change the duty value very smoothly. Note that the variable duty output circuit as described above is effective when used in a brightness modulation circuit of a display device.

[Effects of the Invention] As detailed above, according to the present invention, in a transmitting/receiving system in which the transmitting side transfers data without detecting the reception timing of the receiving side, data output from the transmitting side can be reliably transmitted to the receiving side. Can be transferred. Therefore, even if a change occurs in the system on the sending side, it is possible to easily transfer data to the receiving side. Also,
Since the sending side can simplify the processing for the data receiving side, it is possible to obtain the effect of improving the processing efficiency of the entire system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data latch circuit according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the embodiment, and FIG. 3 is a specific circuit of the embodiment. FIGS. 4 and 5 are timing charts for explaining the operation of the circuit shown in FIG. 3, and FIG. 6 shows the configuration of a variable duty output circuit when the present invention is specifically applied. FIG. 7 is a timing chart for explaining the operation of the circuit shown in FIG. 6, and FIGS. 8 and 9 are block diagrams each showing the configuration of a conventional data latch circuit. 10...CPU, 11...Transmission register, 14...
・Microprocessor, 15...110 boats, 20
...Peripheral device, 21...First latch register, 2
2... Second latch register, 23... Latch control circuit. Applicant's agent Patent attorney Takehiko Suzue α
Engineering≧Cr-〇- 1g hair"l)! 1K large

Claims (1)

[Claims] a first latch means for latching data transferred from a transmitting side to a receiving side according to the timing of a transmission control signal output from the transmitting side; Detects the data transmission state from the transmitting side, and outputs a latch control signal corresponding to the latch timing set by the receiving side when the data is not being transmitted, and outputs a latch control signal corresponding to the latch timing set by the receiving side when the transmitting side is in the data transmitting state. latch control means for outputting a latch control signal changed to delay latch timing; and latch control means for latching the data output from the first latch means in accordance with the latch control signal output from the latch control means. A data latch circuit comprising: second latch means for outputting to the receiving side.