JPS61179580A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the number of processes for forming a recess by shaping the recess up to the depth of a channel layer from the surface of a metallic thin-film through one-time etching process. CONSTITUTION:A source electrode 4 and a drain electrode 5 as first and second main electrodes are formed to a semiconductor proper 3 consisting of an N- GaAs channel layer 2 shaped to a semi-insulating GaAs substrate 1, an AuGe alloy layer 8 is applied onto the surface of the channel layer 2 between the source electrode 4 and the drain electrode 5 through evaporation, and an ohmic junction between the AuGe alloy layer 8 and the N-GaAs layer 2 is formed through heat treatment. A resist with an etching window 9 is applied and shaped as an etching mask 10, and the AuGe alloy layer 8 and the N-GaAs layer 2 are etched simultaneously by Ar ion beams 11 to form a recess 12. A metallic layer 13 such as a Ti layer as a gate electrode material is evaporated onto the surface of the wafer, the Ti layer 13 evaporated to sections except the recess 12 is removed through a lift-off, and the Ti layer 13 in the recess 12 is left as a gate electrode 7.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device with a recessed structure, and particularly to a field effect transistor with low source resistance.

(Prior Art) A semiconductor device having such a recessed structure is also disclosed in the literature: Proceedings of the 1985 National Congress of Optical and Radio Division of the Institute of Electronics and Communication Engineers (August 1981), pages 1-125.

FIG. 3 is a cross-sectional view for explaining the conventional structure of a field effect transistor among this type of semiconductor device and its manufacturing method. In order to obtain this conventional structure, the following steps were taken. Approx.
A semiconductor body 3 is formed by stacking n-GaAs 2 with a thickness of 00λ. Next, AuGe is deposited on this channel layer z.
The respective metals are laminated in the order of /Xi/Au to form a three-layered source electrode 4 and drain electrode 5, respectively. Approximately 1,000 etching steps are performed to form a recess 6, and Ti metal is deposited within this recess to form a Ti gate 7.

In the field effect transistor having the structure thus obtained, conduction electrons flowing from the source electrode 4 into the channel layer 2 as an n-GaAs layer are transferred to the gate electrode 7 whose channel is narrowed by controlling the potential of the gate electrode 7. It reaches the drain electrode 5 via the channel layer portion 2a located directly below. In other words, when these electrons conduct, they flow from the source electrode 4 to the channel layer portion 2a directly under the gate electrode 7.
and flows from this portion 2a to the drain electrode. In this case, since the parasitic resistance between the source electrode and the gate electrode and the parasitic resistance between the gate electrode and the drain electrode strongly influence the magnitude of the transconductance 5- of the field effect transistor, It is necessary to make the resistance as small as possible. In order to reduce this resistance, in the conventional structure, a recess is provided in the gate electrode forming part, and the gate electrode is provided within this recess, and two holes are provided between the source electrode and the gate electrode and between the gate electrode and the drain electrode. n-GaAs channel layer part 2
b and 2c were formed thickly.

(Problems to be Solved by the Invention) However, n-GaA forming this channel layer
The s-layer is 100Ω no matter how high the concentration of Si is added to it.
Since a sheet resistance of only about 10 is obtained, the transconductance 211 becomes small, resulting in a problem in that high-speed operation of the field effect transistor cannot be expected.

Therefore, the inventors of this application conducted many experimental studies to create field effect transistors with large transconductance, and found that this channel exists around the gate electrode, that is, on the channel layer between the gate electrode and the source and drain electrodes. Providing a metal thin film with a sheet resistance smaller than the sheet resistance of the layer reduces the parasitic resistance between the gate electrode and the source electrode and between the gate electrode and the drain electrode, increasing the transconductance. discovered.

However, after depositing this metal thin film, if a window for forming a recess in the channel layer is formed in this film, and then a new recess is formed in the channel layer in another etching process, the process is complicated and manual. There was a drawback that +1JJ was applied.

An object of the present invention is to form a groove or recess in a channel layer where a gate electrode is to be formed simultaneously with etching of the gold FIt thin film when such a metal thin film with a low sheet resistance is provided, thereby making it possible to form a self-aligned metal thin film. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a large transconductance in which a gate electrode is formed.

(Means for Solving the Problems) In order to achieve this object, the present invention includes a step of forming first and second main electrodes in the channel layer of the semiconductor body, and forming a recess in the channel layer. In a method of manufacturing a semiconductor device having a recessed structure, the method includes an etching step and a step of forming a control electrode in the recess.

Furthermore, the channel layer is coated with a thin metal film having a sheet resistance lower than that of the channel layer, and the recess is recessed from the surface of the metal thin film to the depth of a portion of the channel layer by a single etching process. It is characterized by the formation of

(Function) As described above, according to the method of the present invention, a metal thin film with low sheet resistance is provided in ohmic contact with the channel layer, and etching of this metal thin film and etching of the channel layer are simultaneously performed by ion beam etching. Therefore, the number of steps for forming the recess can be reduced, and the recess can be formed in a short time.

A gate electrode can be formed in a self-aligned manner using the mask used in this etching.

Furthermore, since a metal thin film with low sheet resistance is used, the current path is gate electrode → metal thin film → channel layer part around the recess → channel layer part directly under the gate electrode →
Chang wood layer area around the recess → drain metal thin film →
Being formed with a train electrode has the advantage that the path is shorter and therefore the parasitic resistance is smaller, resulting in a larger transconductance y-. in this case,
The transconductance 9- becomes at least 20% larger than in the conventional case.

(Example) Hereinafter, an example of the present invention will be described with reference to FIGS. 1(A) to (F) and FIG. 2. It should be noted that these figures merely schematically illustrate the shapes, dimensions, and arrangement relationships of each component to the extent that the present invention can be understood. Furthermore, each figure shows a portion of a semiconductor device in a cross-sectional view, and Components that are the same as those shown in FIG. 3 are indicated with the same reference numerals, and hatching indicating a cross section is partially omitted to avoid complicating the diagram.

FIGS. 1A to 1F are manufacturing process diagrams for explaining one embodiment of the method of the present invention, and each figure is a sectional view showing the state of a wafer at a main process step. The semiconductor device of this embodiment has the same layer structure as the conventional semiconductor device shown in FIG.

First, the n-Ga layer provided on the upper side of the semi-insulating GaAs substrate 1 is
A source electrode 4 and a drain electrode 5, which are first and second main electrodes, are formed on a semiconductor body 3 made of a channel layer 2 of As (FIG. 1(A)).

Next, on the surface of the channel layer 2 between the source electrode 4 and the drain electrode 5, a metal thin film 8 having a sheet resistance lower than that of the channel layer 2 is formed, for example, an AuGe film having a thickness of about 500 nm.
An alloy layer is deposited by vapor deposition (FIG. 1(B)), and the wafer is then heat treated at a temperature of about 450° C. for 1 minute to diffuse Ge from the AuGe alloy layer 8 into the channel layer 2. , to form an ohmic junction between the AuGe alloy layer 8 and the n-GaAs layer 2.

Next, a resist having an etching window 9 corresponding to the region where the gate electrode, which is the control electrode 7, is to be formed is deposited as an etching mask 10 (FIG. 1(C)). 8 and on the source and drain electrodes 4 and 5.

Next, the Ar ion beam 11 is used to remove the AuGe alloy layers 8 and n.
- At the same time, the GaAs layer 2 is etched to form a recess 12 (FIG. 1(D)). By this etching, Au
The Ge alloy layer is an AuGe electrode portion 8 connected to the source electrode.
a, and the AuGe electrode portion 8b connected to the drain electrode 5
are electrically separated from each other.

Next, a metal layer 13, for example, a Ti layer, which is a gate electrode material, is deposited on the surface of this wafer (FIG. 1(E)), and then,
The Ti layer 13 deposited outside the recess 12 is removed by lift-off, leaving the Ti layer 13 inside the recess 12 as the gate electrode 7 (FIG. 1(F)).

As is clear from the above description, according to the present invention, n-GaAs is formed on the surface of the n-GaAs layer 2 between the gate and drain electrodes 4 and 5 and around the recess 12.
Since the AuGe electrode portions 8a and 8b can be formed in ohmic contact with the layer 2 and have a sheet resistance lower than that of the n-GaAs layer 2, the parasitic resistance can be reduced, and as a result, the transconductance 9- can be increased. I can do it.

Furthermore, in forming the gate electrode 7, the formation of the recess 12 in the n-GaAs layer 2 and the etching of the AuGe alloy layer 8 can be easily and simultaneously performed by ion beam etching.

Furthermore, the formation of the gate electrode 7 can be easily and easily performed in a self-line manner by using a lift-off technique.

Although GaAs was used as the semiconductor in this example,
Other types of semiconductors may be used, and although the conductivity type of the channel layer 2 is n-type, it may be p-type.

FIG. 2(A) is a cross-sectional view schematically showing a part of a high electron mobility field effect transistor for explaining another embodiment of the present invention. In this structure, the semiconductor body 3 consists of a semi-insulating GaAs substrate l, an undoped AQGaAs layer 14 stacked sequentially on the semi-insulating GaAs substrate l, and a Si layer l x 10".
n”-AQ with a thickness of about 200 people with additions of about c+a-3
15 GaAs layers, approximately 500 without added impurities! ? GaAs layer 16, Si with a thickness of 5 x 10 cm
-GaA with a thickness of about 500 with addition of about -3
It consists of an n''-GaAs layer 18 doped with sR 17 and Si to an extent of 2 x 10'Cm-'. In this case, the channel layer 2 consists of layers 16, 17 and 18. Note that 19 is E MIGaAs layer 15 and Ga
This is a two-dimensional electron layer accumulated on the GaAs layer 16 side of the bonding interface with the As layer 16.

The deposition of the source electrode 4, the drain electrode 5, the metal thin film 8, the etching of the recess 12, and the formation of the gate electrode 7 on the semiconductor body 3 can be performed in the same manner as in the first embodiment described above. Detailed explanation will be omitted. In this example, other than AuG which forms the source and drain electrodes 4 and 5, the i/Au layer and AuG
The e-electrode portions 8a and 8b are heat-treated at a temperature of about 450°C for 1 minute to form an ohmic contact with the nj-GaAs layer 18. When added at a high concentration of -3, this e-GaAs can be added without heat treatment.
Layer 18 forms an ohmic contact with AuGe alloy layer 8 .

Energy band diagrams of this structure in cross sections along the line AA and line BB are shown in FIGS. 2(B) and 2(C), respectively. This energy band diagram shows the state when the source electrode 4 and gate electrode 7 are short-circuited, and 20 is the Fermi level.

In order to operate a transistor with this structure, e-GaA
Electrons are caused to flow into the s layer 18, and the inflow electrons are
- The conduction electrons flow into a channel formed by the two-dimensional electron layer 19 via the GaAs layer 17, and the flow rate of conduction electrons in this channel is controlled by the gate voltage applied to the gate electrode 7. The electrons flowing directly under the gate electrode 7 are n -Ga
AuG via the As layer 17 and the n''-GaAs layer 18
It flows to the e-electrode portion 8b and flows out to the drain electrode 5 connected thereto.

Incidentally, in this embodiment, S is applied to the nj-GaAs layer 18.
When the i-addition amount is as high as IXlocm-', each electrode 4.5.8a, 8b may be formed of a metal film other than AuGe.

Furthermore, instead of the combination of GaAs and AQGaAs described above, In, gGa, 47As/InP, A
InP instead of QGaAs or Ga547. In, 53As, AQ GaAs0, AQo, 41 ■”oJLA S may be used instead.

Furthermore, instead of the combination of n-type GaAs and AQGaAs, a combination of p-type GaAs and AQGaAs may be used. In that case, each AuGe electrode 4.5.8a, 8b Preferably, it is an AuZn layer.

Furthermore, in the embodiments described above, the first main electrode is formed first,
Although the second main electrode is formed after that, it is also possible to form the second main electrode first.

Moreover, the thickness of each layer can be set to an appropriate thickness depending on the purpose other than the thickness mentioned above.

Note that the present invention can be widely applied to transistors having a recessed structure including first and second main electrodes and a control electrode.

(Effects of the Invention) As is clear from the above description, according to the method of the present invention, the underlying channel layer is formed between the first main electrode and the control electrode of the semiconductor device, and between the control electrode and the second main electrode. Since a metal electrode layer is provided which has a sheet resistance smaller than the sheet resistance and is in ohmic contact with this channel layer, n
In the case of the type GaAs layer, the parasitic resistance is reduced by more than an order of magnitude to about 10Ω/hole or less compared to the conventional one, and the transconductance of 9m is expected to increase.

Furthermore, according to the method of the present invention, a metal thin film with low sheet resistance is provided in ohmic contact with the channel layer, and etching of this metal thin film and channel layer can be performed simultaneously by ion beam etching. , the number of steps for forming the recess can be reduced, and the recess can be formed in a short time.

A gate electrode can be formed in a self-aligned manner using the mask used in this etching.

Therefore, according to the present invention, parasitic resistance is reduced and manufacturing is simple and easy, so it is suitable for application to field effect transistors for microwaves with a high cutoff frequency and field effect transistors for high speed digital circuits. .

[Brief explanation of the drawing]

FIGS. 1(A) to (F) are process diagrams showing the manufacturing process of a semiconductor device for explaining one embodiment of the semiconductor manufacturing method of the present invention, and FIGS. A schematic cross-sectional view showing the structure of a semiconductor device for explaining another embodiment of the semiconductor manufacturing method; FIG. 3 is a schematic cross-sectional view showing the structure of the semiconductor device for explaining the conventional semiconductor device manufacturing method; It is a front view. ■... Semi-insulating GaAs substrate 2... Channel layer (or n-GaAs layer) 3...
...Semiconductor body 4...First main electrode (source electrode) 5...Second main electrode (drain electrode) 7...Control electrode (gate electrode) 8...Thin metal electrode, 8a, 8b ...AuG
e-electrode portion 9...Effink window, 10...Etching mask 11...Ar ion beam, 12.
...Recess 13...Metal layer 14...AQGaAs layer 15-n''' with no impurity added
-AQGaAs layer 16... Impurity-free GaAs layer 17-...-n -GaAs layer, l8...
E-GaAs layer 18... two-dimensional electronic layer, 20...
・Fermi level. Patent applicant Oki Electric Industry Co., Ltd.
% S'-Q h 2 b mm) 1 spider ~
N = Q - no J2
, 2'a 2C Procedural amendment March 6, 1986

Claims (1)

[Claims] A recess comprising the steps of forming first and second main electrodes in a channel layer of a semiconductor body, an etching step of forming a recess in the channel layer, and a step of forming a control electrode in the recess. The method for manufacturing a semiconductor device having a structure further includes the step of depositing a metal thin film having a sheet resistance smaller than that of the channel layer on the channel layer, and depositing the metal thin film from the surface of the metal thin film to a depth of a part of the channel layer. A method of manufacturing a semiconductor device, characterized in that the recess is formed by one etching step.