JP2002016085A - Junction field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a JFET which is superior in breakdown voltage and will not be easily affected by impurity concentration or variations in the thickness of a channel region or the like. SOLUTION: The JFET is provided with a second conductivity-type SiC film 2 formed on an SiC substrate 1, a first conductivity-type SiC film 3, including a channel region 4 formed on the second conductivity-type SiC film, source and drain regions 5 and 6 formed on the first conductivity-type SiC film, so as to be formed on the both sides o the channel region, gate electrodes 13 formed on the second conductivity-SiC film, and a conductive film 7 which is brought into contact on the channel region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a junction field effect transistor using SiC, and more particularly, to a junction field effect transistor having low on-resistance.

[0002]

2. Description of the Related Art Conventional junction type field effect transistors (J
FET: Junction Field Effect Transistor)
When the ET was in the ON state, a current was flowing through the channel region. The impurity concentration in the channel region is limited to secure predetermined transistor characteristics, and cannot be so high. For this reason, the electric resistance of the channel region tends to increase.

[0003]

The characteristics of the transistor are strongly affected by the high electric resistance of the channel region. Further, since the electric resistance of the channel region increases and decreases depending on the impurity concentration, the thickness of the channel region, and the like, the transistor characteristics greatly fluctuate according to variations in the impurity concentration, the thickness, and the like. If a high-concentration impurity element is implanted for the purpose of reducing the electric resistance of the channel region in order to avoid such a variation between the elements, the withstand voltage performance deteriorates. For this reason, there has been a demand for a JFET that is not easily affected by variations in the impurity concentration of the channel region and its thickness without using a high-concentration impurity.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a JFET which has excellent withstand voltage and is not easily affected by variations in the impurity concentration of the channel region and its thickness.

[0005]

According to a first aspect of the present invention, a JFET includes a second conductive type semiconductor film formed on a semiconductor substrate, and a second conductive type semiconductor film formed on the second conductive type semiconductor film.
A first conductivity type semiconductor film including a channel region, and a first conductivity type semiconductor film formed on the first conductivity type semiconductor film, the source regions being separately formed on both sides of the channel region And a drain region, a gate electrode provided in contact with the second conductivity type semiconductor film, and a conductive film provided in contact with the surface of the channel region.

[0006] With the above configuration, the channel region and the conductive film are arranged in parallel to the current flowing through the channel. Therefore, for example, when the electric resistance of the conductive film is lower by one order than that of the channel region, the current flowing through the conductive film in the ON state is about 10 times lower than that of the channel region.
Twice as high. For this reason, even if there is a variation in the impurity concentration or a variation in the thickness of the channel region, the influence on the transistor characteristics is negligible, and the influence of the fluctuation of these factors does not substantially matter. On the other hand, in the off state, the negative potential (reverse bias voltage) applied to the gate electrode causes the first conductive type semiconductor layer including the channel region to be connected to the second conductive type semiconductor layer below the first conductive type semiconductor layer. The depletion layer extends toward the conductive semiconductor layer. The depletion layer is wider in proportion to the reverse bias voltage and inversely proportional to the impurity concentration of the first conductive layer and the second conductive layer. When the depletion layer blocks the channel region, the path of carriers passing through the channel region is blocked. For example, in the case where the above conductive film is disposed so as not to be in contact with the first conductive type semiconductor layers on both sides sandwiching the channel region, the above-described cutoff cuts off not only the channel region but also the conductive film. You. As a result, the off state can be easily realized. Further, even when the conductive film is in contact with only one side of the first conductivity type semiconductor layer and is not in contact with the other, the off state can be easily realized and the resistance can be reduced. This decrease in resistance reduces the effects of variations in impurity concentration and variations in the thickness of the channel region. When both side portions of the conductive film are in contact with the first conductivity type semiconductor layer, respectively, the resistance is further reduced and further affected by the variation in the impurity concentration and the variation in the thickness of the channel region. It becomes difficult. The first conductivity type may be n-type or p-type, and the second conductivity type may be p-type or n-type. Further, the semiconductor substrate may be an n-type Si substrate or a p-type Si substrate,
An n-type SiC substrate or a p-type SiC substrate may be used.

In the JFET according to the first aspect, the length of the conductive film along the channel length direction is shorter than the channel length.

With this configuration, it is possible to eliminate the difficulty of achieving the off operation when both ends of the conductive film are in contact with the side walls. That is, since at least one end of the conductive film is insulated from the side wall, it can be turned off by blocking the channel region on the side where the depletion layer is insulated.

In the JFET according to the first aspect, the channel region has a thickness in the junction between the second conductive type semiconductor film and the first conductive type semiconductor film formed on the second conductive type semiconductor film. The width is smaller than the width of the depletion layer in the first conductivity type semiconductor film due to the diffusion potential.

With the above structure, when the gate potential is zero, the depletion layer generated by the diffusion potential at the junction between the second conductivity type semiconductor film and the first conductivity type semiconductor film blocks the entrance and exit of the channel region. . For this reason, a normally-off JFET can be obtained, and can be used for controlling a rotating machine or the like without taking measures against failure of the gate circuit. Further, power consumption in the ON state can be reduced, and furthermore, influences such as variations in impurity concentration in the channel region can be avoided.

The JFET according to the second aspect of the present invention comprises:
In the front (front) surface, the first first conductivity type semiconductor layer having an impurity concentration determined by the element breakdown voltage formed on the surface and the surface of the first first conductivity type semiconductor layer A substrate having a conductive film deposited to a high position. The JFET further includes a region of the second first conductivity type semiconductor layer provided on the substrate and on both sides of the conductive film up to a position higher than the surface of the conductive film;
A source region of the first conductivity type semiconductor layer disposed on each of the two regions of the first conductivity type semiconductor layer; and a region on the substrate and outside of each of the second first conductivity type semiconductor layers. A second conductivity type provided with a gate electrode and having a second conductivity type impurity concentration higher than the value of the first conductivity type impurity concentration of the second first conductivity type impurity layer formed on the substrate; The semiconductor device includes a semiconductor layer and a drain region of the first conductivity type semiconductor layer provided on the back surface of the substrate.

With the above structure, the electric current of the drift (channel) path that traverses the substrate in the thickness direction from the two source regions provided on the front (front) surface side of the semiconductor substrate to the drain region on the back surface of the semiconductor substrate. Resistance decreases. That is, the portion where the conductive film is deposited on the path forms a circuit partially parallel to the path. Even in the case of a JFET in which carriers flow in the thickness direction of the substrate as described above, it is possible to substantially reduce the electric resistance of the channel region along the same direction. Therefore, the vertical JFE
In addition to the high withstand voltage characteristic unique to T, the power consumed in the channel region can be reduced, and the heat generation problem can be solved. In order to apply a reverse bias voltage to the junction between the second first conductivity type semiconductor layer and the second conductivity type semiconductor layer to extend the depletion layer to the second first conductivity type semiconductor layer and realize an off state It is necessary that the above relationship be satisfied for the concentrations of these two layers. However, the impurity concentration of the second first conductivity type semiconductor layer may be higher or lower than the impurity concentration of the first first conductivity type semiconductor layer. The first first conductivity type semiconductor layer having the impurity concentration determined by the element withstand voltage may be formed on the surface of the substrate, or the substrate itself may be the first first conductivity type semiconductor layer. It may be.

In the JFET according to the second aspect, a groove is provided on the front surface of the semiconductor substrate, and the conductive film is deposited so as to fill the groove.

According to the above configuration, in the vertical JFET, the conductive film is inserted into the deeper drift (channel) path, so that the current flowing through the drift (channel) is lower, and the current is more increased by the conductive film. It will flow a lot. Therefore, variation between elements due to the impurity concentration of the drift (channel) path and the like is further reduced.

In the JFET according to the second aspect, the low-concentration first-conductivity-type semiconductor layer has a cross-sectional length from the second-conductivity-type semiconductor film to the conductive film, the second-conductivity-type semiconductor film having a low-concentration. And a width of a depletion layer in the low-concentration first-conductivity-type semiconductor film due to a diffusion potential at a junction between the low-concentration first-conductivity-type semiconductor film inside the second-conductivity-type semiconductor film (claim) Item 6).

According to the above configuration, when the gate voltage is zero, the low-concentration first conductivity type semiconductor film is reduced by the diffusion potential into a depletion layer formed at a junction with the second conductivity type semiconductor film located outside the first conductivity type semiconductor film. Will be shut off. The conductive film is a source region in contact with the low-concentration first conductivity type semiconductor film,
Since there is no contact, the path to the conductive film is also blocked by the above-described blocking. As a result, even a vertical JFET having high withstand voltage and low power consumption in the ON state can be normally off.

JFE in the first and second aspects
In T, the conductive film is any one of a metal film and a semiconductor film containing a high concentration of impurities.

With the above configuration, a low-resistance parallel bypass can be easily provided in the channel region using a low-resistance metal film. Any metal film can be used as long as it becomes an electrode material. However, considering ease of etching and high conductivity, aluminum (Al) or an aluminum alloy is preferable.

JFE in the above first and second aspects
In T, the semiconductor substrate is a SiC substrate, the first conductivity type semiconductor film is a first conductivity type SiC film, and the second conductivity type semiconductor film is a second conductivity type SiC film.

SiC has excellent pressure resistance, the mobility of carriers is as high as that of Si, and a high saturation drift velocity of carriers can be obtained. Therefore, the above JFE
T can be used for a high-power high-speed switching element.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view showing a JFET according to a first embodiment. In FIG.
A p-type SiC film 2 is formed on an iC substrate 1, and an n-type SiC film 3 having a reduced channel region 4 is formed thereon. On the n-type SiC film 3 on both sides of the channel region 4, n @ +
Type SiC films 5 and 6 are formed, and source and drain electrodes 11 and 12 are formed on the respective regions.
Further, two gate electrodes 13 are formed on the p-type SiC film and sandwich the source and drain regions in plan view. The greatest feature of the present embodiment is that aluminum film 7 is formed on the channel region. The cross-sectional length of the aluminum film is smaller than the channel length L, and when viewed in plan, the aluminum film is included in the channel region. That is, the aluminum film 7 is not in contact with the walls on both sides of the channel region 4.

Next, the operation of the JFET will be described. First, in the ON state, carriers flow through the channel region 4 along the substrate surface. At this time, if the aluminum layer 7 is arranged on the channel region, the current becomes
It flows through a parallel circuit composed of the channel region 4 and the aluminum film 7. When the electric resistance of the aluminum film is lower than the electric resistance of the channel region by, for example, one order, the current flowing through the aluminum film 7 becomes higher by approximately one order than the current flowing through the channel region. As a result, the current flowing in the semiconductor can be almost ignored, and the transistor characteristics hardly depend on the impurity concentration of the channel region or the thickness a of the channel region. As a result, it is not necessary to dope high-concentration impurities in order to reduce the electric resistance of the channel region, and other transistor characteristics without variation can be secured while maintaining high withstand voltage performance.

On the other hand, in the off state, a negative potential is applied to the gate electrode 13 shown in FIG. Therefore, the depletion layer 8 is formed at the junction between the p-type SiC film 2 and the n-type SiC film 3.
Are formed, and as the absolute value of the negative potential increases, the width of the depletion layer increases toward the side where the impurity concentration is lower, almost in inverse proportion to the impurity concentration. When the tip 8a of the depletion layer width exceeds the thickness a of the channel region 4, the channel region is cut off by the depletion layer,
Carrier passage is impeded. As described above, since the aluminum film 7 is not in contact with the walls on both sides of the channel region 4, the off state is realized when the leading end 8a of the depletion layer width exceeds the channel region thickness a.

(Embodiment 2) The JFET in Embodiment 1 shown in FIGS. 1 and 2 has a normally-on state in which a current flows through the channel region 4 when the gate voltage is zero. . Normally-on JFE
When T is used for controlling a rotating device or the like, rotation may not be stopped if a failure occurs in the gate circuit. Therefore, it is necessary to provide a mechanism for coping with the failure of the gate circuit. Since it is troublesome to provide such a mechanism, a normally-off JFET is desirable. In the second embodiment, a normally-off JFET will be described. As shown in FIG. 3, the greatest feature of the present embodiment is as follows. The width of the depletion layer generated by the diffusion potential at the pn ₂ junction, that is, the width of the depletion layer generated when the gate potential is zero, is set to be larger than the thickness a of the channel region. For example, by setting (a) the concentration n ₂ to 1 × 10 ¹⁶ cm ⁻³ and (b) the thickness a of the channel region to about 500 nm or less, the width of the depletion layer due to the diffusion potential is reduced by the thickness a of the channel region.
Can be normally off.

By employing the above structure, it is possible to realize a normally-off JFET which does not decrease the withstand voltage performance and does not vary its characteristics due to variations in channel concentration and the like. As a result,
It is possible to use a control device such as a large rotating device without providing a gate circuit failure countermeasure mechanism.

(Embodiment 3) FIG. 4 is a sectional view showing a JFET in Embodiment 3. In FIG.
The n-type impurity concentration of the type SiC substrate has an impurity concentration determined by the withstand voltage of the element, and has a first first conductivity type (n
(Type) Also serves as a semiconductor layer. An aluminum film 7 is formed to a predetermined height on the front surface of the n-type SiC substrate 9 so as to fill the groove. On both sides of the aluminum film 7, n-type SiC films for forming the channel regions 4a and 4b are formed. The heights of the channel regions 4a and 4b are set slightly higher than the height of the aluminum film 7. P-type SiC films 2a and 2b are formed outside in contact with the two channel regions 4a and 4b, and a gate electrode 13 is disposed thereon. Source regions 5a and 5b are formed on the two channel regions 4a and 4b, respectively, and source electrodes 11a and 11b are disposed thereon. Also, n-type SiC
An n + -type SiC film is formed on the back surface of the substrate 9, and the drain electrode 12 is disposed thereon. It goes without saying that an ohmic contact is formed between each electrode and the semiconductor layer.

In the ON state, carriers are in the source region 5
a, 5b across the substrate in the thickness direction,
Flows to That is, a normally-on JFET is realized. At this time, the current is diverted to the path between the aluminum film 7 and the channel region and the n-type SiC substrate, but the current mainly flows on the aluminum film side because the electric resistance of the aluminum film is very low. For this reason, there is no influence from the impurity concentration or the dimensional change in the channel region, and the variation between elements can be greatly reduced.

In the off state, a negative voltage (-15 to -25 V) having a large absolute value is applied to the gate. Therefore, a reverse bias voltage is applied to the junction between the channel regions 4a and 4b and the p-type region outside the gate region. Is applied. For this reason, the width of the depletion layer increases mainly on the side with the lower impurity concentration. When the depletion layer spreads over the entire channel region, the path from the source region to the drain region 6 via the substrate 9 is cut off.
Since the aluminum film 7 has a lower height than the channel regions 4a and 4b, a path passing through the aluminum film is also cut off, and an off state is realized.

Since the vertical JFET shown in FIG. 4 has high withstand voltage, the use of the JFET of this embodiment makes it possible to provide an element for high-voltage power with a small characteristic fluctuation between elements. .

In FIG. 4, the channel region is cut off at a gate voltage of zero and an off state is realized by setting the cross-sectional length l of the channel region to be shorter than the depletion layer width due to the diffusion potential of the pn-junction. I do. That is,
A normally-off JFET can be obtained.

[0032]

EXAMPLE A prototype of the JFET shown in Embodiment 1 of FIG. 1 was manufactured, and the channel resistance when 1 V was applied was measured. Book J
The FET was a 100V withstand voltage element. The impurity concentration of the n-type SiC films 3 and 4 including the channel region is 4.0 × 10 ¹⁷ c
m ⁻³ , and the channel length L is 1000 nm (10 μm).
m), and the thickness a of the channel region was set to 230 nm.

[0033]

[Table 1]

According to the results shown in Table 1, the channel resistance of the conventional JFET having no metal film in the channel region (JFET obtained by removing the aluminum film from the JFET of FIG. 1) was 7.8 mΩcm ² . On the other hand, the channel resistance of the JFET of the first embodiment (example of the present invention) including the aluminum film was significantly reduced to 1.6 mΩcm ² . Therefore, it was found that the channel resistance was significantly reduced by the example of the present invention. Therefore, it is not affected by the fluctuation of the impurity concentration of the channel region or the thickness of the channel region,
A JFET with small variation between elements was obtained.

Although the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. Not limited. The scope of the present invention is shown by the description of the claims, and further includes all modifications within the meaning and scope equivalent to the description of the claims.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a JFET according to a first embodiment.

FIG. 2 is a schematic diagram illustrating an off state of the JFET of FIG. 1;

FIG. 3 is a cross-sectional view of a JFET according to a second embodiment.

FIG. 4 is a cross-sectional view of a JFET according to a third embodiment.

[Explanation of symbols]

1 SiC substrate, 2, 2a, 2bp p-type SiC film, 3
n-type SiC film, 4, 4a, 4b channel region, 5, 5
a, 5b source region, 6 drain region, 7 aluminum film, 8 depletion layer, 8a tip of depletion layer width, 9 n-type SiC substrate, 11, 11a, 11b source electrode, 12
Drain electrode, 13 gate electrode, L channel length, a channel region thickness, l channel region cross-sectional length.

Claims (8)

[Claims] A second conductive type semiconductor film formed on a semiconductor substrate; a first conductive type semiconductor film including a channel region formed on the second conductive type semiconductor film; A film made of a first conductivity type semiconductor formed on the conductivity type semiconductor film, wherein the source region and the drain region are formed separately on both sides of the channel region; A junction field effect transistor including a gate electrode provided in contact with the conductive film and a conductive film provided in contact with the surface of the channel region. 2. The junction field effect transistor according to claim 1, wherein a length of the conductive film along a channel length direction is shorter than a channel length. 3. The semiconductor device according to claim 1, wherein a thickness of the channel region is determined by a diffusion potential at a junction between the second conductivity type semiconductor film and the first conductivity type semiconductor film formed on the second conductivity type semiconductor film. 3. The junction field effect transistor according to claim 1, wherein the width of the junction field effect transistor is smaller than a width of a depletion layer in the first conductivity type semiconductor film. 4. A first first conductivity type semiconductor layer having an impurity concentration determined by an element withstand voltage formed on the front surface thereof, and the first first conductivity type semiconductor layer. A substrate having a conductive film deposited to a position higher than the surface of the semiconductor layer; and a second provided on the substrate and on both sides of the conductive film up to a position higher than the surface of the conductive film. A region of the first conductivity type semiconductor layer; a source region of the first conductivity type semiconductor layer disposed on each of the two regions of the second first conductivity type semiconductor layer; A second conductivity type film formed outside each of the second first conductivity type semiconductor layers and having a higher value than the concentration of the first conductivity type impurity of the second first conductivity type impurity layer. A second conductivity type semiconductor layer having an impurity concentration and provided with a gate electrode; And a drain region of a first conductivity type semiconductor layer provided on the back surface of the plate, the junction field effect transistor. 5. The junction field effect transistor according to claim 4, wherein a groove is provided on a front surface of the semiconductor substrate, and the conductive film is deposited so as to fill the groove. 6. A second conductive type semiconductor film, wherein the low-concentration first conductive type semiconductor layer has a cross-sectional length from the second conductive type semiconductor film to the conductive film. 6. The width of a depletion layer in the low-concentration first conductivity type semiconductor film due to a diffusion potential at a junction with the low-concentration first conductivity type semiconductor film inside the type semiconductor film. Junction field effect transistor. 7. The semiconductor device according to claim 1, wherein the conductive film is one of a metal film and a semiconductor film containing a high concentration of impurities.
7. The junction field-effect transistor according to any one of items 6 to 6. 8. The semiconductor device according to claim 1, wherein the semiconductor substrate is a SiC substrate, the first conductivity type semiconductor film is a first conductivity type SiC film, and the second conductivity type semiconductor film is a second conductivity type SiC film. 8. The junction field-effect transistor according to any one of 1 to 7.