JP5348171B2 - Junction field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a JFET excellent in a break down voltage, and hard to be affected by the variations of impurity concentration or thickness or the like in a channel region. <P>SOLUTION: An aluminum film 7 is formed on the one face of an SiC substrate 9. Channel regions 4a, 4b comprising an SiC film are formed in the both sides of the aluminum film 7 as contacting to the aluminum film 7. Source electrodes 11a, 11b are formed on the channel regions 4a, 4b through source regions 5a, 5b. A gate electrode 13 is formed in the opposite side of the aluminum film side 7 in the channel regions 4a, 4b through p-type SiC films 2a, 2b. A drain region 6 is formed on the other side of the SiC substrate 9. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a junction field effect transistor using SiC, and more particularly to a junction field effect transistor having a low on-resistance.

  In a conventional junction field effect transistor (JFET), a current flows through the channel region when the JFET is on. The impurity concentration of the channel region is limited to ensure predetermined transistor characteristics and cannot be so high. For this reason, the electrical resistance of the channel region tends to increase.

  The characteristics of the transistor are strongly influenced by the high electric resistance of the channel region. In addition, since the electric resistance of the channel region increases and decreases depending on the impurity concentration, the thickness of the channel region, and the like, the transistor characteristics greatly vary according to variations in the impurity concentration, the thickness, and the like. In order to avoid such variation between elements, if a high concentration impurity element is implanted for the purpose of reducing the electrical resistance of the channel region, the withstand voltage performance deteriorates. Therefore, there has been a demand for a JFET that is not easily affected by variations in the impurity concentration and thickness of the channel region without using a high concentration of impurities.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a JFET that has excellent pressure resistance and is not easily affected by variations in the impurity concentration and thickness of the channel region.

  A JFET according to one aspect of the present invention includes a first semiconductor layer of a first conductivity type having an impurity concentration determined by an element breakdown voltage, and a first semiconductor layer having one surface and the other surface facing each other. A conductive film formed on the first surface, and a first conductive film formed on one side of the first semiconductor layer so as to be in contact with the conductive film on both sides of the conductive film and provided at a position higher than the surface of the conductive film. A pair of channel regions of the type, a pair of source regions of the first conductivity type each disposed on each of the pair of channel regions, and a pair of each on the one surface of the first semiconductor layer The second conductivity type 1 having a concentration of the second conductivity type impurity higher than the concentration value of the first conductivity type impurity in the channel region and disposed on the opposite side of each channel region of the channel region. A pair of second semiconductor layers and a second half of each pair A pair of gate electrodes disposed on each of the body layers and a drain region of the first conductivity type provided on the other surface of the first semiconductor layer, the first semiconductor layer being a SiC substrate, Each of the pair of channel regions is a first conductivity type SiC film, each of the pair of second semiconductor layers is a second conductivity type SiC film, and in the ON state, a current flows between the channel region, the conductive film, and the conductive film. It has a resistance lower than that of the channel region.

  In the JFET of one aspect of the present invention, a groove is provided on one surface of the first semiconductor layer, and the conductive film is deposited filling the groove.

  In the JFET according to one aspect of the present invention, the channel length of the channel region in the direction from the second semiconductor layer toward the conductive film is the channel region due to the diffusion potential at the junction between the second semiconductor layer and the channel region. It is smaller than the depletion layer width inside.

  In the JFET according to one aspect of the present invention, the conductive film is any one of a metal film and a semiconductor film containing an impurity.

  A JFET according to another aspect of the present invention includes a second conductive semiconductor film formed on a semiconductor substrate, a first conductive semiconductor film including a channel region formed on the second conductive semiconductor film, and A film made of a first conductivity type semiconductor formed on the first conductivity type semiconductor film, the source region and the drain region formed separately on both sides of the channel region, and the second conductivity type semiconductor film And a conductive film disposed in contact with the surface of the channel region.

  With the above structure, the channel region and the conductive film are arranged in parallel to the current flowing through the channel. For this reason, for example, when the electrical resistance of the conductive film is one order lower than that of the channel region, the current flowing through the conductive film in the on state is approximately 10 times higher than that of the channel region. For this reason, even if there are variations in impurity concentration and channel region thickness, the effect on transistor characteristics is negligible, and the effect of variations in these factors is not substantially a problem. On the other hand, in the off state, the negative potential (reverse bias voltage) applied to the gate electrode causes the first conductivity type semiconductor layer including the channel region and the second conductivity type semiconductor layer below the first conductivity type semiconductor layer to A depletion layer extends toward the conductive semiconductor layer. The depletion layer expands more widely on the low concentration side in proportion to the reverse bias voltage and in inverse proportion to the impurity concentration of the first conductive layer and the second conductive layer. When this depletion layer blocks the channel region, the path through which carriers pass through the channel region is blocked. For example, when the conductive film is arranged so that the first conductive semiconductor layers on both sides sandwiching the channel region are not in contact with the side portions, not only the channel region but also the conductive film is blocked by the above-described blocking. The As a result, the off state can be easily realized. Further, even when the conductive film is in contact with only one side of the first conductive type semiconductor layer and not in contact with the other, the off state can be easily realized and the resistance can be lowered. This decrease in resistance reduces the influence of variations in impurity concentration and channel region thickness. When both side portions of the conductive film are in contact with the first conductive type semiconductor layer, the resistance is further lowered, and it is further affected by the variation in the impurity concentration and the variation in the thickness of the channel region. It becomes difficult. The first conductivity type may be n-type or p-type, and the second conductivity type may be p-type or n-type. The semiconductor substrate may be an n-type Si substrate or a p-type Si substrate, and may be an n-type SiC substrate or a p-type SiC substrate.

  In the JFET of the other aspect described above, the length of the conductive film along the channel length direction is shorter than the channel length.

  With this configuration, it is possible to eliminate the difficulty of achieving the off operation when both ends of the conductive film are in contact with the side walls. That is, since at least one end of the conductive film is insulated from the side wall, the conductive film can be turned off by blocking the channel region on the insulated side.

  In the JFET of the other aspect described above, the thickness of the channel region is determined by the diffusion potential at the junction between the second conductive semiconductor film and the first conductive semiconductor film formed on the second conductive semiconductor film. The width is smaller than the depletion layer width in the first conductivity type semiconductor film.

  With the above configuration, when the gate potential is zero, the depletion layer generated by the diffusion potential at the junction between the second conductive semiconductor film and the first conductive semiconductor film blocks the entrance and exit of the channel region. For this reason, a normally-off JFET can be obtained, and can be used for controlling a rotating machine or the like without taking measures against failure of the gate circuit. In addition, power consumption in the on state can be reduced, and influences such as variations in the impurity concentration of the channel region can be avoided.

  The JFET according to still another aspect of the present invention includes a first first-conductivity-type semiconductor layer having an impurity concentration determined by a device breakdown voltage formed on the front surface and a first surface of the front surface. And a conductive film deposited up to a position higher than the surface of the first conductive type semiconductor layer. The JFET also has a region of a second first-conductivity-type semiconductor layer provided on the substrate and on both sides of the conductive film up to a position higher than the surface of the conductive film, and a second first A source region of the first conductivity type semiconductor layer disposed on each of the two regions of the conductivity type semiconductor layer, and a film formed on the substrate and outside each of the second first conductivity type semiconductor layers. A second conductivity type semiconductor layer provided with a gate electrode having a second conductivity type impurity concentration higher than the concentration value of the first conductivity type impurity concentration of the second first conductivity type impurity layer, And a drain region of the first conductivity type semiconductor layer provided on the back surface of the substrate.

  With the above configuration, the electrical resistance of the drift (channel) path that crosses the substrate in the thickness direction from the two source regions provided on the front (front) surface side of the semiconductor substrate to the drain region on the back surface is small. Become. That is, the portion where the conductive film is deposited on the path forms a circuit partially parallel to the path. As described above, even in the case of a JFET in which carriers flow in the thickness direction of the substrate, it is possible to substantially reduce the electrical resistance of the channel region along the same direction. For this reason, it is possible to reduce the power consumed in the channel region as well as the high withstand voltage characteristic peculiar to the vertical JFET, and to solve the heat generation problem. In order to realize an off state by applying a reverse bias voltage to the junction between the second first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer to extend the depletion layer to the second first-conductivity-type semiconductor layer. Therefore, the above relationship needs to be satisfied for the concentration of both layers. However, the impurity concentration of the second first conductivity type semiconductor layer may be higher or lower than the impurity concentration of the first first conductivity type semiconductor layer. The first first conductivity type semiconductor layer having an impurity concentration determined by the element breakdown voltage may be formed on the surface of the substrate, or the substrate itself is the first first conductivity type semiconductor layer. It may be.

  In the JFET according to still another aspect described above, a groove is provided on the front surface of the semiconductor substrate, and the conductive film is deposited by filling the groove.

  With the above configuration, since the conductive film is inserted into the deeper drift (channel) path in the vertical JFET, the current flowing through the drift (channel) is lower, and the current flows more through the conductive film. become. For this reason, the variation between elements due to the impurity concentration of the drift (channel) path or the like becomes smaller.

  In the JFET according to the still another aspect, the low-concentration first conductive semiconductor layer has a cross-sectional length from the second conductive semiconductor film to the conductive film, the second conductive semiconductor film, It is smaller than the depletion layer width in the low-concentration first conductive semiconductor film due to the diffusion potential at the junction with the low-concentration first conductive semiconductor film inside the second conductive semiconductor film.

  With the above configuration, when the gate voltage is zero, the low-concentration first conductive type semiconductor film is blocked by the depletion layer generated at the junction with the second conductive type semiconductor film located outside by the diffusion potential. . Since the conductive film is not in contact with the source region in contact with the low-concentration first conductive type semiconductor film, the path to the conductive film is also blocked by the blocking. As a result, even a vertical JFET with high pressure resistance and low power consumption in the on state can be normally off.

  In the JFETs according to the other aspects and still other aspects, the conductive film is any one of a metal film and a semiconductor film containing a high concentration of impurities.

  With the above configuration, a low-resistance parallel bypass can be easily provided in the channel region using a low-resistance metal film. Any metal film may be used as long as it is an electrode material, but aluminum (Al) or an aluminum alloy is desirable in consideration of ease of etching and high electrical conductivity.

  In the JFET according to the other aspect described above and still another aspect, the semiconductor substrate is a SiC substrate, the first conductivity type semiconductor film is a first conductivity type SiC film, and the second conductivity type semiconductor film is a second conductivity type SiC film. It is.

  SiC has excellent pressure resistance, carrier mobility is as high as Si, and high saturation drift velocity of carriers can be obtained. For this reason, it becomes possible to use said JFET for a high-speed switching element for high power.

FIG. 3 is a cross-sectional view of a JFET according to the first embodiment. It is a schematic diagram explaining an OFF state in JFET of FIG. It is sectional drawing of JFET in Embodiment 2. FIG. FIG. 6 is a cross-sectional view of a JFET according to a third embodiment.

Next, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a cross-sectional view showing a JFET according to the first embodiment. In the figure, a p-type SiC film 2 is formed on an SiC substrate 1, and an n-type SiC film 3 having a reduced channel region 4 is formed thereon. On the n-type SiC film 3 on both sides of the channel region 4, n + -type SiC films 5 and 6 serving as source and drain regions are formed, and source and drain electrodes 11 and 12 are formed on the respective regions. Has been. Further, two gate electrodes 13 are formed on the p-type SiC film and sandwiching the source and drain regions in plan view. The greatest feature of the present embodiment is that an aluminum film 7 is formed on the channel region. The cross-sectional length of the aluminum film is smaller than the channel length L, and the aluminum film is included in the channel region in plan view. That is, the aluminum film 7 is not in contact with the walls on both sides of the channel region 4.

  Next, the operation of this JFET will be described. First, in the on state, carriers flow through the channel region 4 along the substrate surface. At this time, if the aluminum layer 7 is disposed on the channel region, a current flows through a parallel circuit composed of the channel region 4 and the aluminum film 7. When the electric resistance of the aluminum film is lower by, for example, one order than the electric resistance of the channel region, the current flowing through the aluminum film 7 is almost one order higher than the current flowing through the channel region. As a result, the current flowing in the semiconductor can be almost ignored, and the transistor characteristics hardly depend on the impurity concentration of the channel region or the thickness a of the channel region. As a result, it is not necessary to dope high-concentration impurities in order to reduce the electrical resistance of the channel region, and other transistor characteristics without variations can be ensured while maintaining high withstand voltage performance.

  On the other hand, in the off state, a negative potential is applied to the gate electrode 13 shown in FIG. For this reason, a depletion layer 8 is formed at the junction between the p-type SiC film 2 and the n-type SiC film 3, and as the absolute value of the negative potential increases, the impurity concentration is substantially inversely proportional to the lower impurity concentration side. The width of the depletion layer increases. When the tip 8a of the depletion layer width exceeds the thickness a of the channel region 4, the channel region is blocked by the depletion layer, and the passage of carriers is prevented. As described above, since the aluminum film 7 is not in contact with the walls on both sides of the channel region 4, the off state is realized when the tip 8a of the depletion layer width exceeds the channel region thickness a.

(Embodiment 2)
The JFET according to the first embodiment shown in FIGS. 1 and 2 realizes a normally-on state in which a current flows through the channel region 4 when the gate voltage is zero. Normally-on JFETs, when used to control rotating equipment or the like, may not be able to stop rotation if a failure occurs in the gate circuit, so it is necessary to provide a mechanism that copes with the failure of the gate circuit. Since it is troublesome to provide such a mechanism, a normally-off JFET is desirable. In the second embodiment, the normally-off JFET will be described. As shown in FIG. 3, the greatest feature in the present embodiment is as follows. The width of the depletion layer generated by the diffusion potential of the pn ₂ junction, that is, the depletion layer generated when the gate potential is zero is made larger than the thickness a of the channel region. For example, (a) the concentration n _{2 is set} to 1 × 10 ¹⁶ cm ^−3, and (b) the channel region thickness a is set to about 500 nm or less. Beyond that, it can be normally off.

  By adopting the above structure, it is possible to realize a JFET that does not deteriorate the breakdown voltage performance and does not vary in characteristics due to variations in channel concentration or the like, and that is normally off. As a result, it is possible to use a control device such as a large rotating device without providing a gate circuit failure countermeasure mechanism.

(Embodiment 3)
FIG. 4 is a cross-sectional view showing a JFET according to the third embodiment. In the figure, the n-type SiC substrate has an n-type impurity concentration determined by the device breakdown voltage, and also serves as a first first conductivity type (n-type) semiconductor layer. An aluminum film 7 is formed to a predetermined height by filling a groove on the front surface of the n-type SiC substrate 9. On both sides of the aluminum film 7, n-type SiC films for forming the channel regions 4a and 4b are formed. The height of the channel regions 4a and 4b is set slightly higher than the height of the aluminum film 7. In contact with the two channel regions 4a and 4b, p-type SiC films 2a and 2b are formed on the outside, and a gate electrode 13 is disposed thereon. Source regions 5a and 5b are formed on the two channel regions 4a and 4b, respectively, and source electrodes 11a and 11b are disposed thereon. Further, an n + -type SiC film is formed on the back surface of the n-type SiC substrate 9, and the drain electrode 12 is disposed thereon. Needless to say, ohmic contact is formed between each electrode and the semiconductor layer.

  In the ON state, carriers flow from the source regions 5a and 5b to the drain region 6 across the substrate in the thickness direction. That is, a normally-on JFET is realized. At this time, the current is shunted to the path between the aluminum film 7 and the channel region and the n-type SiC substrate. However, since the electrical resistance of the aluminum film is very low, the current flows mainly on the aluminum film side. For this reason, the variation between elements can be greatly reduced without being affected by the impurity concentration and dimensional variation in the channel region.

  In the off state, a negative voltage (−15 to −25 V) having a large absolute value is applied to the gate. For this reason, a reverse bias voltage is applied to the junction between the channel regions 4a and 4b and the p-type region outside thereof. The For this reason, the width of the depletion layer broadens mainly on the side with a low impurity concentration. When this depletion layer reaches the entire channel region, the path from the source region to the drain region 6 through the substrate 9 is blocked. Since the aluminum film 7 has a height lower than that of the channel regions 4a and 4b, the path through the aluminum film is also blocked, and an off state is realized.

  Since the vertical JFET shown in FIG. 4 has a high withstand voltage, the use of the JFET of the present embodiment makes it possible to provide an element for high-voltage power with little characteristic variation between elements.

  In FIG. 4, the channel region is cut off at the gate voltage of zero to realize the off state by making the cross-sectional length l of the channel region shorter than the depletion layer width due to the diffusion potential of the pn− junction. That is, a normally-off JFET can be obtained.

The JFET shown in Embodiment 1 of FIG. 1 was prototyped and the channel resistance when 1 V was applied was measured. The JFET was a 100V withstand voltage element. The n-type SiC films 3 and 4 including the channel region have an impurity concentration of 4.0 × 10 ¹⁷ cm ⁻³ , a channel length L of 1000 nm (10 μm), and a channel region thickness a of 230 nm.

According to the results shown in Table 1, the channel resistance of the conventional JFET having no metal film in the channel region (JFET obtained by removing the aluminum film from the JFET in FIG. 1) was 7.8 mΩcm ² . On the other hand, the channel resistance of the JFET of the first embodiment provided with the aluminum film (example of the present invention) was greatly reduced to 1.6 mΩcm ² . Therefore, it was found that the channel resistance is greatly reduced by the example of the present invention. Therefore, it was possible to obtain a JFET with little variation between elements without being affected by variations in the impurity concentration of the channel region and the thickness of the channel region.

  While the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

  1 SiC substrate, 2, 2a, 2b p-type SiC film, 3 n-type SiC film, 4, 4a, 4b channel region, 5, 5a, 5b source region, 6 drain region, 7 aluminum film, 8 depletion layer, 8a depletion Layer tip, 9 n-type SiC substrate, 11, 11a, 11b Source electrode, 12 Drain electrode, 13 Gate electrode, L channel length, a channel region thickness, l channel region cross-sectional length.

Claims (4)

A first semiconductor layer of a first conductivity type having one surface and the other surface facing each other and having an impurity concentration determined by an element breakdown voltage;
A conductive film formed on the one surface of the first semiconductor layer;
A pair of first conductivity type formed on the one surface of the first semiconductor layer so as to be in contact with the conductive film on both sides of the conductive film and to a position higher than the surface of the conductive film. A channel region;
A pair of source regions of a first conductivity type, each disposed over each of the pair of channel regions;
Each is disposed on the one surface of the first semiconductor layer on the side opposite to the conductive film side of the pair of channel regions, and from the concentration value of the first conductivity type impurity in the channel region A pair of second semiconductor layers of the second conductivity type having a concentration of the second conductivity type impurity having a higher value;
A pair of gate electrodes, each disposed on each of the pair of second semiconductor layers;
A drain region of a first conductivity type provided on the other surface of the first semiconductor layer,
The first semiconductor layer is a SiC substrate, each of the pair of channel regions is a first conductivity type SiC film, and each of the pair of second semiconductor layers is a second conductivity type SiC film;
The junction field effect transistor, wherein the conductive film is configured so that a current flows separately between the channel region and the conductive film in an ON state, and has a lower resistance than the channel region.   The junction field effect transistor according to claim 1, wherein a groove is provided on the one surface of the first semiconductor layer, and the conductive film is deposited to fill the groove.   The depletion in the channel region due to the diffusion potential at the junction between the second semiconductor layer and the channel region is a cross-sectional length that is the length of the channel region in the direction from the second semiconductor layer toward the conductive film. The junction field effect transistor according to claim 1, wherein the junction field effect transistor is smaller than the layer width.   The junction field effect transistor according to claim 1, wherein the conductive film is one of a metal film and a semiconductor film containing impurities.

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