JPS61174718A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61174718A
JPS61174718A JP1586285A JP1586285A JPS61174718A JP S61174718 A JPS61174718 A JP S61174718A JP 1586285 A JP1586285 A JP 1586285A JP 1586285 A JP1586285 A JP 1586285A JP S61174718 A JPS61174718 A JP S61174718A
Authority
JP
Japan
Prior art keywords
layer
photo resist
semiconductor substrate
photoresist
ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1586285A
Other languages
Japanese (ja)
Inventor
Atsushi Sakamoto
淳 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1586285A priority Critical patent/JPS61174718A/en
Publication of JPS61174718A publication Critical patent/JPS61174718A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Abstract

PURPOSE:To reduce a number of manufacturing steps and manufacturing cost by executing the photorithography using the positives photo resist coated at first to the surface of semiconductor substrate also for the second and successive steps in the photorethography process to be continued twice or more. CONSTITUTION:The surface of semiconductor substrate 1 is coated with a positive photo resist 2 and it is then pre-baked. A photo resist pattern layer 5 is selectively formed by the mask alignment, exposure, developing process and first ion implantation is carried out. The part not exposed of the layer 5 is selectively exposed and developed by the mask alignment process in order to form another photo resist pattern layer 9. The second ion implantation is carried out thereto. Thereby, ion is implanted also to the window part of layer 5. In the same way, the photo resist 2 can be used in three times or more.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に関し、特にフォトリ
ソグラフィー工程の改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a photolithography process.

〔従来の技術〕[Conventional technology]

従来の半導体装置の製造方法において、2回以上連続す
るフオ) IJソグラフイ一工程を行なう場合、例えば
、半導体基板表面に形成されたトランジスタノしきい値
電圧音制御す小鳥にチャンネル部にイオン注入するチャ
ンネルドープ工程と、さらに、前記トランジスタよりし
きい値電圧乞下げたいトランジスタのチャンネル部にイ
オン注入するダブルチャンネルドープ工程の様に、連続
して、同一トランジスタのチャンネル部にイオン注入す
る為の、フォトレジストパターンZ形成する場合、一般
的には、第2 flN (at〜(jlの様な工程乞通
して行なわれていた。
In the conventional manufacturing method of semiconductor devices, when one step of IJ lithography is performed two or more consecutive times, for example, ions are implanted into the channel part of a transistor formed on the surface of the semiconductor substrate. In the channel doping process, and also in the double channel doping process in which ions are implanted into the channel part of a transistor whose threshold voltage is to be lowered than that of the previous transistor, a photo-optical process is performed to continuously implant ions into the channel part of the same transistor. When forming the resist pattern Z, a process such as the second flN(at~(jl) is generally performed.

まず、半導体基板表面1上に、ネガ型フォトレジスト2
ン塗布、プレベークする。(第2 内a )次にマスク
アライメント工程(第2図b)によって、選択的にフォ
トレジストパターン層5y!/形成(第21Nc)L、
そのパターン層をマスクとして、半導体基板表面にホロ
ンイオン、リンイオン等のイオン6を照射し、イオン注
入層7Z形成していた。(@2図d) ところが、2回以上連続したフォトレジストパターン層
χ形成する為には、上記フォトレミスト層Y剥離しく第
2図e)、再度半導体基板表面上に、ネガ型フォトレジ
スト8乞塗布、プレベーク(第2図r)し、再度マスク
アライメント、露光工程(第2図g)をへて、必要なフ
ォトレジストパターンniqw、形成していた。(第2
囚h)その後、2回目のイオン注入が行なわれ(第2図
1)、上記フォトレジストパターンIi#9奮剥離する
ことで、表面濃度の異なるイオン注入層7.10ン選択
的に得ていた。(第2図j)〔発明7>X解決しようと
する問題点〕しかし、上記の従来の製造方法では、2回
以上連続するフォトリソグラフィー工程において、連続
する回数だけのフォトレジスト塗布、ズレベーク、フォ
トレジスト剥離を行なう必要があり、工程χ複雑かつ、
作業性を低下させるという問題点があった。
First, a negative photoresist 2 is placed on the semiconductor substrate surface 1.
Coat and pre-bake. (Second Inner A) Next, by a mask alignment process (FIG. 2b), the photoresist pattern layer 5y! / Formation (21st Nc) L,
Using the patterned layer as a mask, the surface of the semiconductor substrate was irradiated with ions 6 such as holon ions and phosphorus ions to form an ion-implanted layer 7Z. (@Fig. 2 d) However, in order to form two or more consecutive photoresist pattern layers χ, the photoresist layer Y must be peeled off (Fig. 2 e), and a negative photoresist layer 8 must be applied again on the semiconductor substrate surface. After coating and pre-baking (FIG. 2r), mask alignment and exposure steps (FIG. 2g) were performed again to form the necessary photoresist pattern niqw. (Second
h) After that, a second ion implantation was performed (Fig. 2 1), and by peeling off the photoresist pattern Ii#9, an ion implanted layer 7.10 with different surface concentrations was selectively obtained. . (Fig. 2 j) [Invention 7>Problem to be solved by It is necessary to remove the resist, and the process is complicated and
There was a problem that work efficiency was reduced.

本発明は、この様な問題点ン解決するもので1工程数の
低減、ひいては製造コストヲ低下させることχ目的とす
る。
The present invention solves these problems and aims to reduce the number of steps per process and, in turn, reduce manufacturing costs.

〔問題点Z解決する為の手段〕[Means to solve problem Z]

不発明の半導体装量製造方法は、2回以上連続するフォ
トリソグラフィー工程において、半導体基板表面に最初
に塗布したポジ型フオ)l/ジストン、2回目以降にも
使用して、フォトリングラツイーン行なうこと’2%徴
とする。
The uninvented method for manufacturing semiconductor components is to carry out photolithography in two or more consecutive photolithography steps by using the positive type phosphatide initially applied to the surface of the semiconductor substrate, and using it from the second time onwards. This is assumed to be 2%.

〔作用〕[Effect]

本発明の作用χ述べれば、ポジ型フォトレジスト層は、
露光によって感光された部分は、元光学反応によって構
造変化ン起こし、現像液に選択的に溶解されるが、感光
されていない部分は、再度の露光プロセスに使用し、フ
ォトレジストのバターニングが可能である。
Effects of the present invention χ In other words, the positive photoresist layer is
The areas exposed to light undergo a structural change due to an original optical reaction and are selectively dissolved in a developer, but the areas that are not exposed to light can be used for a second exposure process to pattern the photoresist. It is.

〔実施例〕〔Example〕

以下、本発明について、実施例に基づき詳細に説明する
Hereinafter, the present invention will be described in detail based on examples.

第1図g −hは、本発明の実施例〉工程順に示す図で
ある。まず、半導体基板表面1上に、ポジ型フォトレジ
スト2Y塗布、プレベークする。
FIGS. 1g to 1h are diagrams showing the steps of an embodiment of the present invention. First, a positive photoresist 2Y is applied onto the semiconductor substrate surface 1 and prebaked.

(第1図g) 次に、マスクアライ、メント、露光、現像工程(第1囚
h)によって、選択的にフォトレジストパターン層5ン
形成(第1図g)する。ただし、この場合、2亘目のイ
オン注入のマスクとして使用スるフォトレジストパター
ンのみ形成する必要がある。その後、上記フォトレジス
トパターン層ンマスクにして、1回目のイオン圧入2行
なう。
(FIG. 1g) Next, 5 photoresist pattern layers are selectively formed (FIG. 1g) by mask alignment, exposure, and development steps (first step h). However, in this case, it is necessary to form only a photoresist pattern to be used as a mask for the second ion implantation. Thereafter, using the photoresist pattern layer as a mask, two first ion press injections are performed.

(第1図d) 次に、上記フォトレジストパターン層の感光していない
部分に、マスクアライメント工程(第1図θ)によって
、選択的に露光、現像処理乞行ない、別のフォトレジス
トパターン層9′?:形成する。
(FIG. 1 d) Next, the unexposed portions of the photoresist pattern layer are selectively exposed and developed by a mask alignment process (θ in FIG. 1), forming another photoresist pattern layer 9. ′? :Form.

(第1図で) 次に、2回目のイオン注入2行なうことで、先に形成し
ていたフォトレジストパターン層の窓開き部分にも注入
がなされる。(第1図g)その後、既フォトレジストパ
ターン層ケ剥離することで、表面濃度の異なるイオン注
入層7.10が得られた。(第1囚h) ここでは、2回連続して行なうフォトリソグラフィー工
程の実施例χ示したが、3回連続してフォトリソグラフ
ィー工程を行かい、3つの男面燭度の異なるイオン注入
層を形成する場合も同様で3回連続して必要とするフォ
トレジストパターン層から順に形成すること圧よって、
半導体基板表面に、最初に塗布したポジ型フォトレジス
トχ有効に活用できる。この様に連続するフォトリソグ
ラフィー工程が多い程、繰り返し行なうフォトレジスト
塗布、プレベータ、フォトレジスト剥離工程が省略でき
る。
(See FIG. 1) Next, by performing two second ion implantations, implantation is also performed in the window opening portion of the photoresist pattern layer that was previously formed. (FIG. 1g) Thereafter, by peeling off the photoresist pattern layer, an ion-implanted layer 7.10 having a different surface concentration was obtained. (First prisoner h) Here, an example χ of a photolithography process performed twice consecutively is shown, but the photolithography process is performed three times consecutively to form three ion-implanted layers with different degrees of irradiation. The same goes for forming the required photoresist pattern layer three times in a row.
The positive photoresist χ initially applied to the surface of the semiconductor substrate can be effectively utilized. The more continuous photolithography steps are performed in this way, the more the repeated photoresist coating, pre-evaporation, and photoresist peeling steps can be omitted.

〔本発明の効果〕[Effects of the present invention]

以上の様に、本発明の製造方法によれば、2回以上連続
するフォトリソグラフィー工程において繰り返し行なわ
れるフォトレジスト塗布、ズレベーク、フォトレジスト
剥離工程ン省略することができた。すなわち製造工数の
減少、フォトレジスト、現像数代の減少による半導体装
置のコストの低減、並びにフォトレジスト塗布時に伴な
うゴミ付着による歩留りの低下Z必要最小限におさえる
ことができた。
As described above, according to the manufacturing method of the present invention, the photoresist coating, shift baking, and photoresist peeling steps that are repeatedly performed in two or more consecutive photolithography steps can be omitted. That is, the cost of the semiconductor device can be reduced by reducing the number of manufacturing steps, the number of photoresist and development steps, and the reduction in yield due to dust adhesion during photoresist application can be suppressed to the necessary minimum.

又、繰り返し形成されていくフォトレジストパターンj
#が、屓次後に残っていく為、パターンの認識ができ、
マスクアライメントパターンに使用したり、マスクアラ
イメント工程の抜1tY未然に防止することができた。
In addition, the photoresist pattern j that is repeatedly formed
Because # remains after the test, patterns can be recognized.
It can be used for mask alignment patterns and can prevent omissions in the mask alignment process.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(at〜(hll全発明実施例図である。 第2図(al〜(jlは、従来の実施例図である。 1・・・・・・半導体基板 2・・・・・・ネガ型フォトレジスト 3・・・・・・ガラスマスク 4・・・・・・光 5・・・・・・ネガ型フォトレジストパターン6・・・
・・・イオンビーム 7・・・・・・イオン注入層 8・・・・・・ネガ型フォトレジスト 9・・・・・・ネガ型フォトレジストパターン10・・
・・・・イオン注入層 第1図は、本発明による実施例内である。 1・・・・・・半導体基板 2・・・・・・ポジ型フォトレジスト 5・・・・・・ポジ型フォトレジストパターン7・・・
・・・イオン注入層 9・・・・・・ポジ型フォトレジストパターン10・・
・・・・イオン注入層。 以上
FIG. 1 (at~(hl) is a diagram of all embodiments of the invention. FIG. 2 (al~(jl is a diagram of a conventional embodiment). 1...Semiconductor substrate 2... Negative photoresist 3...Glass mask 4...Light 5...Negative photoresist pattern 6...
... Ion beam 7 ... Ion implantation layer 8 ... Negative photoresist 9 ... Negative photoresist pattern 10 ...
. . . Ion-implanted layer FIG. 1 is in an embodiment according to the present invention. 1...Semiconductor substrate 2...Positive photoresist 5...Positive photoresist pattern 7...
...Ion implantation layer 9...Positive photoresist pattern 10...
...Ion implantation layer. that's all

Claims (1)

【特許請求の範囲】[Claims] 半導体装置の製造に関して、2回以上連続するフォトリ
ソグラフィー工程において、半導体基板表面に最初に塗
布したポジ型フォトレジストを、2回目以降にも使用し
て、フォトリソグラフィーを行なうことを特徴とする半
導体装置の製造方法
A semiconductor device characterized in that, in two or more consecutive photolithography steps, a positive photoresist coated on the surface of a semiconductor substrate is used for the second and subsequent photolithography steps in manufacturing the semiconductor device. manufacturing method
JP1586285A 1985-01-30 1985-01-30 Manufacture of semiconductor device Pending JPS61174718A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1586285A JPS61174718A (en) 1985-01-30 1985-01-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1586285A JPS61174718A (en) 1985-01-30 1985-01-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61174718A true JPS61174718A (en) 1986-08-06

Family

ID=11900607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1586285A Pending JPS61174718A (en) 1985-01-30 1985-01-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61174718A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303504A (en) * 2005-03-23 2006-11-02 Asml Netherlands Bv Process of processing reduced pitch multiple exposures
US7781149B2 (en) 2005-03-23 2010-08-24 Asml Netherlands B.V. Reduced pitch multiple exposure process
US7906270B2 (en) 2005-03-23 2011-03-15 Asml Netherlands B.V. Reduced pitch multiple exposure process

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303504A (en) * 2005-03-23 2006-11-02 Asml Netherlands Bv Process of processing reduced pitch multiple exposures
US7781149B2 (en) 2005-03-23 2010-08-24 Asml Netherlands B.V. Reduced pitch multiple exposure process
JP4630839B2 (en) * 2005-03-23 2011-02-09 エーエスエムエル ネザーランズ ビー.ブイ. Reduced pitch multiple exposure method
US7906270B2 (en) 2005-03-23 2011-03-15 Asml Netherlands B.V. Reduced pitch multiple exposure process
US7981595B2 (en) 2005-03-23 2011-07-19 Asml Netherlands B.V. Reduced pitch multiple exposure process

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