JPS61174236U - - Google Patents
Info
- Publication number
- JPS61174236U JPS61174236U JP5865585U JP5865585U JPS61174236U JP S61174236 U JPS61174236 U JP S61174236U JP 5865585 U JP5865585 U JP 5865585U JP 5865585 U JP5865585 U JP 5865585U JP S61174236 U JPS61174236 U JP S61174236U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- converter
- diffusion region
- insulating layer
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案による一実施例の半導体基板断
面図、第２図は同平面図、第３図は同実施例の要
部等価回路図、第４図は従来の並列形Ａ―Ｄコン
バータの回路図、第５図は従来の並列形Ａ―Ｄコ
ンバータの等価回路図である。
３……ポリシリコン抵抗体、４……拡散領域、
２，５……絶縁層、６……金属電極。
Fig. 1 is a sectional view of a semiconductor substrate of an embodiment of the present invention, Fig. 2 is a plan view of the same, Fig. 3 is an equivalent circuit diagram of the main part of the embodiment, and Fig. 4 is a conventional parallel type AD converter. FIG. 5 is an equivalent circuit diagram of a conventional parallel type AD converter. 3... Polysilicon resistor, 4... Diffusion region,
2, 5...Insulating layer, 6...Metal electrode.
Claims (1)
置からタツプを引き出して複数の基準電圧を形成
し、各基準電圧と入力電圧を比較して出力信号を
形成する並列形Ａ―Ｄコンバータにおいて、 半導体基板上に絶縁層を介して形成された抵抗
体と、 該抵抗体と対向する基板面に形成された拡散領
域とを備えてなり、 上記拡散領域を接地電位に接続して上記抵抗体
とで容量を形成してなることを特徴とするＡ―Ｄ
コンバータ。 (2) 抵抗体の拡散領域と相対する側に、絶縁層
を介して電極を形成し、該電極をも接地電位に接
続してなることを特徴とする請求の範囲第１項記
載のＡ―Ｄコンバータ。[Claims for Utility Model Registration] (1) A plurality of reference voltages are formed by pulling out taps from different positions of a resistor string connected between predetermined voltages, and an output signal is formed by comparing each reference voltage with the input voltage. A parallel A-D converter comprising: a resistor formed on a semiconductor substrate via an insulating layer; and a diffusion region formed on a surface of the substrate facing the resistor, the diffusion region being grounded. A-D, characterized in that it is connected to a potential and forms a capacitance with the above-mentioned resistor.
converter. (2) A according to claim 1, characterized in that an electrode is formed on the side of the resistor facing the diffusion region via an insulating layer, and the electrode is also connected to a ground potential. D converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5865585U JPS61174236U (en) | 1985-04-18 | 1985-04-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5865585U JPS61174236U (en) | 1985-04-18 | 1985-04-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61174236U true JPS61174236U (en) | 1986-10-30 |
Family
ID=30584364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5865585U Pending JPS61174236U (en) | 1985-04-18 | 1985-04-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61174236U (en) |
-
1985
- 1985-04-18 JP JP5865585U patent/JPS61174236U/ja active Pending
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