JPS61168175A - Disk controller - Google Patents

Abstract

PURPOSE:To detect an address mark without using any timer by delaying a detection signal as to the end of a synchronizing area through a shift register and determining the timing of address mark detection. CONSTITUTION:A signal 11 read out of a disk is inputted to a 16-bit shift register (SR)1 with a clock signal 12 and the output data signal 13 obtained by delaying the signal 11 by 16 clock pulses is inputted to a 16-bit SR2. A 32-bit comparator 3 compares the contents of the SR1 with the synchronizing area data pattern of the output 15 of the SR2 and sends a synchronizing area end signal 16 to a 15-bit SR4 on transition from coincidence to dissidence; and the comparison permit signal 17 obtained by delaying the signal by 15 clock pulses is sent from an SR4 to a 16-bit comparator 5, which compares the contents of the SR1 with the data pattern of a specific address mark, so that the address mark detection signal DET18 is outputted when the comparison result indicates coincidence.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a disk control device that inputs a data signal read from a disk and detects its address mark.

(Prior Art) First, address mark detection in a disk control device will be described.

A first comparator compares the data read from the disk and a second comparator compares the data read from the disk with the data pattern of the address mark.
It was equipped with a comparator and a timer.

First, the data read from the disk is synchronized (S
YN C) The first comparison operation with the data pattern of the area
As soon as the comparison results match, the timer is enabled, and at the same time, the second comparator starts comparing the data read from the disk with the data pattern of the address mark.

When the count value of this timer is below a certain value and an address mark data pattern is detected on the data read from the disk, the address mark detection signal is activated and the timer count value is detected before the address mark data pattern is detected. If exceeds a certain value, the timer counter is reset and the data pattern detection operation for the 8YNC area is performed again. Thereafter, address mark detection was executed by repeating similar operations.

Therefore, in this conventional circuit, it is necessary to have a timer to perform the address mark detection operation, and the amount of hardware is quite large.The upper limit of the count of the timer is determined by the length of the 5YNC area on the disk and Since it depends on the speed at which data is read, it has the disadvantage that it cannot be fixed.

(Object of the Invention) An object of the present invention is to provide a disk control device that can eliminate the above drawbacks and realize address mark detection without using a timer.

(Configuration of the Invention) The configuration of the present invention is that, in a disk control device that inputs a data signal read from a disk and a clock signal for reading this data signal, a first shift register that inputs the data signal; A first shift register that compares the contents of this first shift register with a data pattern in a predetermined synchronization area and detects a transition from a match to a mismatch in the comparison result.
a comparator, and a second shift register which inputs a signal indicating the detection result of the first comparator and outputs the signal after being delayed by a certain number of pulses of the clock signal, the contents of which are the same as those of the first shift register. a second comparator for comparing the data pattern of a predetermined address mark; the comparison result of the second comparator is referred to and output at a timing determined by the output signal of the second shift register; It is characterized in that it is determined whether the contents of the address mark match the data pattern of the address mark.

(Example) Next, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram showing the system configuration of an embodiment of the present invention. In this embodiment, the 5YNC area consists of a data pattern area of 4 bytes or more of AAH (A is "10'1OJ"), and the address mark is 2 bytes of 44
It is assumed that the data pattern is composed of H89H data pattern. In the figure,
1 and 2 are 16-pit shift registers, and their contents are shifted by 1 bit every clock. 3 is a 32-bit comparator that compares the input data with the 4-byte AAH every 1 clock, and once the comparison results match, thereafter compares the input data with the 4-byte AAH every 2 clocks. 4 is 1
Its contents are shifted one bit every clock. 15-bit shift register, 5 compares input data with 44H89H. It is a 16-bit comparator. Further, numeral 11 is read from the disk and consists of data pulses and clock pulses. MFM data input signal, 12 is signal 1
1 is a clock input signal for reading 1, 13 is an output data signal of shift register 1 and is a delayed signal obtained by delaying signal 11 by 16 clocks, and 14 and 15 output the contents of shift registers 1 and 2, respectively. 16-bit wide data bus, 1
Reference numeral 6 is an output of the comparator 3, which is a synchronization region end detection signal NAAH, which outputs a pulse with a clock width of 1.0 clock immediately after the comparison result of the comparator 3 changes from match to non-match. Reference numeral 17 is an output signal of the shift register 5, which is a signal obtained by delaying the signal 16 by 15 clocks, and is a comparison operation permission signal STR of the comparator 5. Reference numeral 18 denotes an address mark detection signal DET which becomes active when the comparison result of the comparator 5 matches.

Next, the operation of this embodiment will be explained.

FIG. 2 is an example of a time chart of signals 11, 12, and 16 in FIG. 1, including clock input signal 12 (CLK), input signal 11 (SR1) of shift register 1,
The numbers shown below the waveforms indicate the bit-by-bit data of the shift register. As shown in this figure, the comparator 3 is the MFM (Modif) read from the disk.
ied FM) The 1104-byte data input signal is ticked every clock, and it is detected whether all 4 bytes are the AAH data pattern. Once a 4-byte continuous AAH data pattern is detected, 2
A comparison operation is performed every clock.

In other words, when detecting a transition from a state in which all four bytes of the contents of shift register 1 are AAH data patterns to a state in which one byte out of the four bytes is not an AAH data pattern, comparator 3 Output pulse 16.

FIG. 3 is a time chart when the MFM data input signal 11 read from the disk includes a data pattern of AAHAAHAAHAAH44H89H. s in the figure
#x 3 is the input signal of the shift register unit, 5TR17
indicates a comparison operation permission signal of the comparator 5, and DET18 indicates an address mark detection signal.

Furthermore, A is an area where the contents of shift register 1 are the data pattern of the 8YNC area, B is an area where the contents of shift register 1 are the data pattern of address mark 44H89H, and C is an area where the contents of shift register 1 are the data after the address mark. As shown in the figure, the pulse output signal 16 is transferred to 15 by the shift register 5.
The signal is delayed by the clock and input to the comparator 5 as a comparison operation permission signal. At this time, the contents of shift register 1 are 44H.
89H, the comparison result of the comparator 5 matches, and the address mark detection signal 18 becomes active.

If the MFM input signal 11 read from the disk does not contain an AAH data pattern of 4 bytes or more, the comparator 3
The address mark detection signal 18 will not become active unless the comparator 5 outputs a pulse signal and the comparison operation of the comparator 5 is performed.

Still, as MFM input signal 11, A A of 4 bytes or more
If a data pattern other than 44H89H is input immediately after the H data pattern, the comparison operation permission signal 17 of the comparator 5 becomes active, but the address mark detection signal 18 never becomes active.

As described above, according to this embodiment, the address mark detection operation can be performed without using a timer.
Furthermore, the timing for detecting the address mark located immediately after the 8YNC area can be determined without depending on the length of the 5YNC area on the disk.

In this embodiment, a 16-bit shift register, a 15-bit shift register, and an input data pattern A are used.
AHA AHA AHA AH Compare with H support 32
Bit comparator, input data to data no turn 44H8
9H and a 16-bit wide data bus, these configurations include the data pattern of the 5YNC area, the number of bits required to detect the 5YNC area, the address mark notator pattern, and the bits of the address mark. It is possible to set it appropriately depending on the number.

(Effects of the Invention) As explained above, in the disk control device of the present invention, a timer is used to determine the address mark detection timing by delaying the signal that detects the end of the 5YNC area using a shift register. Address mark detection timing can be managed without any problem. For example, compared to the 15-pit shift register (4) of this embodiment, the conventional
Since a 12-bit timer is required, the present invention requires less hardware than the prior art. Further, the address mark can be detected without depending on the length of the 5YNC area on the disk or the speed at which data on the disk is read. Furthermore, since the address mark detection operation can be performed only on the data immediately after the data pattern in the 5YNC example area, the probability of erroneously detecting data other than the address mark as an address mark is reduced compared to conventional circuits. I can do it.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the system configuration of an embodiment of the present invention, and FIGS. 2 and 3 are time charts showing the operation of FIG. 1. In the figure 1. Za4=10-...Shift register, 45...Comparator, 11...Data input signal, 12...
Clock input signal, 13...1-bit width data bus, 14.15...16-bit width data bus, 16...5YNC area end detection signal, 17.
...Comparison operation permission signal of comparator 6, 18...
...Address mark detection signal.

Claims (1)

[Claims] A disk control device that inputs a data signal read from a disk and a clock signal for reading this data signal, a first shift register that inputs the data signal, and a predetermined synchronization area with the contents of the first shift register. a first comparator that compares the data pattern with the data pattern and detects a transition from match to mismatch in the comparison result; a second shift register that outputs the output with a delay of 10 minutes, and a second comparator that compares the contents of the first shift register with a data pattern of a predetermined address mark, the comparison result of the second comparator A disk control device characterized in that the data signal is referred to and outputted at a timing determined by an output signal of the second shift register, and it is determined whether the contents of the data signal match the data pattern of the address mark.