JPS61201516A - Pattern detection circuit - Google Patents

Abstract

PURPOSE:To obtain a small sized pattern detecting circuit with very simple control by inputting an input signal, its clock information and number of coincidence or dissidence of patterns so far as memory address signals for pattern detection of a digital signal. CONSTITUTION:Let a compared pattern be '1101(2)', when an input signal 1 is '0000(2)', '1 or 3' is outputted as a count data 5. A count data 6 is latched at the trailing of a clock signal 2 the same as the clock data 6 and becomes an address signal 11. When the 1st input signal 1 is inputted, a signal representing 'number of coincidence or dissidence between the 1st input signal 1 and the 1st comparison pattern + number of coincidence or dissidence between the 0-th input signal 1 and the 0-th comparison pattern' is outputted as the count data 5. When the input signals 1 up to the i-th order are inputted similar ly, a signal representing 'number of coincidence or dissidence between the i-th input input signal 1 and the i-th comparison pattern +......+ 0-th number of coincidence or dissidence between the 0-th input signal 1 and the 0-th compari son pattern' is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a pattern detection circuit that detects a correlation between a digital input signal and an arbitrary comparison pattern to determine the number of matches or mismatches.

<Prior art> Conventionally, this type of pattern detection circuit has basically consisted of a comparison circuit that compares an input signal with a comparison pattern, and a counting circuit that sequentially counts the number of matches or mismatches output from the comparison circuit. It was configured as.

<Problem to be solved> However, the comparator circuit compares the input signal of the lth clock with the comparison pattern of the first clock, and compares the input signal of the second clock with the comparison pattern of the second clock. A control circuit is required to move the comparison pattern in synchronization with the signal, and if a counter is used as a counting circuit, a control circuit is required to advance the lanter by the number of matches or mismatches output from the comparison circuit. Naru etc.
There was a problem that the circuit scale became large.

The present invention solves the above problems and provides a pattern detection circuit that is easy to control and can be configured on a small scale.

Means for Solving the Problems> In order to solve the above problems, the configuration of the pattern detection circuit according to the present invention is a pattern detection circuit that detects the number of matches or mismatches between a digital input signal and an arbitrary comparison pattern by correlation. By inputting the output of the memory, which is the number of matches or mismatches between the input signal and its clock information and the comparison pattern, as the address signal of the memory, the input signal and the comparison pattern can be compared and the match or mismatch of the comparison results can be determined. The memory is used to count numbers, and stores the number of matches or mismatches between all possible patterns of clock input signals up to 0, 1, 2...1 and the comparison pattern. The clock information and the input signal, which clock input signal is inputted, and the memory output which is the number of matches or mismatches between the previous clock input signal and the comparison pattern are used as the memory address signal. It has the function of comparing the input signal with the comparison pattern and counting the number of matches or mismatches of the comparison results in memory, and the control is performed only by a clock signal synchronized with the input signal. It is.

<Example> Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a pattern detection circuit according to the present invention.

FIG. 2 is a timing chart showing each signal waveform in the same embodiment.

In FIG. 1, 7.8 is a launch circuit, and 9 is a memory. Input signal 1, count data 5, and clock data 6 are arbitrary pit barrel two-barrel signals. Input signal 1 becomes address signal 10 via launch circuit 7 and is input to memory 9.

The output data of the memory 9 includes judgment data 4 and counting data 5.
Count data 5 and clock data 6 are passed through a latch circuit 8 to become an address signal ti, 12, which is input to a memory 9. In this way, the address of memory 9 is the address signal 1.
It is composed of three values: 0, 11, and 12. The memory 9 contains the following clock data 6 and count data 5.
, determination data 4 are stored.

Clock data at address i = value of address signal 12 at address i + 11 count data at address i = number of matches or mismatches between the value of address signal 10 at address i and the j-th comparison pattern + address signal at address i 11 value, (where j = value of the address signal of address i) If the address is larger than the judgment data of address i = the count data of address i is the set threshold, input logic "H" (or "L") The timings of signal 1, clock signal 2 and frame signal 3 are shown in FIG. The latch circuit 8 is reset by the frame signal 3,
Address signal ii, 12 is initialized to rOJ. First (0th) This becomes the address signal of the memory 9 when input. When the first input signal l is input, the clock data 6 becomes "1+1=2
J is output, and the address signal 12 becomes "2" at the falling edge υ of the clock signal 2. In this way, the address signal 12 is
It shows clock information indicating which clock signal the input signal l corresponds to. When the 0th input signal 1 is input, the count data 5 becomes "0" stored in the memory 9.
The number of matches or mismatches between the 1st input signal 1 (=the value of the address signal 10) and the 0th comparison pattern+0 is output. As a specific example, the comparison pattern is “1101 (21
j, then when the input signal 1 is r 0000 (21J), the count data 5 is output as "1 or 3".The count data 6, like the clock data 6, corresponds to the falling edge of the clock signal 2. is doubled and becomes the address signal 11. When the first input signal l is input, the count data 5 is "the match or mismatch between the first input signal l and the first comparison pattern". "The number of matches or mismatches between input signal 1 and the 0th comparison pattern" is output.Similarly, when input signals 1 to 1 are input, "the number of matches or mismatches between input signal 1 and 0th comparison pattern" is output.
The number of matches or mismatches with the 10th comparison pattern . . . the number of matches or mismatches between the 10th input signal l and the 0th comparison pattern is output.

In this way, when an input signal l synchronized with a clock is input, an address signal 11 is generated which indicates the number of matches or mismatches with the comparison pattern of the same length as the input signal, and the magnitude relationship between the number of matches or mismatches and the threshold value. A determination signal L3 is obtained.

<Effects of the Invention> As explained above, according to the pattern detection circuit according to the present invention, in order to detect a pattern of a digital signal, the input signal, its clock information, and the number of coincidences or mismatches of patterns up to that point are stored in memory addresses. By inputting it as a signal, it is possible to compare the input signal with a comparison pattern and count the number of matches or mismatches in the comparison results using memory, which is very easy to control and is a small-scale pattern detection circuit. This has the effect that the following can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a pattern detection circuit according to the present invention. FIG. 2 is a time chart showing the waveforms of each signal in the same embodiment. 1... Input signal 2... Clock information 3...
・Frame signal 4... Judgment data 5... Counting data 6... Clock data 7, 8... Latch circuit 9... Memory 10, 11, Minister... Address signal 13... Judgment signal

Claims (1)

[Claims] In a pattern detection circuit that correlates and detects the number of matches or mismatches between a digital input signal and an arbitrary comparison pattern,
By inputting the output of the memory, which is the number of matches or mismatches between the input signal, its clock information, and the comparison pattern, as a memory address signal, the input signal and the comparison pattern are compared, and the comparison results match or mismatch. A pattern detection circuit characterized in that a pattern detection circuit counts numbers using the memory.