JPS5936812A - Monitoring unit - Google Patents

Abstract

PURPOSE:To improve information processing ability, by connecting a process input controller between a microprocessor and a bus, clocking only the input information subjected to state change then entering the input information to the microprocessor through an FIFO memory. CONSTITUTION:A process input device outputs input information to a data bus I while being updated sequentially by an output from a counter 10. The output from the counter 10 is also inputted to an RAM11, which outputs old data Q to a status change detecting circuit 12 by a data reading signal K. The state change detecting circuit 12 detects whether the old data Q coincides with new data from the data bus I or not. If dissidence is detected, a status change signal M is outputted to a controller 13, a data writing signal P is outputted to the FIFO memory 14, the time, new information, etc. at that time are written in the FIFO memory 14 and read in an MPU5 in accordance with the processing speed, and then the new information is written in the RAM11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides a monitoring device, particularly a gross input device using a microprocessor. m
This invention relates to a monitoring device that records time in units of seconds and enables efficient information acquisition.

[Technical background of the invention]

A conventional process input processing device using a microprocessor periodically scans the process input device used for inputting information.
The full ring was read and state change detection processing was performed.

FIG. 1 shows a configuration diagram of a conventional process input processing device.

In the figure, 1 is a process input processing device using a microprocessor.
U) 2 and process input device (hereinafter referred to as PVo) 3
-1. ...3-n, MPU2 and P Ilo
n@ are connected by an address bus and a data bus A. And MPU 2 ii P Ilo 3-
Process input information was obtained by sequentially sampling and reading 1, . . .-3-n.

[Problems with back shell technology]

In the case of the conventional device having the above configuration, all points of input information, including information with no state change, must be read, and each time, a state change detection process is performed by comparing it with the old information in the memory circuit. Therefore, the processing power of the microprocessor is severely restricted, and the number of points that can be read and the sampling period are also restricted.

Due to the above constraints, it is possible to detect state changes and attach a time in seconds to each input information of the next process, even if it is a device with considerable functionality such as a minicomputer. , which was not possible with devices using microprocessors.

[Purpose of the invention]

The present invention was made with the aim of solving the above-mentioned problems, and it adds a time to the manual information whose state has changed among the sequentially input process manual information, and stores only the necessary information via the FIFO memory. The purpose is to provide a monitoring device that can capture

[Summary of the invention]

In the present invention, a self-running process controller is provided between the microprocessor and the address bus and data bus, and the process input information is read by sampling four signals from each process input device, and the state changes. The system adds a time stamp to the process input information that has been received, and also imports it into the microprocessor via the FIFO memory along with the address of the process input device.

[Embodiments of the invention]

Examples will be described below with reference to the drawings. FIG. 2 is a configuration diagram of an embodiment of a monitoring device according to the present invention. In Fig. 2, numeral 4 denotes an input processing device; 1, an MPU;
A process input controller 6 according to the invention is provided between the MPU 5 and the PIlo 7-1"-7-n, and the MPU 5 and the process input controller 6 are connected to an address bus and a data bus B (
(hereinafter referred to as internal path) and connect to Zorocess input controller 6.
and PI107-1°...7-n are fully connected to address bus and data path C (hereinafter referred to as I10 path).

FIG. 3 is a detailed configuration diagram of the process input controller. 9 is a time signal 1 circuit which outputs the first time F among TmS, and also outputs a reset pulse signal J'(r
- Output. 10 is the address counter, h-v, IJ list! The address count is completely started by pulse J and clock signal N. A buffer memory circuit (hereinafter referred to as RAM) 11 temporarily stores process input information obtained by sampling every TmS using the address bus output G from the address counter 10. 12 is a state change detection circuit (hereinafter referred to as state change detection circuit)
The contents of the old information Q output from the RAM 11 and the new process input information obtained by the data bus I are compared, and if they do not match, a state change bit pattern (hereinafter referred to as a refreshing turn) H is set. At the same time as the output, a state change output signal (hereinafter referred to as refreshing signal) P is output. 13
is a RAM-FIFO controller (hereinafter referred to as controller), which outputs a data read signal and a data write signal when a clock signal, a pass signal N, and a reset pulse signal J are input. Also, P is FIFO memory 14
This is a data write signal for the controller 13, and is output when the state change signal is input to the controller 13. Then, the message F from the "Jigo" circuit 9, the address bus output G from the address counter 10, the change pattern H, and the new information data.
The outputs I and I are input to the FIFO memory 14, respectively.

Furthermore, the FIFO memory 14 is connected to the internal bus B of the MPU 5 by an address bus D and a data bus E, and
``It can be connected to the I10 path C by the address bus G and the disk path.

The fourth step is flowchart 1 for explaining the operation.
This will explain the series of operations. First, clock circuit 9
t: j: TmS The time F of accession to the throne and the reset pass (i number J) are output for each TmS.
Then, in response to the clock signal N input at the same time, counting of addresses O to P is started. As in hII, the controller 13 is also cleared by resetting Tonomalus J, and the RAM is
11, the read word K and write signal are corrected. The output from the address counter 10 to the address bus G is updated every few microseconds) and is connected to the input devices 7-1, . . . , 7-n.

Process input 'r'ij77-1 + ...7-
Addresses are determined for each of n ll-, and upon receiving the O address, the 7°C process input device 7-1 outputs the manual information to the data bus ■, and at the same time, the RAM 11 also receives the O address and outputs it from the controller 13. The old data (l) is outputted to the status change detection circuit 12 by the data read signal K thus generated.

On the other hand, the state change detection circuit 12 detects whether the old data Q from the RAM 11 and the new data from the data path match or not.

Now, when the state change detection circuit 12 detects a mismatch, it outputs a state change signal M-i, and the controller 1 receives this state change signal M.
3 V, t, data η-included signal Pi is output to the FIFO memory 14, and the time F and address G at that point are
1 state change) 9th turn H, new information I is written to the FIFO memory 14 and stored. Then controller] 3 is RA
A write signal is output to M11, and new information I is written to RAM11.

Next, the state change detection circuit 12 detects a match between the old data and the new data, and the next case will be explained. In this case, since the status change signal M is not output, the data write signal P from the controller 13 is
(See the dotted line in Figure 4).

Note that since a data write signal is periodically output from the controller 13 to the RAM 11, new information I is written.

After the state change detection and writing are performed for each address in this manner, the address counter 1° increments sequentially. In addition,
At this time, during Tm8, about 1000 bytes of process input, ie, process input information of 1000 addresses, is detected and written into the FIFO memory 14. Furthermore, since the contents of the RAM 11 may differ from the input information at the initial stage, such as when the power is turned on, the controller 13 locks the reception of the status change signal M for a certain period of time, and transfers all new information only to the RAM 11. data is written to the FIFO memory 14. However, once all the new information has been written to RAM 11, the reception lock for status change signal M is released and F
Writing of status change detection information to the IFO memory 14 is started. Furthermore, if a nonvolatile memory is used as the RAM 11, old information is stored even when the power is cut off, so there is no need to lock reception of the status change signal M at the initial stage.

The status change information once stored in the FIFO memory 14 is read in accordance with the processing speed of the MPU 5.

In the above embodiment, only the information whose state changes rarely is read is processed, but if the MPU 5 outputs a command signal to the controller 13 and forcibly receives the state change signal M, all the input Information 't MPU 5 can be read.

In this case, it is necessary to divide the clock signal N into an address update period corresponding to the processing capacity of the MPU 5 and perform sampling.

Furthermore, in the above embodiment, the information in the FIFO memory 14 is constantly read, but the invention is not limited to this. ,λ?U
The processing power of 5 is even more efficient.

In addition, if all of the process input information is not used and there is some that will be used in the future, the process input device 7-1...
If a ROM table corresponding to the address 7-n is added, there is no need to detect a change in status even if the process input device 7-m is not mounted, and writing to the FIFO memory 14 can be locked. Note that since the address counter 10 and the controller 13 use the same clock signal N, there is no difference in timing.

〔Effect of the invention〕

As explained above, according to the present invention, the continuously input new data and the stored old data are compared by the state change detection circuit, and only the information whose state has changed is sequentially stored in the FIFO memory with time stamps. Since it is configured to input data to the circuit and read it according to the processing capacity of the MPU, it not only improves the information processing capacity when investigating information such as continuous accidents, but also enables visual inspection without making any changes to conventional process power equipment. equipment can be provided.

4, -9□- months. ! 9 BJ'l,!
FIG. 1 is a configuration diagram of a conventional process input processing device, FIG. 2 is a configuration diagram of an embodiment of a monitoring device according to the present invention, FIG. 31 is a detailed configuration diagram of a process input controller, and FIG. 4 is an explanation of operation. This is a time chart for

1.4... Process input processing device, 2.5... Microprocessors, 6... Process input controller, 9... Clock circuit, 10... Address counter, 11... Buffer memory Circuit 1 12... State change detection circuit, 13... Controller, 14... FIFO memory circuit, Patent applicant: Tokyo Shibaura Electric Co., Ltd., Patent attorney: Nori Ishii, Mitsuru 2, Figure 4 (- ■ and - 1

Claims (1)

[Claims] In a monitoring device that inputs process input information from a plurality of process input devices to a microprocessor via a path, a self-propelled gross input controller is provided between the microprocessor and the path, and the gross input control device is provided with a self-running gross input controller between the microprocessor and the path. 1. A monitoring device characterized in that by attaching a time to only process input information whose state has changed depending on the device, the entire FIFO memory circuit is activated and the information is read into a microprocessor.