JPH03192855A - Synchronizing data reception circuit - Google Patents

Abstract

PURPOSE:To receive a synchronizing data without distinguishing a consecutive flag sequence in 15-bit sequence and an HDLC 16-bit sequence by detecting a zero insertion bit in a fetched data, applying forced reset to an octal counter, starting the circuit again to apply zero insertion bit elimination processing. CONSTITUTION:An octal counter 1c runs in itself till a flag detector 16 is turned on or a P output of a data receiver 1f is set and the counter is turned on for 8 reception clocks each and the data receiver 1f receives a signal continuously in the timing of INT. Even when flags are consecutive, a flag is detected again in a timing 2a (8 hits later), the flag detector 1b is turned on and the information is delivered to the data receiver 1f via the octal counter 1c and resynchronization is enabled. Moreover, a flag is detected again in a succeeding timing 3a (7 bits later), the flag detector 1b is turned on and the information is delivered to the data receiver 1f via the octal counter 1c and resynchronization is enabled. Thus, synchronization is taken without distinguishing the 16-bit sequence and the 15-bit sequence and data reception is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous data receiving circuit, and particularly to an HDLC one.
The present invention relates to a synchronous data receiving circuit having a continuous flag sequence of a 6-bit sequence and a 15-bit sequence.

[Conventional technology]

A conventional synchronous data receiving circuit receives synchronous data by fixing a continuous flag sequence of an HDLC 16-bit sequence or a 15-bit sequence to either one.

[Problem to be solved by the invention]

In the conventional synchronous data receiving circuit described above, the HDLC 1
There is a drawback that synchronized data cannot be received unless the continuous flag sequence of the 6-bit sequence or the 15-bit sequence is fixed to either one.

[Means to solve the problem]

The synchronous data receiving circuit of the present invention includes a serial/parallel converter that converts HDLC reception data of synchronous communication into 8-bit parallel data at the timing of a reception clock, and the parallel data outputted from the serial/parallel converter. a flag detector that detects the data "7E" pattern while the flag is detected; an octal counter that is activated at the detection timing of the flag detector and outputs a pulse; and an octal counter that outputs a pulse every eight received clocks; Data is taken in every 8 bits from the 8-bit flip-flop transmitted at the timing of the reception clock and the flip-flop at the timing of the output pulse of the octal counter, and a zero insertion bit in the taken data is detected. and a data receiver for forcibly resetting and restarting the octal counter to perform zero insertion bit removal processing.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The received data is synchronized with the reception clock, and the center portion of the reception data coincides with the transition timing (falling edge) of the reception clock from ON to OFF.

The received data is serial/transmitted at the timing of the receive clock.
It is converted into 8-bit parallel data by a parallel converter 1a, and transmitted to a flag detector 1b and an 8-bit flip-flop 1e.

The HDLC continuous flag sequence includes a 16-bit sequence ``...0111111001111110...''
・” and the 15-bit sequence “...01111110
1111110...", but the flag detector 1b
will turn on regardless of which of these conditions.

Further, the flip-flop 1e receives the output of the serial/parallel converter 1a at the timing of the reception clock.

The output of flag detector 1b is transmitted to OR gate 1d. At this time, the P output of the data receiver 1f is kept OFF. When the OR gate 1d turns on, the octal counter I
C is reset and the octal counter 1c is initialized. After this, the Q output of the octal counter IC is transmitted to ONL and the interrupt input port INT of the data receiver 1f every eight reception clocks.

The data receiver 1f receives the data at the INT timing. In the reception process, the read pulse output R of the data receiver 1f is ONL, which is transmitted to the output enable OE of the flip-flop 1e, and the output QO to Q of the flip-flop 1e is transmitted to the output enable OE of the flip-flop 1e.
7 is transmitted to the data input ports DO to D7 of the data receiver 1f, and the data receiver 1f takes in the 8-bit data, thereby completing the process. INT of data receiver 1f
is generated every eight reception clocks, so the data receiver 1f can receive the output of the flip-flop 1e without missing every 8 bits.

The octal counter IC runs on its own until the flag detector 1b turns ON or the P output of the data receiver 1f turns ON, and the data receiver 1f continuously receives signals at ONL and INT timings every 8 reception clocks.

FIG. 2 is a time chart showing the operation when a 16-bit sequence is received.

2 indicates the timing at which the flag detector 1b turns ON upon detecting the flag "7E"' pattern. 2b indicates the timing at which the octal counter 1c is transmitted to the ONL and INT of the data receiver 1f and received by the data receiver 1f. Even if the flags are consecutive, next timing 2a (after 8 bits)
The flag is detected again by the flag detector 1b, which is transmitted to the data receiver 1f via the ONL and octal counter IC, and resynchronization can be performed.

FIG. 3 is a time chart showing the operation when a 15-bit sequence is received.

3a detects the flag 7E'' pattern and outputs the flag detector 1.
This shows the timing when b turns on. 3b is octal counter 1
c is transmitted to ONL and INT of data receiver 1f, indicating the timing at which data receiver 1f receives it.Even if the flags are consecutive, the flag is detected again at the next timing 3a (after 7 bits), and the flag detector 1b detects the flag again. is transmitted to the data receiver 1f via the ONL and octal counter IC, allowing resynchronization.

As can be seen from FIGS. 2 and 3, synchronization can be achieved without distinguishing between 16-bit sequences and 15-bit sequences, and data reception can be achieved.

FIG. 4 is a time chart showing the operation of zero removal processing when zero-inserted data is received.

There is a “1” in the data received by the data receiver 1f.

If there are 5 consecutive bits, the next bit is checked and if the bit is '0°', it is determined that a zero has been inserted and zero removal processing is performed.
When `` is five consecutive bits and the next bit is ``0'', it is similarly determined that the bit is a zero-inserted bit.

4a indicates the timing at which the data receiver 1f receives;
At this time, the data receiver 1f inserts one zero insertion bit,
Or, if 2 bits are detected, the P output is ONL at the timing of 4b, and the octal counter 1 is sent via the OR gate 1d.
Force a reset to c. At this time, the data receiver 1f holds 8-bit data (previous stage data). The data receiver 1f controls the ON time of the P output by the number of zero insertion bits, and then turns the P output OFF.

As a result, the octal counter IC is initialized, and at timing 4c (after 1 bit or 2 bits), the octal counter IC notifies ONL and data receiver 1f of reception. At this time, the data receiver 1f receives 8 bits of data (later stage data).
hold. The data receiver 1f removes the inserted "0" from the previous stage data (shifts the higher bits from "0'' to the lower bits), and removes the upper bits of the previous stage data by the number of bits removed from the lower bits of the latter data. Zero removal is achieved through this operation.

Thereafter, the data receiver 1f uses the octal counter 1c which runs again.
Reception processing is performed for each 8-bit data at the output timing 4d of the counter.

〔Effect of the invention〕

As described above, the present invention has the advantage that synchronous data reception can be performed without distinguishing between continuous flag sequences of HDLC 16-bit sequences and 15-bit sequences.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 to 4 are time charts of the embodiment shown in FIG. 1a... Serial/parallel converter, 1b... Flag detector, 1c... Octal counter, 1d... OR gate, 1e... Flip-flop, 1f... Data receiver. -T)1 Figure +f-

Claims (1)

[Claims] A serial/parallel converter converts HDLC received data of synchronous communication into 8-bit parallel data at the timing of the reception clock, and a data "7E" pattern is detected from the parallel data output from this serial/parallel converter. a flag detector; an octal counter that is activated at the detection timing of the flag detector and outputs a pulse, and thereafter outputs a pulse every eight received clocks;
An 8-bit flip-flop that transmits the parallel data at the timing of the reception clock, and data that is fetched every 8 bits from the flip-flop at the timing of the output pulse of the octal counter, and zero insertion in the fetched data. A synchronous data receiving circuit comprising: a data receiver that detects a bit, forcibly resets and restarts the octal counter, and performs zero insertion bit removal processing.