JPS61166142A - Wiring for integrated circuit - Google Patents

Abstract

PURPOSE:To enable to rapidly decide a wiring ranging from its one end to its other end without spending a wasteful labor hour by a method wherein a clearance with the prescribed interval to the segments for the wiring route decided at first is set on the inner side of the wiring region and a new wiring region boundary line is formed. CONSTITUTION:Before the first wiring route is decided, a boundary line 2 with a clearance to the frame of a wiring region 1 is formed on the periphery of the inner side of the wiring region 1. After that, after segments, which are used as the wiring ranging from a starting end Si to a terminal Ti, are decided according to the prescribed procedures, segments bi1, Bi2...bil parallel to the segments decided are formed in the residual wiring region in such a way as to have a clearance width to the segments decided for setting a clearance for the following wiring to be formed adjacent to the wiring decided at first. A boundary line 3 to show the residual wiring region is anew formed from both of the segments bi1...bil formed according to these procedures and the boundary line 2 formed at first. This boundary line 3 gives a direction needed for deciding the following wiring route.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a wiring method for integrated circuits in semiconductor chips such as ICs and LSIs, and more particularly to a wiring method for speeding up automatic wiring using a computer.

<Summary of the Invention> The present invention has the advantage of forming a plurality of wires in a single layer in a part of a semiconductor chip without intersecting each other. According to the order, the wiring is sequentially connected as a wiring route along the area boundary line from between the starting end and the ending end for the first wiring, and the wiring is connected between each starting end and the ending end.

<Prior Art> In the work of forming wiring on a semiconductor chip for an integrated circuit, a method of automatically wiring using a computer has been developed. These traditional automatic wiring methods include:
In any of the above methods, such as the maze method or the line search method, firstly, in order to determine the wiring route, the terminal end of the wiring is exposed to sunlight, and the wiring is progressed within the wiring area.
The route that was currently being progressed was deemed to be inappropriate at the time when an obstacle occurred due to intersection with other wiring that had already been determined, and the work was returned to the starting point and proceeded to the ending point again using a different route. The wiring is determined by repeating the work until the end can be reached without any problems.

<Problem that the invention seeks to solve> In this way, with conventional methods, it is not possible to know in advance if there is a problem on the way, and the wiring work must proceed until the problem is encountered, then return to the starting point and start the work again. The problem is that line segments other than the desired route must be searched, resulting in a long processing time and hindering the design of integrated circuits.

<Means for Solving the Problems> In order to eliminate the drawbacks of the conventional wiring method as described above, the present invention provides a method for eliminating the problem in which the plurality of wires intersect with each other in a certain wiring area where a plurality of wires intersect. The wiring order is determined in advance, and when drawing a wiring route according to this determination, the next wiring route is determined along the boundary of the wiring area formed by the previously determined wiring route. The wiring area formed by the above-determined wiring route is formed in advance, including clearances between the wirings.

〈Operation〉 - According to the wiring method described above, a line segment search for wiring is performed for each wire ranked ``G, llrM'' along the boundary of a thick wiring area formed on the already determined wiring route. . Therefore, it is possible to speed up rigid line processing without executing unnecessary searches. - <Example> The wiring area 1 shown in FIG. 1(a) is a part of an integrated circuit semiconductor chip, and the wiring area 1 has a
- Wiring lines for interconnecting semiconductor circuits provided on a conductive substrate are formed in a single layer by crossing each other in the following procedure. The wiring region 1 usually includes a plurality of wires (zero wires), and each pair of ends of the wires are located in a frame -F surrounding the wiring region.

Each 0 wire can be expressed by a line segment connecting a pair of points whose coordinates are given on the frame of the wiring area, and between these pair of coordinates within a predetermined area called wiring area 1. Connecting line segments are first determined by giving their coordinates and setting a condition that line segments must not intersect with each other.
The wiring from the th to the nth is ordered.

However, not only do the wires not intersect with each other, but also clearances are set between the rigid wires based on manufacturing technology constraints.

Next, a procedure for determining wiring while maintaining clearance between line segments will be described.

The two points for the first wiring on the frame of the wiring area 1 are defined as the starting end S1 and the ending end TI, as shown in FIG. 1 (1).

(2) Before determining the first wiring route, a boundary line 2 with the above-mentioned clearance is formed around the inside of the wiring area 1 with respect to the frame of the wiring area 1.

■ To determine the violet-th wiring route, first draw a line segment a from the starting edge Si toward the inside of the wiring area until reaching boundary line 2.
is formed. The line segments for wiring below, including the line segment aH1, are all extended horizontally and vertically, and are usually parallel or perpendicular to the frame line of the wiring area 1.

Similarly, a line segment a1p reaching the boundary line 2 is formed from the terminal end Ti.

” - From the point reaching boundary 2 of marked line segment a11, move along the predetermined boundary to the next line segment a, 2 . a13... is formed. A line segment ai extended from the starting point S1.

al. ... completes the first wiring at the point when it reaches the line segment a14 from the terminal Ti.

Here, the predetermined boundary indicated by "-" is the boundary line 2 for the first wiring, but for the first wiring, the (i-1)th wiring is determined.

■ After the line segment that will be the wiring from the start end S1 to the end Ti is determined by the above procedure, in order to set the clearance for the next adjacent wiring, the width of the clearance is set in the remaining wiring area for the determined line segment. First of all
Parallel line segments bi+, bi2・bI as shown in figure (C)
form e.

■ Parallel line segment bi+bIe formed by the above procedure
From the previously formed boundary line 2, a new boundary line 3 is formed for the remaining wiring area as shown in FIG. 1(d). This boundary line provides the direction for determining the next wiring route.

-1- Execute steps ① to ② at the 1-19th dimension of the starting end and the ending end to form n wires in the wiring area 1.

When the above procedure is executed here, the following problem may occur, especially at step (2).

For example, assume that the (j-1)th wiring is completed and a boundary line 4 of a new wiring area is formed as shown in FIG. 2(a). Next, when the third wiring from the starting end S to the ending end T is executed according to the above procedure ■, the wiring result is shown in Figure 2 (1
] ) is line segment 5 shown by a thick line.

When the process of step (2) is executed on such line segment 5, as shown in FIG. and 1) Or line segment bj, intersects J5 like bj9
18 points are generated. The parallel line segments that are intersected by the parallel line segments that intersect in this way are subjected to a process of detecting the intersection and omitting the line segments, thereby forming the boundary line 6 shown in FIG. 2(d).

The method for detecting the intersection is to detect each line segment 1) j1 to 11 given by the coordinates of both ends, and for the horizontal line segment, move from the vertical line segment farther away to the closer one. The presence or absence of intersection is detected sequentially. In this example, for line segment bj1, b o→l〕 −〉b −>
b, followed by line segment bj11 versus Jl 18
36 ] 1 then 1] →b →l]・-)
1], line segment b] 12 J4 3 for 2
6 18bjlI01)J9-)l)]7→1]
Intersections are detected based on the coordinate data in J5 order. line segment b
and line segment b1. The intersection of is detected and the line segment b15,
1) 16, I) 37, 1) 18 hurt, Figure 2 (
A boundary line 6 shown in d) is formed.

<Effects of the Invention> According to the present invention, it is possible to quickly determine the wiring from one end to the other end while maintaining the clearance between the lines, and to avoid wasted time and effort. It is possible to significantly speed up pattern design on a chip, and further enhance the effectiveness of automatic wiring.

[Brief explanation of drawings]

Figures 1(a) to (d) are schematic diagrams of a wiring area for explaining an embodiment of the present invention, and Figures 2(a) to (d)
) is a model diagram of a wiring area for explaining another case of an embodiment according to the present invention. 1: Wiring area 2: Boundary line ai+~"i#" Line segment for wiring b, 1~bj#: Line segment of boundary line Sl: Starting end Tl: Terminal agent Patent attorney Aihiko Fukushi (et al.) 2 people) Figure 1 (
C) Figure 2 (C7) Figure 2 (C) Figure 2 (d)

Claims (1)

[Claims] 1. a. A method of forming a plurality of wires crossing a partial region within a semiconductor chip, b. Based on positional information of two corresponding points on the boundary of the wiring region, Order each wire so that no intersection occurs between the wires, c. Connect two corresponding points on the area boundary line with a line segment along the boundary to form a wiring route, and d. 1. A wiring method for an integrated circuit, comprising: forming a new area boundary line by setting a clearance at a predetermined interval inside the area with respect to a line segment for the area.