JPS6118166A - Compaction method of layout - Google Patents

Abstract

PURPOSE:To search easily a compression ridge and to attain a high speediness of compaction by dividing rectangularly a space area of a layout into patterns of an initial layout, extracting chaining rectangles and detecting and erasing a minimum wide space area. CONSTITUTION:A minimum clearance is made on circuit elements 10, 11 of an initial layout from a front processing portion. This area which lines are slanted at a clearance part 2 and a clearance and a line width on only an wire 12 falling at right angles with the direction of compaction is for the area for compaction and is divided rectangularly in the dividing part 3. A longitudinal area with a minimum value in the direction of compaction in common in each rectangle on each pass found to reach the top through a chaining (contacting) rectangles from the bottom of a layout is detected. This area is a compression ridge, and its minimum value is a compression ridge width. A horizontal compaction is done by erasing a compression ridge detected in an erasing element 5 from a layout.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement of a compaction method for mask layout of LSI and the like.

Mask layouts used in LSIs and the like are created using CAD technology, and the initial layout provided by a designer at the time of creation usually includes empty areas between layout elements.

Such an initial layout cannot be used as it is as a mask layout for LSI etc. from the viewpoint of effective use of the semiconductor chip area.

Therefore, conventionally, empty areas existing in the initial layout are deleted to create a mask layout, and the mask layout is used for manufacturing LSIs and the like.

[Conventional technology] “Contiguous free space from a given initial layout (
There is a compression ridge method as a technique for eliminating compression ridges (hereinafter referred to as compression ridges) from the initial layout.

The search for compression ridges in this technique starts from the bottom of the layout as shown in Figure 6, extends the compression ridge while checking the design rules, and when an obstacle is encountered, searches for the shear line.
1ine) Generate S L and search for a new compression ridge CR.

If shear line cannot be generated, go back up the compression ridge (back tracking) BT
It's like trying again.

The compression ridge searched in this way may intersect with the wiring in the direction perpendicular to it (the solid line in Figure 7A), but it may also include parallel wiring or include circuit elements (the 7th
Blocks connected by solid lines as shown in Figure A) must not intersect.

Also, the compression ridge must cross from the left side to the right side of the chip, or from the bottom side to the top side.
The compression ridges may be connected by shear lines. Shear lines must not intersect with wiring or circuit elements.

The compression ridges thus obtained are sequentially erased (see FIGS. 7A to F), and the layout is gradually changed (
The compression ridge technique is constructed in such a way that pressure is applied (from A to F in FIG. 7).

[Problem that the invention seeks to solve]

In the above technique, a major problem is how to determine the locations of shear lines and bank tracks, which exist almost infinitely in the initial layout, which makes the search for compression ridges complicated and the calculation time unpredictable. In addition, as the layout is compacted, it takes time to search for compression ridges, making it difficult to determine whether the search is complete.

Means for Solving Problem c] The present invention provides a layout compaction method that can solve the above problem.
In a device for compressing a layout by deleting free space from an initial layout given when designing a mask layout such as, for example, dividing means for dividing the free space of the initial layout into eight rectangles on the orthogonal coordinates of the initial layout; Extract the rectangles that are chained from one side of the layout to the opposite side at the second coordinate perpendicular to the first coordinate for which compaction is to be performed, and find the minimum width common to the first coordinate of these rectangles. A detection means for detecting an empty area, and an erasing means for erasing the minimum width empty area from the layout.
This means is constructed by adding means to provide clearance to the LSI or other pattern of the initial layout prior to rectangular division in the first means.

[Effect]

According to the method of the present invention, - After giving or not giving a clearance to the LSI etc. pattern in the initial layout, the empty area in the initial layout is divided into rectangles, and among these rectangles,
Extracts rectangles that are chained from one side of the layout to the opposite side in the direction perpendicular to the compression direction, detects the smallest free space in the compression direction that is common to these rectangles, and deletes this from the layout. This makes it easier to search for compression ridges and achieve faster compaction.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the invention. This example is CAD
This is an example implemented in a device. In this figure, reference numeral 1 denotes a preprocessing unit that converts initial layout data given when designing a mask layout for an LSI or the like into data that is easy to compact, secures a data area, and the like. Reference numeral 2 denotes a clearance granting unit that provides clearance from the preprocessing unit to the LSI or other patterns in the initial layout. Reference numeral 3 denotes a dividing section which divides the empty area of the initial "aud" into rectangular shapes according to predetermined rules.

4 is a detection process in which rectangles that are chained from one side of the layout to the opposite side in the direction perpendicular to the compression direction are extracted from the divided rectangles, and a free area with the minimum width in the compression direction that is common to these rectangles is detected. Department. Reference numeral 5 denotes an erasing unit that erases the detected minimum width free area from the layout. Reference numeral 6 denotes a post-processing unit that converts the compacted layout data into the data format before compaction, returns the data area to the management of the host device, and so on.

The compaction process under this configuration will be explained below.

First, its outline will be explained using FIG. 2. Pre-processing section 1
Minimum clearance for circuit elements 10°11 of initial layout 1 from 1, and wiring 1 perpendicular to the compaction direction
The line width and clearance are applied only to 2 by the clearance providing section 2 (see FIG. 2C) (the dotted line in the figure indicates this). The shaded area in FIG. 2A is the empty area to be compacted. This empty area is divided into rectangles by the dividing unit 3 as will be described later (see FIG. 2C).

(■ to ■ in this figure indicate the divided rectangles).

In the detection unit 4, a bus (
■−■−■−■−■；■−■−■−■−■−■) and detect the vertical area of the minimum value in the compaction direction common to each rectangle on each path (second (See Figure C)
. This area is the compression ridge, and its minimum value is the compressor ridge width. Erase fIIl1
5, horizontal compaction is performed by erasing the detected compaction ridges from the layout (see second diagram).

Vertical compaction can also be performed in exactly the same manner.

After the completion of the processing, processing is performed in the post-processing section 6.

While referring to FIGS. 3 to 5, the above-mentioned rectangular division and compression ridge search can be performed in its horizontal direction.
I will explain Bakjong in detail.

Give clearance to line segments and circuit elements in the initial layout (for line segments, give half the line width on both sides). In providing this clearance, parallel line segments ~[phase] are generated for only the vertical line segment 2o for the line segment, and for the circuit element 21 only for the vertical line segment of its outline (see Fig. 3). (see step Sl in FIG. 5). At that time, the line segment on the left side of the generated parallel line segment has an upward direction,
Further, a downward direction is given to the line segment on the right side. In addition, the left side of the layout is a downward line segment [phase], and the right side is an upward line segment @.

Map the Y coordinate of the end point of each generated line segment to the Y axis,
These are called basic coordinates, and the interval a between adjacent basic coordinates is
bib cH...-;Bf is called the basic interval.

For any basic section, a group of line segments including that section is found from the respective sets of upward line segments and downward line segments. The obtained upward and downward line segments are sorted by axis coordinates (X coordinates), and the corresponding upward and downward line segments represent one rectangle. For example, for the basic interval (e-f) in Figure 3, the downward line segment is ([phase], o, [phase]), and the upward line segment is (0
, ■, 0> are found. A set of these line segments ([phase]
,■).

(0, [phase]) and (@l, @) each represent a rectangle.

Such processing is performed for all basic intervals. If adjacent basic sections share the same upward line segment and downward line segment, the rectangles represented by them can be merged into one. The set of rectangles thus obtained is obtained by dividing the empty space of the layout into rectangles (step S2 in FIG. 5).

The layout divided into rectangles in this way is expressed in a graph as follows. That is, nodes are assigned to each rectangle, and if there is a vertical connection (chain) relationship between these nodes, that is, between rectangles, a graph is generated by assigning directed edges (arrows in FIG. 4). Step S3 in the figure). Each node N1 has two values: weight Wi and gain G1
, the weight WI is a value meaning the horizontal width (@ in the compaction direction) of the corresponding rectangle, and the gain G1
is a value to which the ridge width is added each time a part of the corresponding rectangle is made into a compression ridge, and is initially zero. Furthermore, even if the rectangles do not touch each other, if they can be connected by a shear line, a directed edge is assigned between the rectangles.

Once the graph is generated in this way, the problem of finding a compression ridge is transformed into a problem of finding a path from the graph. The path must start from the source node S (the node corresponding to the bottom rectangle in the layout) and end at the sink node T (the node corresponding to the top rectangle in the layout), and must also be on the path. The weight Wl of the node must not be 0 (step S4 in FIG. 5).

For the nodes on the bus thus discovered, the minimum weight W min is determined. This weight W m i
While subtracting n from the weight Wl of each node on the bus, the gain G
Add to i. The W min is the width of the compression ridge in that path. The combination long ridge obtained in this way is deleted from the layout. That is, by moving the circuit elements and wiring on the right side of the compression ridge in parallel to the left by W m f n, the layout is compacted by the amount of the compression ridge (step S6 in FIG. 5).

As long as a path for performing such compaction exists, a similar compaction process is performed each time a path is discovered.

Then, as described above, vertical compaction is performed in the same way, and the compaction ends (No.
), post-processing is performed and the process proceeds to the next step.

〔Effect of the invention〕

As described above, according to the present invention, an empty area of the layout is divided into rectangles, and the compression direction common to the rectangles that are chained from one side of the layout to the opposite side in the direction perpendicular to the compression direction is calculated. Since a free area with the smallest width is detected and this area is deleted from the layout, it becomes easier to search for combination long ridges, and the effect of speeding up compaction can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining an overview of the embodiment in FIG. 1, and FIGS. 3 to 5 are diagrams for explaining details of the embodiment in FIG. 1. FIG. 6 is a diagram for explaining a conventional compression ridge search mode, and FIG. 7 is a diagram showing a compaction process by erasing compression ridges. In the figure, 2 is a clearance imparting section, 3 is a dividing section, 4 is a detecting section, and 5 is an erasing section. Figure 2 1n Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (2)

[Claims] (1) In an apparatus for compressing a layout by deleting free space from an initial layout given when designing a mask layout for an LSI or the like, a dividing means for dividing the free space of the initial layout into rectangular shapes on orthogonal coordinates of the initial layout; Extract rectangles that are chained from one side of the layout to the opposite side at the second coordinate perpendicular to the first coordinate where compaction of the rectangular coordinates is to be performed, and calculate the minimum width in the compaction direction common to these rectangles. 1. A layout compaction method, comprising: a detecting means for finding a free area of the minimum width; and an erasing means for erasing the free space of the minimum width from the layout. (2) In a device that compresses a layout by deleting free space from an initial layout given when designing a mask layout for an LSI or the like, the LSI of the initial layout
a clearance providing means for giving a clearance to an equal pattern, a dividing means for dividing an empty area of the initial layout to which the clearance has been given into rectangles on the orthogonal coordinates of the initial layout, and a first coordinate at which the compaction of the orthogonal coordinates is to be performed. detecting means for extracting rectangles chained from one side of the layout to the opposite side at second coordinates perpendicular to the layout and finding a free area with the minimum width in the compaction direction common to these rectangles; A layout compaction method characterized by comprising an erasing means for erasing a small free area.