JP3080161B2 - Graphic layout compression apparatus, graphic layout compression method, and recording medium - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout of a large-scale semiconductor integrated circuit and a layout design of a printed wiring board.

[0002]

2. Description of the Related Art An automatic layout change system using a compaction method of moving a component by moving a component in a component moving direction is used for designing a layout of a large-scale semiconductor integrated circuit or a layout of a printed wiring board. . For this type of automatic layout change system, various compaction techniques for moving components in conjunction with each other have been proposed.

An example of a conventional graphic compression system is disclosed in Japanese Unexamined Patent Application Publication No. 1-279373, entitled "LSI Layout Compressor".
(Hereinafter referred to as Conventional Example 1). In the conventional example 1, in the design of an integrated circuit, at the stage after wiring between terminals of cells, both cells and wiring are compacted.

In addition, as in the "partial compaction processing method of layout" described in Japanese Patent Application Laid-Open No. Sho 62-78681 and the "compacting method of layout" described in Japanese Patent Application Laid-Open No. Sho 63-214880, wiring is applied to semiconductor cells. Alternatively, many of the conventional methods for compacting together with parts (hereinafter referred to as Conventional Example 2) use a method using a constraint graph. As another method, a jog insertion compaction method has been proposed that can change the structure of the constraint graph by inserting a bend called jog into the wiring, thereby reducing the layout area and correcting points that violate design rules. (Reference (1): Wataru Yamamoto, Tei Awashima , Masao Sato, Tatsuo Ohtsuki "Chip compaction method using constraint graph and its evaluation", IEICE Technical Report VLD91-43pp41-48 1
991, Reference (2): Wataru Yamamoto, Tei Awashima , Masao Sato, Tatsuo Ohtsuki , "Chip Spacers for Layouts Including Violation of Design Rules", IEICE Technical Report VLD 91-120pp37-44, 1992.
July 7, Reference (3): Wataru Yamamoto, Tei Awashima , Masao Sato, Tatsuo Ohtsuki "Chip / spacer with automatic diagonal wiring generation function",
IEICE Technical Report VLD 91-123pp17-24 1992).

As shown in FIG. 33, such a graphic layout compression apparatus 5000 of the related art 2 includes a longest path search unit 250, a layout enlargement unit 260, a layout automatic compression unit 270, and a layout modification designation unit 280. .

The graphic layout compression device 5000 operates as follows.

The longest path search means 250 searches the order of the longest graphic element in the layout in order to compress the layout of each cell and wiring on the LSI chip into a smaller area, and finds it in FIG. 34 (original arrangement). It is displayed on the display unit as shown by the diagonal lines.

The layout enlarging means 260 inserts, into the layout, a space that crosses the longest path of the constraint graph as shown in FIG.

In the example shown in FIG. 34, the layout correction designating means 280 moves the second component from the bottom to the right so as to shorten the longest path in response to an instruction from the operator. Move the part from the longest path in the graph.

Then, the layout automatic compression means 270
Changes the layout of the corrected result (up and down in FIG. 34)
Compress.

However, the conventional layout automatic compression means 270 reduces the size of the layout to either one (for example, vertical) first and then reduces the size to the other (horizontal) when performing compaction for reducing the layout both vertically and horizontally. In order to reduce the layout in two steps, for example, when the layout is reduced in one direction (for example, vertically), the components are densely packed in that direction, and then the components are arranged vertically (horizontally). When the wiring layout is reduced, there is a disadvantage that the reduction of the arrangement is hindered.

The reason for this drawback is that in these compaction systems, compaction moves the layout in a predetermined specified direction regardless of whether the component is moved in the vertical or horizontal direction. This is because if there is an obstacle, the movement of the parts is hindered.

In order to improve this disadvantage, a method of simultaneously moving in two directions has been proposed as two-dimensional compaction (hereinafter referred to as Conventional Example 3). It is (Reference (4): Hyunchul
Shin, Alberto L. Sangiovanni-Vincentelli, Carlo H.
Sequin, `` Two-DimensionalCompaction by 'Zone Refi
ning ''', Proc. of 23rd Design Automation Conferenc
e, 1986, pp115-122), an upper and lower constraint graph and a left and right constraint graph are created, and the semiconductor cells are sequentially moved from top to bottom. At this time, the cell is moved right and left at the same time as being moved directly below, and the cell is arranged at an appropriate position. Then, a fold (jog) is generated in the wiring, and the wiring is moved downward.

In Japanese Patent Application Laid-Open No. 5-274392, "Layout Compaction Method" (hereinafter referred to as Conventional Example 4), a substrate is divided into partial regions with a wiring as a boundary.
It has a partial pattern compression part of the partial region, and compresses the shape of the partial region of the substrate upward and downward from the edge of the upper substrate while compressing the shape of the partial region of the substrate left and right from the left substrate edge. Thus, the entire area of the substrate is uniformly compacted while maintaining the relationship between the top, bottom, left and right of the area.

However, in Conventional Example 4, since the order of wiring cannot be changed, there are many wirings on the right side of the via hole on one layer surface and many wirings on the left side on another layer surface. If there is an inconsistency, the layout cannot be further compressed.

On the other hand, in Japanese Unexamined Patent Publication No. Hei 8-115344, "Automatic placement and routing apparatus" (hereinafter referred to as Conventional Example 5), as shown in FIG.
From the route A passing through the channel 32 in which the wires are stored,
The route is changed to the route B passing through the channel 33 in which the wire is housed, thereby alleviating the degree of congestion of the wiring. As a result, a wiring layout that minimizes the chip area due to compaction was obtained.

Then, BSG (Bounded Sliceline-Gri)
A method has been proposed in which a rectangular area surrounding a component is specified in d), and the dimensions of this area are changed to simultaneously compact vertically and horizontally (hereinafter referred to as Conventional Example 6) (Reference (4): Keishi Sakamoto) , Tsuyoshi Kurasawa, Yasuhiro Takashima, Shigehisa Nakatake, Yoji Kajitani "BS
Proposal of Simultaneous Placement and Schematic Routing Optimization Method Based on G Structure ", IEICE Technical Report VLD97-40pp175-182 June 1997
Month).

However, in the conventional examples 5 and 6, the partial area of the substrate can be compressed by two-dimensional compaction or partial compaction.
The expansion and contraction of the wiring in the vertical and horizontal directions expands and contracts the partial area, and there is a drawback that diagonal wiring cannot be handled. In addition, there is a drawback that the printed wiring board cannot cope with a pattern having a via hole having a dimension larger than the wiring width.

The reason for this drawback is that, in this system, the channel wiring is made in a rectangular area between the semiconductor cell arrangement areas, and the via holes connecting between the layers are roughly wired so as to have a wiring width of approximately the wiring width. The outline has been decided. On the other hand, in a printed wiring board, other areas of component terminals (corresponding to semiconductor cells) are larger than the area occupied by the component terminals, and oblique wiring is frequently used. Also, the via hole connecting the wiring layers has a size as large as the component terminal, so the via hole cannot be ignored. However, the size of the via hole is ignored in the conventional schematic wiring method.

On the other hand, in Japanese Patent Application Laid-Open No. Hei 10-34991, "Compaction Compaction Device, Wiring Method Wiring Device, Schematic Wiring Method and Schematic Wiring Device" (hereinafter referred to as Conventional Example 7), all the original wirings are erased once. However, by performing compaction while performing new wiring, diagonal wiring has become possible.

However, even in the conventional example 7, it was not possible to cope with the compaction of a printed wiring board having a complicated layout in which components are arranged on the front and back surfaces, component regions overlap, and component terminals intersect.

[0022]

The drawbacks of the prior art as described above are summarized as follows. (1) If the image is reduced in one direction and then reduced in the other direction, the components are densely packed in the previously reduced direction, preventing rearrangement in the direction to be reduced later. (2) The layout cannot be compressed by arranging the regions with high wiring density on each layer surface when viewed from the direction perpendicular to the layer surface. (3) Diagonal wiring cannot be handled. (4) It is not possible to cope with a pattern having a via hole having a size larger than the wiring width. (5) Compaction of a printed wiring board having a complicated layout in which components are arranged on the front and back, component regions overlap, and component terminals intersect cannot be supported.

In view of the above conventional examples, an object of the present invention is to provide the following graphic layout compression apparatus and method.

First, component terminals are arranged in a partition room, and wiring is compacted using a data structure in which a wiring bundle width is recorded and taken into terminal constraint graph data of the component terminals on both sides of the partition line. In addition, compaction can be performed in any form including diagonal wiring.

Second, the compaction bottleneck can be reduced and the layout can be compacted into smaller areas.

Third, by arranging the components sequentially in the outer shape of the board and disposing the wiring together with the components, the component layout and the wiring can be compactly packed.

Fourth, components and wiring can be compacted more closely toward the center of the component layout.

Fifth, a compaction process can be performed in which the component can be moved to a predetermined target position and the component layout can be enlarged or reduced.

[0029]

In order to solve these problems, the present invention provides the following apparatus.

The present invention reads layout data including at least one layer pattern having wiring, component terminals, via holes, and a polygonal conductor shape arranged in a two-dimensional space, and components of a printed wiring board or semiconductor cells. In the graphic layout compression apparatus for compacting the layout, component terminals,
A means for creating constraint graph data having a combination of via holes, semiconductor cells, wiring, and components adjacent to each other as nodes at both ends, and, from layout data, component terminals, via holes, semiconductor cells, and component shapes for each layer surface Calculates the position of the vertical or horizontal partition line that divides the area to be placed, and calculates the terminal constraint graph data that has the component terminals and via holes stored in the area adjacent to both sides of the partition line as nodes at both ends Means and one end of the terminal constraint graph data approach the other end of the node in the compaction direction via a wire bundle that adds the width of the wiring and the necessary gap between the nodes at both ends of the terminal constraint graph data. Means for calculating the relative movement limit length of the component to be obtained, and recording the relative movement limit length of the component, and using the part number as a node, the terminal constraint graph data of all layers A means for creating constrained part constraint graph data, a part compaction means for moving a part terminal and a via hole of a node at the other end within a part relative movement limit length, and a part for layout data output by the part compaction means. And a re-wiring means for shaping the wiring into a wiring shape including a diagonal wiring at an interval between the wiring and the via hole and re-wiring the wiring.

Further, according to the present invention, in the graphic layout compression apparatus, the means for generating constraint graph data treats segments having the same signal name as non-interfering with each other and connects in parallel from segments having other signal names. The present invention provides a graphic layout compressing apparatus characterized by creating constraint graph data of a relation to be performed.

Further, according to the present invention, in the graphic layout compressing apparatus, via holes, component terminals or semiconductor cells are further displayed, and moving target vector data of moving target directions and moving target distances of individual components and via holes are designated. A graphic layout compression apparatus is provided, comprising: a component movement designation unit; and a unit for creating component constraint graph data for recording a component number and a fixed point as nodes.

Further, the present invention provides the graphic layout compressing apparatus, further comprising means for designating a center position of the compaction of the layout and compacting the layout toward the central position. I will provide a.

Further, according to the present invention, in the graphic layout compression apparatus, when compacting the component layout, the component terminals are moved in the compaction direction in order from the component in the compaction direction in accordance with the outer shape of the board. A graphic layout compression apparatus, comprising: means for compacting a terminal while moving it to an empty area beyond a partition line.

Further, the present invention provides the graphic layout compression apparatus, further comprising: means for changing the order of the component terminals, via holes, or other wirings in the compaction direction, and searching for a route for moving the wiring in the compaction direction; Thereafter, there is provided a graphic layout compression apparatus characterized by comprising means for compacting a component layout.

Further, according to the present invention, in the graphic layout compressing apparatus, a dead end of a wiring is further extracted, and a wiring and a via hole are moved in a different order from a component terminal, a via hole and other wirings to eliminate the dead end. A graphic layout compression device, comprising: means for searching for a path to be performed.

Further, in order to solve the above-mentioned problems, the present invention provides the following method.

According to the present invention, layout data including at least one layer pattern having wires, component terminals, via holes, and polygonal conductor shapes arranged in a two-dimensional space, and components of a printed wiring board or semiconductor cells are processed. In a graphic layout compression method for reading into a device and compacting the layout, a constraint graph having a combination of component terminals, via holes, semiconductor cells, wirings, and components adjacent to each other in a component outline as nodes at both ends from layout data for each layer surface From the data creation step and from the layout data, calculate the position of the vertical or horizontal dividing line that divides the area where the component terminals, via holes, semiconductor cells, and component outlines are arranged for each layer surface, Ends with component terminals and via holes housed in areas adjacent to both sides as nodes on both ends Through the step of calculating the constraint graph data and a wire bundle that adds the required width and the width of the wire sandwiched between the nodes at both ends of the terminal constraint graph data, the node at one end of the terminal constraint graph data has the other end. Calculating the relative movement limit length of the part that can approach the node in the compaction direction, and recording the relative movement limit length of the part, and using the part number as a node, the part restriction graph data that summarizes the terminal restriction graph data of all layers And the component compaction stage of moving the component terminal and via hole of the other end node within the component relative movement limit length, and shaping the wiring into a wiring shape that includes diagonal wiring at the interval between the component and the via hole. And a rewiring step of rewiring the graphic layout.

Further, according to the present invention, in the graphic layout compression method, the step of generating the constraint graph data includes treating segments having the same signal name as non-interfering with each other,
A graphic layout compression method characterized by generating constraint graph data of relations connected in parallel from segments of other signal names.

Further, according to the present invention, in the graphic layout compression method, via holes, component terminals, or semiconductor cells are further displayed, and movement target vector data of a movement target direction and a movement target distance of each component and via hole are designated. A method for compressing a graphic layout, comprising: a part movement designation step; and a step of creating part constraint graph data for recording a part number and a fixed point as nodes.

Further, the present invention further provides a method of compressing a graphic layout, the method further comprising the step of designating a center position of compaction of the layout and compacting the layout toward the central position. I will provide a.

Further, according to the present invention, in the graphic layout compression method, when compacting a component layout, the component terminals are moved in the compaction direction in order from the component in the compaction direction in accordance with the outer shape of the board. A method of compacting a graphic layout, comprising compacting a terminal while moving the terminal to an empty area beyond a partition line.

Further, the present invention provides the graphic layout compression method, further comprising: changing the order of the component terminals, via holes, or other wirings in the compaction direction, and searching for a route for bringing the wirings in the compaction direction; Thereafter, there is provided a graphic layout compression method including a step of compacting a component layout.

Further, according to the present invention, in the graphic layout compressing method, a dead end of the wiring is further extracted, and the dead end of the wiring and the via hole are moved by changing the order of the component terminal, the via hole and the other wiring. A method of compressing a graphic layout, the method including a step of searching for a path to be performed.

Further, in order to solve the above-mentioned problem, the present invention provides the following recording medium.

According to the present invention, layout data including at least one layer pattern having wires, component terminals, via holes, and polygonal conductor shapes arranged in a two-dimensional space and components of a printed wiring board or semiconductor cells are processed. In a machine-readable recording medium that records a graphic layout compression program that causes the apparatus to read and output layout data that has undergone compaction processing, from layout data, for each layer surface, component terminals, via holes, semiconductor cells,
Wiring and processing to create constraint graph data having a combination of adjacent ones of component outlines as nodes at both ends, and from layout data, for each layer surface, the area where component terminals, via holes, semiconductor cells, and component outlines are arranged Calculate the position of the vertical or horizontal dividing line to be divided,
Processing to calculate terminal constraint graph data that has component terminals and via holes as nodes at both ends that are stored in areas adjacent to both sides of the partition line, and the width and width of the wiring sandwiched between the nodes at both ends of the terminal constraint graph data A process of calculating a relative movement limit length of a component in which a node at one end of the terminal constraint graph data can approach a node at the other end in the compaction direction through a wiring bundle with a gap added, and recording a component relative movement limit length, The process of creating component constraint graph data that combines terminal constraint graph data on all layers with the component number as a node, and component compaction that moves the component terminal and via hole of the other node at the other end within the component relative movement limit length And causing the information processing apparatus to execute a process and a rewiring process of shaping and rewiring the wiring into a wiring shape including a diagonal wiring in a space between the component and the via hole. To provide a recording medium recording a graphic layout compressor.

According to the present invention, there is provided a recording medium comprising:
The process of creating constraint graph data treats segments with the same signal name as non-interfering with each other, and causes the information processing device to create constraint graph data of a relationship connected in parallel from segments with other signal names. Provided is a recording medium on which a characteristic graphic layout compression program is recorded.

Further, the present invention provides a recording medium comprising:
Further, a via hole, a component terminal or a semiconductor cell is displayed, a component movement designation process for designating a movement target vector data of a movement target direction and a movement target distance of each component and the via hole, and a part number and a fixed point are recorded as nodes. A recording medium storing a graphic layout compression program characterized by causing an information processing apparatus to execute processing for creating component constraint graph data.

Further, the present invention provides a recording medium comprising:
Further, the present invention provides a recording medium storing a graphic layout compression program characterized by designating a center position of compaction of a layout and causing an information processing apparatus to execute processing of compacting the layout toward the center position.

Further, the present invention provides a recording medium comprising:
Furthermore, when compacting the component layout, the components should be arranged in order from the compaction direction side according to the board outline.
Moving the component terminals in the compaction direction, and moving the component terminals to an empty area beyond the partition line, and causing the information processing apparatus to execute a compaction process. provide.

According to the present invention, there is provided a recording medium comprising:
Further, the information processing apparatus is configured to change the order of the component terminals, via holes, or other wirings in the compaction direction to search for a route that brings the wiring in the compaction direction, and then perform processing to compact the component layout. There is provided a recording medium having recorded thereon a graphic layout compression program.

Further, according to the present invention, in this recording medium,
In addition, it extracts the dead ends of the wiring, and creates wiring and via holes.
A recording medium in which a graphics layout compression program is recorded, wherein the graphics layout compression program is moved by changing the order of component terminals, via holes, and other wirings, and causing the information processing apparatus to execute a process of searching for a route for eliminating a dead end. .

[0053]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a semiconductor device having a wiring, terminals, via holes and a polygonal conductor shape arranged in a two-dimensional space.
And a graphic layout compression apparatus and a graphic layout compression method for compressing components in a pattern of a plurality of layers in the vertical direction and the horizontal direction while changing the wiring order.

According to the present invention, the layout data 20 is input, the component terminals and via holes are divided into segment data 30 for each layer, and the wiring and polygonal conductor shape 4 are segmented for each bending point and branch point. Segment data 3 to be divided and connected
0 is assigned a common part number 32. Here, the part number 32 is specified for each via hole.

For each layer surface, a lattice structure is created which divides the substrate area into rooms (partition rooms) divided by vertical and horizontal partition lines, and each component terminal is stored in a partition room. Then, via holes adjacent to each other via a partition line, component terminals or pieces of semiconductor cells are connected to each other via a wire bundle consisting of a required width and a width of a wire sandwiched between upper and lower, left and right pieces. The terminal restriction graph data 50 that stores the distance that can approach the partition line in the vertical direction is created for each layer surface.

Next, the dead ends are eliminated by the wiring alignment means mainly taking out the wiring from the dead ends of the wiring traveling in the direction perpendicular to the compaction direction and closing the dead ends.

Next, for the inconsistency between the layer planes having the graph length of the terminal constraint graph created for each layer plane, the shortest path between the layer planes is matched by a process of changing the order of the wiring and the via hole, and the terminals on all the layer planes are matched. A component constraint graph 60 in which the constraint graphs are aggregated is created.

Next, the component layout is compacted by the shortest path of the component constraint graph data 60, and finally,
The wiring is shaped by the rewiring means 109 and rewired between the component terminals.

In FIG. 1, terminal restriction graph creating means 1
04 creates terminal constraint graph data 50 having nodes of component terminals (excluding wiring) as nodes, and the terminal constraint graph data 50
The relative movement of the component that can be approached via the wire bundle that adds the required width and the width of the wire sandwiched between the pieces of the node at both ends of the terminal constraint graph data 50 is the movement amount of the node approaching the node at the other end. The limit length 62 is calculated and stored. Parts compaction means 1
07 moves and compacts the components that are linked in the component movement direction.

In this manner, the order of the via hole and the wiring is switched, and compaction in which the wiring density between the layer surfaces is matched is enabled.

A graphic layout compression apparatus 1000 according to a first embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a graphic layout compression apparatus 1000 according to the present invention includes a computer 100 (central processing unit; processor; data processing apparatus) which operates under program control, and a display unit (CRT display or liquid crystal display) 101. And an operation unit (keyboard and mouse or tablet or the like) 102.

The internal configuration of the computer 100 will be further described. The computer 100 includes a layout data conversion unit 111, an operation command input unit 110, a constraint graph creation unit 103, a partition room arrangement unit 112, a terminal constraint graph creation unit 104, a shortest path Calculation means 105, component compaction means 107, wiring compaction means 1
08, rewiring means 109, layout data 20, segment data 30, constraint graph data 40, terminal constraint graph data 50, component constraint graph data 60, and wiring limit position data 80.

Each of these means operates roughly as follows.

The layout data converting means 111 creates the segment data 30 by decomposing each shape of the layout data 20 into segments.

The constraint graph creation means 103 includes component terminals,
The unit data 30 of the via hole or the component terminal or the wiring adjacent to the wiring in the Y direction or the X direction is extracted, and the Y direction or the X connecting the adjacent unit numbers 31 to each other is extracted.
Constraint graph data 4 recording direction 61 of direction graph
Create 0.

The partition room arranging means 112 arranges, in a partition room, a piece of a component terminal or a piece of a via hole (excluding wiring) or a component outer shape for each layer surface or component placement surface, and stores all of the component terminals to be stored. The partition line is moved in parallel to the position surrounding.

The terminal constraint graph creating means 104 records, for each layer surface, adjacent component terminals or via holes in any of the vertical and horizontal directions, records the adjacent direction as the graph direction 61, and records both component terminals (via holes). The terminal constraint graph data 50 for calculating and recording the component relative movement limit length 62 that indicates the limit of movement that can be approached closest to each other is created.
Also, the part number 32 is recorded as a node at both ends of the graph,
A value obtained by quantizing the component relative movement limit length 62 of the terminal constraint graph to a multiple of the arrangement grid spacing of the via holes or less is recorded as the component relative movement limit length 62, and the component constraint graph data 60 having the terminal constraint graph number 51 recorded therein is It is created from the terminal constraint graph data data 50 of all layers.

The component compaction means 107 moves the component terminals (via holes) accommodated in the partitioning room in order from the lower left corner to the left by the shortest path length of the X-direction component constraint graph data 60, and moves the shortest of the Y-direction component constraint graph data 60 Move down along the path length and calculate the minimum partition room surrounding the component terminal (via hole).

The component movement designation means 301 is characterized in that a component terminal (via hole) is moved from a compartment where the component terminal is stored to another partition room.

Here, in the case of a multi-terminal component having a fixed terminal interval, each terminal has a fixed relative position of a partition room address corresponding to the interval. The component terminals (via holes) are simultaneously moved to the partition room at the same relative address.

The shortest path calculation means 105 creates the shortest path of the component constraint graph data 60 from the top, bottom, left and right of the board,
Thus, by calculating the component margin, it is detected that the component arrangement position causes a neck.

The wiring compaction means 108 obtains octagonal wiring limit position data obtained by bending the wiring along the shape of the component terminal (via hole) at one end of the terminal constraint graph data 50 sandwiching the wiring. 80 is created and stored.

The rewiring means 109 reshapes the wiring into a shape including diagonal wiring and performs rewiring.
0 is stored.

The operation of each unit constituting the computer 100 is as described above. Next, the operation of the entire graphic layout compression apparatus 1000 will be described in detail with reference to FIGS. FIG. 2 is a flowchart of the operation of the graphic layout compression apparatus 1000. 3 to 5 are diagrams showing the structures of various data of the present invention. 6 to 8 are plan views showing patterns for explaining the operation of the graphic layout compression apparatus 1000. FIG. 6A is an initial layout of a printed wiring board to be processed by the graphic layout compression apparatus 1000. FIG. 8B is a diagram showing the layout of the final result. FIG. 9 is a diagram showing the left and right component terminals of the vertical partition line of the partition room and the wiring bundle therebetween, and showing the procedure for creating the terminal constraint graph 50. FIG. 10 shows the relative movement limit length 6 of the component.
FIG. 3 is a diagram illustrating the concept of FIG. FIG. 11 is a diagram showing a partition line and a wiring bundle, and showing a procedure for changing the partition line.

In step S100, first, the layout data conversion means 111 converts the layout data 20 as shown in FIG. 6A into component terminals, via holes, wiring, polygonal conductor shapes 4 and component outlines constituting a layout pattern. , Board outlines, marking pattern characters, etc., are decomposed for each layer surface to form one piece data 30, and the shape is approximated to an octagon, and the piece data 30 is stored in the data structure shown in FIG. . The component terminals, via holes, and wiring are arranged on the signal layer and the power ground layer surface, while the component outline is arranged on the component outline layer surface. Marking and characters and marking-prohibited area patterns such as processing hole positions that interfere with them are arranged on the marking layer surface. In addition, for each signal layer surface and each power supply ground layer surface, the wiring is decomposed at each corner, a branch point, and an intersection with a component terminal (via hole), and the segment data 30 in which the polygonal conductor shape 4 is decomposed into its sides is created. Individual component numbers 32 are assigned to the segment data 30 of the components separated for each layer surface, and the individual component numbers 32 are specified and recorded for the via holes, and the board outlines on each side are also common to them. And a part number 32 is recorded. Hereinafter, the board outline and the via hole are also referred to as components.

FIGS. 4A and 4B are diagrams showing the data structure of the generated unit data 30. FIG. 4 shows the data structure of the unit data 30 of the component terminal 1 and the via hole 3. FIG.
FIG. 4A shows the data structure of the piece data 30 of the wiring 2. In the piece data 30 of the component terminal or the via hole, the same part number 32 is recorded in all pieces of the terminal relating to one component, and the same component number 32 is recorded in the piece data 30 of all the layers of one via hole 3. . Also, the shape number 3 of the shape data 35 for recording the shape of the segment
6 is recorded. The piece data 30 of the wiring 2 connected to the component terminal 1 or the via hole 3 has the same position number as that of the component terminal 1 or the via hole 3 to which the end of the wiring is connected or the end of the other wiring 2 with respect to the position of the wiring. 33 is recorded, and the shape number 36 of the figure representing the width of the wiring is recorded. In the position data 34, a coordinate value and a layer surface number 38 are recorded, and a part number 32 associated with the position number 33 is recorded. Each shape of the figure is described and stored in the shape data 35 of the figure shown in FIG. 4C, and the shape number 36 of the figure, the upper and lower widths, the left and right widths, and the 45 The width and the width of the right-downward oblique 45 degrees are stored, and the figure is represented by an octagon. In addition, polygonal conductor shape 4
Is the segment data 30 of a line segment in which each piece of the polygonal conductor shape 4 is recorded as a fixed shape, and is stored in the data structure of FIG.

Here, the initial layout of the printed wiring board is such that adjacent wirings 2, component terminals 1 and via holes 3
The present invention is applicable even when the gap between the polygonal conductor shapes 4 is arranged without observing the minimum gap of the design rule. This is because a gap smaller than the minimum dimension of the design rule is corrected in the course of processing by the graphic layout compression apparatus 1000 as described later.

Next, the partition room arranging means 112 separates a part of the horizontal component constraint graph data 60 and a part of the vertical component constraint graph data 60 of the component outer shape for each layer surface on which the component is mounted, as follows. create. First, as shown in FIG. 6B, the component outer shape is divided into right and left (up and down) rectangle groups by vertical (horizontal) partition lines. If this horizontal partition line abuts on a rectangle, the position is taken as the end of the horizontal partition line, and the rectangular group is further divided into right and left by a vertical partition line extending vertically from that end, and the vertical partition line is also rectangular or existing. If it collides with a partition line, set that position as the end of the vertical partition line, set a horizontal partition line extending from the end to the left and right, and keep the partition line until all other partition lines that hit the ends of all the partition lines exist Create Of the areas (partition rooms) divided by these partition lines, a partition room in which a plurality of component outlines are stored is further added with a partition line until one or more component outlines are stored in one partition room. Continue partitioning.

Next, the rectangle surrounding the component outer shape and the horizontal (vertical) partition line are recorded as nodes, and the gap between the rectangle and the horizontal (vertical) partition line is defined as the graph length in the vertical (horizontal) direction. The component constraint graph data 60 in the direction is created by aggregating all layer surfaces. On the other hand, for the component outlines in which the minimum rectangles surrounding the component outline overlap each other, both the horizontal component constraint graph data 60 and the vertical component constraint graph data 60 connecting the component outlines are created, and the graph length is set to 0.

Next, the partition room arranging means 112 corrects the existing partition line so as not to intersect with the via hole for each inner layer surface on which component mounting is not performed and for each layer surface. The terminal group is divided by a second partition line that divides the terminal group into different partition rooms (FIG. 7). Here, when there is a free end of the wiring, the end point is treated in the same manner as the via hole. (1) Here, the component terminals of the same component need not be divided into different partition rooms. It also allows the partition line to cross the component terminals. In addition, for a partition room that does not store component terminals and via holes, an empty terminal is defined at a position between the wirings stored in the partition room, and the empty terminal is recorded as a substitute for the actual terminal. (2) The number of partitions on either side is 2
The long partition line is divided on the way by a vertical partition line as follows. This prevents the number of terminal constraint graphs created for each combination of component terminals and via holes on both sides of the partition line from becoming too large later.

Next, the constraint graph creating means 103 generates, for each layer surface, for each partition room, the segment data 3 stored in the partition room.
0 is read out in the order of the coordinate values in the direction perpendicular to the compaction direction (first direction) (second direction), and the unit number 31 is read out.
Is calculated in the first direction, and as shown in FIG. 5A, constraint graph data 40 in the first direction that records the unit numbers 31 in that order is created. This constraint graph data 40 is
When the unit number 31 of the same signal name 37 is adjacent, the constraint graph data 40 is created between the unit number 31 and the adjacent unit number 31 having a different signal name ahead of the unit number 31. That is, processing is performed as if a partner having the same signal name is transparent and does not exist. As a result, the same signal name 37
Are connected in parallel from the unit numbers 31 of the other signal names 37. Then, the constraint graph data 40 is
Is calculated, and the order of the constraint graph numbers 41 is recorded in the constraint graph order data 42 in the first direction shown in FIG. 5B.

Similarly, in the second direction, constraint graph data 40 in the second direction and constraint graph rank data 42 in the second direction are created (step S100).

Next, in step S104, the part constraint graph data 60 whose data structure is shown in FIG. 5D is created by aggregating the terminal constraint graph data 50 of all layers in the following procedure.

That is, as shown in FIG. 9, for each layer surface, a component terminal (first terminal) housed in a partition room (first room) on the right side of a vertical partition line for partitioning a partition room, and the vertical partition. A wire bundle between component terminals (second terminals) housed in a partition room (second room) on the left side of the line is extracted from the X-direction constraint graph ranking data 42, and the sum of the width of the wiring and a required gap is extracted. Is calculated, and if the width of the wiring bundle is smaller than the gap in the X direction between the two component terminals, the process proceeds to step S106.
Otherwise (1) If the gap in the Y direction between the two component terminals is greater than or equal to the wiring bundle width therebetween, step S1061
If the gap in the Y direction between the two component terminals is less than the width of the wiring bundle therebetween, the process proceeds to step S105.
(The above is Step S104).

In step S105, first, the terminal constraint graph creating means 104 stores the X-direction terminal constraint graph data 50 (FIG. 5) for recording the first terminal and the second terminal for each layer surface.
(C) is created, and the width of the wiring bundle between the two terminals and the wiring piece sandwiched between the terminals are recorded.
Record 2 as 0. Then, X-direction part constraint graph data 60 for recording both part numbers 32 is created, and the X-direction part relative movement limit length 62 is recorded as 0 in the data, and
The X-direction terminal constraint graph number 51 is recorded. If the part constraint graph data 60 for recording the same part number 32 has already been created in the processing of another layer surface or the processing of the same layer surface, the recorded X-direction part relative movement limit length 62 is set to a smaller value. , And the record of the X-direction terminal constraint graph number 51 of the neck of the part movement is updated. By updating the component relative movement limit length 62 in this manner, the component constraint graph data 60 in which the component relative movement limit lengths of the terminal constraint graph data 50 on all layers are aggregated is created.

Next, the Y-direction part constraint graph data 60 for both parts is created in the following procedure. That is, as shown in FIG. 10, in the terminal constraint graph data 50 in which the second terminal and the first terminal are nodes at both ends of the graph, the terminal at both ends is freely bent obliquely in the Y direction. Is calculated as follows, and the Y-direction terminal constraint graph data 50 for recording this as the Y-direction component relative movement limit length 62 is calculated. Furthermore, the component constraint graph data 60 to be recorded is created by quantizing the value of this calculation to a multiple of the interval of the component placement grid and recording it. First, assume the following. Let the relative coordinates of the upper and lower component terminals be (X, Y). The sum of the X-direction radii of both terminals and the sum of the wiring bundle widths is represented by Bx, and the sum of the Y-direction radii of both terminals and the sum of the wiring bundle widths are represented by By.
Further, considering the coordinate axis (X + Y) in a direction between the direction of the coordinate axis X and the direction of the coordinate axis Y, the sum of the increment of the coordinate (X + Y) of the radius of the shadow projected in the direction of the coordinate axis (X + Y) and the wiring bundle The sum of the width multiplied by the square root of 2 is represented as Bz. Similarly, considering the coordinate axis (Y-X) in a direction between the direction of the coordinate axis Y and the direction opposite to the coordinate axis X, the coordinate axis (Y-
X) coordinates at the position of the radius of the shadow projected in the direction (Y−
The sum of the increment of X), the wiring bundle width, and the value obtained by multiplying the wiring bundle width by the square root of 2 is represented as Bw. At this time, the maximum moving distance M
Is calculated as follows, and that value is set as the component relative movement limit length 62. -Bx <X <BxU <= ByU <= Bz-XU <= Bw + XM = Y-U This relative movement limit length 62 (M) is recorded in the Y-direction terminal constraint graph data 50, and is quantized. The converted value is recorded in the component constraint graph data 60. If there is existing Y-direction component constraint graph data 60 for recording both components, the Y-direction component relative movement limit length 62 to be recorded is updated to the shortest value. Next, the process proceeds to step S107 (step S105).

In step S106, if the wiring bundle width between the component terminals on both sides is smaller than the gap in the X direction between both component terminals,
X-direction terminal constraint graph data 5 for recording both component terminals
0 is created, and the difference between the gap and the width of the wiring bundle is recorded as the component relative movement limit length 62 in the X direction. The upper limit of the component relative movement limit length 62 is the pitch between both component terminals. Then, X-direction part constraint graph data 6 for recording both parts
0 is created (or updated), the component relative movement limit length 62 in the X direction is quantized to a multiple of the interval of the component placement grid, recorded (or updated to the minimum value), and the terminal constraint graph number as the bottleneck Record 51. Next, step S
The process proceeds to 107 (step S106).

The above step S106 can be performed as follows. That is, the partition line between the two component terminals is a kind of component, and the first terminal and the vertical partition line are nodes at both ends.
The directional terminal restriction graph data 50 is created, and further, the X-direction terminal restriction graph data 50 having the vertical partition line and the second terminal as nodes at both ends is created. The X-direction terminal restriction graph data 50 is preferentially created from a graph having a small inclination from the X-axis. The width of the wiring bundle between the first terminal and the second terminal is recorded in the X-direction terminal restriction graph data 50 having both ends of the first terminal and the vertical partition line, and the wiring element sandwiched therebetween. Is recorded, and the component relative movement limit length 62 is recorded.
Further, a value obtained by quantizing the component relative movement limit length 62 is recorded in the X-direction component constraint graph data 60.

The X having both ends of the first terminal and the vertical partition line has already been set.
If the directional terminal constraint graph data 50 is created, the terminal constraint graph data 50 having both ends of the second terminal and the vertical partition line is updated, and the wiring width between the first terminal and the second terminal is updated. The wiring bundle width obtained as a result of subtracting the wiring bundle width of the wiring between the first terminal and the vertical partition line already defined from is recorded. Similarly, terminal constraint graph data 50 and component constraint graph data 60 for the second terminal and vertical partition line are created,
Calculate and record the wiring bundle width of the wiring between them and the wiring element number 32 sandwiched therebetween.

The advantages of this processing are exhibited in the following cases. That is, in other processes, when the number of component terminals on both sides of one partition line is large, the number of terminal constraint graphs due to the combination of the component terminals on both sides of the partition line is a number obtained by multiplying the number of component terminals on both sides. However, this process has the advantage that the number of terminal constraint graphs can be reduced to about the number of component terminals.

In step S1061, as shown in FIG. 11 (a), if the wiring bundle width between the component terminals on both sides exceeds the gap in the X direction between the two component terminals but is smaller than the gap in the Y direction, The following processing is performed. (1) As shown in FIG. 11A, when there is a vertical partition line in the Y direction that separates the component terminals on both sides to the left and right in the X direction, FIG.
As shown in (b), a horizontal partition line in the X direction which is orthogonal to the vertical partition line and vertically separates both component terminals is set, and the vertical partition line is divided and changed. (2) Further, terminal constraint graph data 50 in the Y direction for recording both component terminals is created, and the difference between the gap and the wiring bundle width is represented by Y.
It is recorded as the component relative movement limit length 62 in the direction. The upper limit of the component relative movement limit length 62 is the pitch between both component terminals. Then, component constraint graph data 60 in the Y direction for recording both components is created (or updated), and a value obtained by quantizing the component relative movement limit length 62 in the Y direction is recorded (or updated to a minimum value). The terminal constraint graph number 51
Record

Next, the operation proceeds to step S107 (step S1061).

In step S107, the X coordinate and the Y coordinate are replaced, and steps S104 to S1061 are performed in the same manner to calculate the terminal constraint graph data 50 in the Y direction to create the component constraint graph data 60 in the Y direction. Next, the process proceeds to step S108 (step S107).

Next, in step S108, the component compaction means 107 moves the component with the shortest path length while calculating the shortest path in the X direction as described below. That is, the shortest path calculation means 105 connects to the existing shortest path nodes (parts) of the part constraint graph data 60 that are connected in the X direction from the left end on all layers of the substrate to the X direction from the left end on all layers of the substrate by the Dijkstra compaction method. The component constraint graph data 60 in the X direction is extracted. Then, the component relative movement limit length 62 of the component constraint graph data 60 is added to the shortest path length of the node.
Is calculated, and the part constraint graph data 60 that minimizes this value is selected. The value is set as the shortest path length of the node (part) at the other end of the part constraint graph data 60. Add data 60 to the shortest path. Further, the components connected by the component constraint graph data 60 are moved to the left in the X direction by the shortest path length and arranged.

This processing is repeated to calculate the shortest path of the component constraint graph data 60 in the X direction, and compact the component layout in the X direction. At this time, in the initial layout of the printed wiring board, even if the gap between the adjacent wiring 2, the component terminal 1, the via hole 3, and the polygonal conductor shape 4 is arranged without observing the minimum gap of the design rule, the gap is set to It is corrected in the above processing. (Step S10
8).

Next, step S110 repeats the processing of step S108 in the Y direction in the same manner.
The shortest path of the component constraint graph data 60 in the Y direction is calculated, and the component layout is compacted in the Y direction as shown in FIG. 8B (step S110).

Next, in step S111, the wiring compaction means 108 reads out the unit number 31 (processed wiring unit) of the wiring recorded by the wiring compaction unit 108 in order from the Y-direction terminal constraint graph data 50 on the lower side in the Y-direction. , All the Y-direction terminal constraint graph data 50 that record the wiring unit number 31
Is extracted. Then, the extracted terminal constraint graph data 5
Calculate a wiring bundle width 52 on the component terminal side at both ends of the zero by combining the required wiring with the other wiring existing therebetween and the radius of the width of the processing wiring element, and calculate the width of the component terminal in the vertical and horizontal oblique directions in eight directions. Then, the shape data 35 of the octagonal wiring suppression region, which is obtained by adding the wiring bundle width 52 to the data, is created. However, if there is a wire whose position has already been determined, make the wire a fixed shape and fold the wires of the wire bundle freely around the fixed shape in 45-degree units to wrap the fixed shape with the wire bundle. The shape data 35 of the shape wiring suppression area is created. Then, the shape number 36 is recorded in the wiring limit position data 80 showing the data structure in FIG. 4 (e), the processed wiring unit number 31 is recorded, the unit terminal unit number 31 is recorded, and the component terminal is recorded. Is recorded.

Next, the re-wiring means 109 re-routes the processed wiring to a regular shape including an oblique wiring shape outside the wiring suppression area of the wiring limit position data 80 (step S11).
1).

Next, the operation of the graphic layout compression apparatus 1000 will be described with reference to a specific example.

FIGS. 6 to 8 show a graphic layout compression apparatus 1.
FIG. 6A is a plan view showing a pattern for explaining the operation of the printed wiring board 000, and FIG. 6A shows an initial layout of a printed wiring board to be processed by the graphic layout compression apparatus 1000.

The partition room arranging means 112 creates a partition room for storing individual component outlines as shown in FIG. 6B, and further creates a partition room for storing individual via holes as shown in FIG.

Next, the terminal constraint graph creating means 104
Terminal constraint graph data 50 and component constraint graph data 60
Create At this time, it is detected that the width of the wiring bundle between the component terminals G and E in FIG. 7 is wider than the gap in the Y direction between both component terminals and smaller than the gap in the X direction, as shown in FIG. like,
A vertical dividing line is created in the Y direction that separates both component terminals in the X direction, and the dividing line is changed (from step S104 to step S104).
107).

Next, the component compaction means 107
By moving and arranging the components in the X direction and the Y direction with the shortest path length in each direction, the component layout is compacted to the component arrangement shown in FIG. 8B (steps S108 to S110).

Next, the wiring compaction means 108
Based on the Y-direction terminal constraint graph data 50 sandwiching the wiring, the octagonal wiring limit position data 80 is formed by storing the wiring along the shape of the lower component terminal in the Y-direction and storing the same.

Next, as shown in FIG. 8B, the rewiring means 109 shapes the wiring into a shape including diagonal wiring and rewiring, and stores the resulting layout data 20 (step S111).

Thus, the component terminals are arranged in the partition room,
Wiring is compacted by using a data structure that records and captures the wiring bundle width in the terminal constraint graph data 50 of the component terminals on both sides of the partition line to compact the parts and wiring, and to perform wiring in any form including diagonal wiring. it can.

The reason why compaction can be performed in this way is that the distance that the component terminals housed in the adjacent partitions can move in the X and Y directions via the wiring bundle therebetween is recorded in the component constraint graph data 60, Constraint graph data 6
This is for compacting the component layout by 0.

Next, a graphic layout compressing apparatus 2000 according to a second embodiment of the present invention will be described in detail with reference to the drawings.

The graphic layout compression apparatus 2000 is, like the graphic layout compression apparatus 1000, operated by a computer 100 (central processing unit; processor; data processing apparatus) operated by program control, and a display unit (CRT display or liquid crystal display, etc.) 101. And an operation unit (keyboard and mouse or tablet or the like) 102. However, the graphic layout compression apparatus 1
The internal configuration of the computer 100 differs between 000 and 2.

As shown in FIG. 12, in the graphic layout compressing apparatus 2000, the computer 100 includes a wiring alignment means 121 in addition to the means of the graphic layout compressing apparatus 1000.
, A wiring update unit 122 and a wiring alignment component compaction unit 123.

The wiring aligning means 121 takes out the wiring surrounded by the blind lane of the wiring in the direction perpendicular to the compaction direction, out of the dead lane, and eliminates the dead lane of the wiring by processing such as closing the blind lane. The shortest path is calculated, and the via holes having different shortest path lengths on each layer surface (and wirings connected to the via holes) are changed in the order of compaction with the nearby wiring bundle, thereby eliminating the mismatch of the shortest path lengths.

The wiring updating means 122 changes the order of the specified wiring and the specified component terminal (via hole) and wiring.

Wiring alignment component compaction means 123
Compacts the layout of components by spacing the components and compacting the layout of the components by changing the order of the wirings and moving them in the compaction direction.

Next, the overall operation of the graphic layout compression apparatus 2000 will be described in detail with reference to the flowcharts of FIGS. FIGS. 16 to 22 are plan views showing pictures for explaining the operation of the graphic layout compression apparatus 2000. FIG.

First, the layout data conversion means 111
Corresponds to step S10 of the graphic layout compression apparatus 1000.
Based on 0, the segment data 30 is created from the layout data 20. Next, the substrate area is divided into partition rooms. Next, constraint graph data 40 and constraint graph order data 42 are created for each partition room (step S100).

Next, by the processing of steps S104 to S107 of the graphic layout compression apparatus 1000, a terminal for recording a component terminal (or an empty terminal) housed in a partition room and a component terminal adjacent via a partition line as a node. The constraint graph data 50 is created, and component constraint graph data 60 for recording both parts as nodes is created (steps S104 to S107).

Next, in step S202, the wiring alignment means 121 reads out the wiring pieces for each layer surface and performs the following processing. First, a group of wiring pieces to be connected is extracted, and FIG.
As in the case of the shape (a) from the via hole A to the via hole C via the via hole C, the projection of the wiring element group in the direction (second direction) perpendicular to the compaction direction is the connection point ( An overlapping bag shape having a length equal to or greater than a predetermined depth (for example, 2.54 mm) is extracted from the via hole C in the drawing. The processing from step S203 to step S206 is performed for each of the bag shapes. On the other hand, if the processing relating to the bag shape has been completed for all the wiring pieces, step S2
07 (Step S202).

Next, in step S203, when the bag shape is detected, the wiring penetrating into the bag shape is taken out of the bag shape, and the wiring route change for eliminating the bag shape is performed as follows.

With respect to the via holes connected from the bottom of the bag shape to both sides of the bag shape, all wirings connected to the via holes are extracted, and the wirings other than the wiring forming the bag shape are connected to the other layer surfaces. 1 is the standard direction (Fig. 1
A via hole (via hole B in FIG. 14A) connected to only the portion indicated by the dotted line in FIG. 4A is extracted.

The via hole position is moved along the wiring connected to the via hole for each layer surface from the via hole to a position intersecting the other side (second side) of the bag shape in the compaction direction (first direction). . When the first direction in which the via hole is moved is separated before the leading end of the interconnect to be connected, the interconnect is extended and inserted into the gap between the adjacent interconnects in the second direction to advance the via hole. Here, the route of the wiring to be inserted is set such that the width of the occupied area of the wiring (and via hole) to be inserted is 0, and the route is searched under a loose design rule that allows the wiring to be inserted as long as it does not come into contact with the surrounding elements. The constraint graph data 40 between the wiring segment and the segment adjacent in the second direction is created.

At this time, if there is a segment which becomes an obstacle in the first direction beyond the via hole, the wiring route is moved in the second direction within a predetermined distance (for example, 10 mm). Search for wiring routes that displace and avoid obstacles.

Further, at the time of this route search, the shape data 35 of the wiring fault connecting the component terminals is recorded at a gap position where no further wiring can be inserted between the component terminals of the same component. This route search may not be performed beyond the shape data 35 of the wiring fault.

When the via hole reaches the position of the second side in the first direction, the via hole B shown in FIG.
, The via hole is connected to the second side, and the wiring from the bag-shaped position to which the via hole was initially connected to the bottom of the bag shape (connecting via hole B and via hole C in FIG. 16A) Removed). As shown in FIG. 16B, when the moved via hole B and the other via hole A are arranged on the entire surface of all layers and no elements are interposed therebetween and are arranged in the vicinity, both via holes are combined into one. Constraint graph data 40 is created between adjacent segments in the first direction and the second direction at the position of the new via hole, and constraint graph order data 4
Create and update 2.

The position obtained in this way in the via hole by moving the via hole and individually obtained in all the layer surfaces is a temporary position, and is used only for defining the constraint graph with the surrounding wiring on each layer surface of the via hole. The specific coordinate position of the via hole is determined after creating a terminal constraint graph that defines the relationship between the surrounding via hole and the component terminal as follows. Next, step S
The process proceeds to 203 (step S203).

Next, in step S204, the partition room arranging means 112 separates the via holes or the component terminals by the partition lines from the via holes moved and inserted in step S203 again by the processing of steps S100 to S107. Is updated, the terminal constraint graph data 50 and the component constraint graph data 60 of the partition room whose wiring has been changed are updated, the terminal constraint graph number 51 is recorded in the inspection array, and then the processing in steps S503 to S510 is performed. And then the process proceeds to step S206 (step S204).

Step S503 performs the following processing.

If the component relative movement limit length 62 of the terminal constraint graph data 50 is negative, it means that the interval between the components needs to be further increased. Can not be spread. The cause of the negative component relative movement limit length 62 is one newly inserted wire between the component terminals. Therefore, the step S503 extracts the terminal constraint graph data 50 in which the component relative movement limit length 62 becomes a negative value from the terminal constraint graph data 50 recorded in the inspection array, and determines whether the component terminals at both ends belong to the same component. Or to detect.

If the component terminals at both ends belong to the same component, the wiring updating means 122 uses the wiring between the terminal constraint graph data 50 and the wiring (first wiring) adjacent to the component terminal on the layer surface. The order of the component terminals is changed by the following processing from step S504 to step S510. This process is repeated for all test arrays (step S503).

[0130] Step S504 is the wiring update means 122.
Is the component terminal D of the terminal constraint graph and the first
Process wiring. As shown in FIG. 17A, when there is no wiring (second wiring) connected to the component terminal D, the process proceeds to step S505. In the case where the second wiring exists and the portion where the first wiring and the second wiring are parallel to each other, and both the first wiring and the second wiring are connected to each other and have no branch, the process proceeds to step S507. move on. If there is a branch, a design rule violation is recorded (step S504).

The step S505 is for the wiring updating means 122.
However, as shown in FIG. 17 (b), a wiring (first wiring) is formed as a detour wiring that attaches to the component terminal, and a neighboring element number 31 of the wiring in the X direction or the Y direction is adjacent to the element number 31 of the wiring. The constraint graph data 40 with the unit number 31 is updated and created. Next, the process proceeds to step S510 (step S50).
5).

Step S 507 is the wiring updating means 122
However, like the component terminal A in FIG. 18A, the wiring (second wiring) on the layer surface where the first wiring exists is connected to the component terminal whose relative position is exchanged with the first wiring. If the second
In the range in which the wiring runs parallel to the first wiring in the X direction, the first wiring and the second wiring are connected one by one without any branching, and the wiring end of the end of the region where the wirings are parallel to each other is formed. When connecting to component terminals, the first wiring and the second wiring are exchanged as follows.

That is, the constraint graph data 40 (first constraint graph) that records the segment number 31 of the first wiring is extracted, and this constraint graph number 41 is assigned from the designated component terminal A to the end of the first wiring. Are arranged in order up to the component terminal (component terminal B) and stored in the first wiring arrangement. Also, the unit number 31 of the terminal component terminal (component terminal B) to which the first wiring is connected is stored.

The constraint graph data 40 (second constraint graph) in which the unit number 31 of the second wiring is recorded.
And the constraint graph numbers 41 are sequentially stored in the second wiring array from the designated component terminal (component terminal A) at the tip of the second wiring to the component terminal (component terminal C) at the end of the second wiring. Also, the unit number 31 of the component terminal (component terminal C) at the position number 33 at the end of the second wiring is stored. Next, step S5
It proceeds to 08 (step S507).

[0135] Step S508 is for the wiring updating means 122.
However, the first wiring arrangement in this order is compared with the second wiring arrangement, and the first constraint graph number 41 and the last constraint graph number 41 of the second wiring arrangement are both recorded in the first wiring arrangement. In this case, the first wiring covers the start and end of the second wiring. In that case, the order of the first wiring and the second wiring is changed as follows. If this condition is not satisfied, the process proceeds to step S509.

That is, of the second wiring, the segment data 30 of the second wiring directly connected to the component terminals at both ends is deleted, and the wiring shape is separated from the component terminals. Then, portions adjacent to both component terminals in the Y direction are deleted from the first wiring to divide the wiring shape. Then, a wiring shape for connecting the first wiring portion between the two component terminals to the second both component terminals is created. In addition, a wiring shape is created that connects the first wiring portions remaining on both sides outside the two component terminals with the second wiring portions remaining between the two component terminals. Then, the unit number 31 of those wirings and the unit number 3 around the adjacent unit number in the X or Y direction are set.
1 is updated and created. next,
The process proceeds to step S510 (step S508).

In step S509, the wiring update means 122
However, the first constraint graph number 41 of the second wiring
In the case where the last constraint graph number 41 of the first wiring array is recorded in the second wiring array, as shown in FIG. In this case, the wirings run partially in parallel. In this case, the order of the second wiring and the first wiring is changed as shown in FIG.

That is, the portion of the second wiring coupled to the designated component terminal that is coupled to the designated component terminal is removed, and the wiring shape is divided. Also, the portion of the first wiring connected to the terminal component terminal on the right side is removed to cut the wiring shape. Then, portions adjacent to both component terminals in the Y direction are removed from the first and second wirings to divide the wiring shape. Then, the left end of the first wiring portion between the two component terminals is connected to the designated component terminal, and the right end is connected to the second wiring divided to the right of the terminal component terminal.
The left end of the second wiring portion divided between the two component terminals is connected to the first wiring portion divided to the left of the designated component terminal, and the right end of the second wiring portion is connected to the terminal component terminal. Connect to Then, the constraint graph data 40 of the unit numbers 31 of those wirings and the unit numbers 31 adjacent thereto in the X direction or the Y direction is updated and created. Next, the process proceeds to step S510 (step S509).

Thus, the wiring updating means 122 changes the order of the first wiring and the second wiring.

Step S510 is repeated at step S10.
From step 4 to step S107, the terminal constraint graph data 50 and the component constraint graph data 60 of the partition room whose wiring has been changed are updated, and the terminal constraint graph numbers are additionally recorded in the inspection array. Then, the process returns to step S503 (step S510).

Next, in step S206, the shortest path is determined by the Dijkstra method in the X or Y direction for the part constraint graph data 60 in each of the X and Y directions, and the path of the part which has already become a node of the shortest path is determined. Detects again the case where the shortest path having a value smaller than the already obtained shortest path length is obtained, determines the existing shortest path from the node to return to the node again as a negative loop, and determines that the design rule is violated. This design rule violation occurs when a via hole and a wire larger than the gap are accommodated between component terminals of the same component.

If this negative loop is detected, the data changed to eliminate the bag shape is returned to the previous one, otherwise, the data returns to step S202 and the next bag shape is released. Processing. If all the bag shapes have been processed, the process proceeds to the next step S207 (step S206).

From this step S203 to step S20
In the process (6), the wiring alignment means 121 eliminates the bag shape of the wiring, so that the wiring advances in the second direction from any wiring gap along the wiring gap, and reaches the substrate end without returning. A gap could be formed. Thereby, the failure rate of the subsequent route search can be reduced.

Next, in step S207, the processing from step S202 to step S206 is performed in the direction perpendicular to the previous direction, and the shape of the bag in the vertical direction is eliminated (step S207).

In step S208, the wiring alignment means 121
However, like the via hole A in FIG. 19A, there is a wiring (third wiring: a solid line connecting A and B in FIG. 19A) connected to the via hole, and the via hole has a third wiring. Wirings running in a direction perpendicular to the standard running direction (third direction: horizontal direction in FIG. 19A) of the wiring on the layer surface (fourth wiring:
The case where the connection is made only with the wiring (the wiring shown by the dotted line descending from A in FIG. 19A) is extracted.

A route is searched in the third direction from the end (third terminal: via hole B in FIG. 19A) on the opposite side from the via hole of the third wiring, and the route crosses the fourth wiring. Move the via hole to the desired position.

In other words, the path of the third wiring is defined by a loose design rule in which the width of the occupied area of the segment to be inserted is set to 0 from the third terminal, and the segment can be inserted unless it comes into contact with the surrounding segments. A gap between wirings adjacent in a direction perpendicular to the third direction (fourth direction) is formed below, and a third wiring is formed in a third direction toward the fourth wiring in a wiring AB shown in FIG. The constraint graph data 40 between the wiring segment and the segment adjacent in the fourth direction is created.

The via hole at the other end of the third wiring is
As in the via hole A of FIG. 19B, the position of the via hole is moved for each layer surface along with the fourth wiring for each layer surface connected to the via hole, and a new route for the third wiring is formed in the fourth direction. Move to the intersection. 4th move via hole
If the direction is ahead of the leading end of the fourth wiring to be connected, a piece of the wiring is extended and inserted between adjacent wirings in the third direction to advance the via hole. Here, the route of the wiring to be inserted is set such that the width of the occupied area of the wiring (and via hole) to be inserted is 0, and the route is searched under a loose design rule that allows the wiring to be inserted as long as it does not come into contact with the surrounding elements. The constraint graph data 40 between the segment of the fourth wiring and the segment adjacent in the third direction is created.

At this time, if there is a segment that becomes an obstacle in the third direction ahead of the via hole, it is displaced in the third direction within a predetermined distance (for example, 10 mm). Search for wiring routes that avoid obstacles.

When the via hole reaches the position where the third wiring is inserted, the via hole is connected to the third wiring.

Then, the terminal constraint graph data 50 connected to the position of the new via hole is recalculated. Further, the terminal constraint graph data 50 having the newly inserted third wiring and fourth wiring between them is updated. Here, the updated terminal constraint graph number 51 is recorded in the inspection array, and step S20
4 and the processing of steps S503 to S510 are performed to read out the component relative movement limit length 62 of the terminal constraint graph data 50 recorded in the inspection array. If the value becomes negative and the component terminals at both ends belong to the same component, Out of the wiring from the gap, and update the shortest path.

Next, the process returns to the beginning of step S208, and proceeds to the process of matching wiring connected to another via hole.
If all the wires have been processed, the process proceeds to step S209 (step S208).

In this step S208, the wiring alignment means 121 causes the wiring route to follow the standard traveling direction of each layer surface,
The wiring is aligned by moving the via hole to the intersection position.

Next, in step S209, the wiring alignment means 121 determines that the wirings connected to the wirings are all in the same running direction on all the layers, such as via holes connected to the three horizontal lines from the top in FIG. Extract the via hole that is only wiring, move the via hole in the direction of the wiring, make the wiring that violates the traveling direction of the layer surface approach so as to shorten it, and if you approach until the via hole touches, both via holes If the wiring connected to the integrated via hole exists only in one layer, the structure shown in FIG.
The via hole is also erased like 0. Thus, the bottleneck of compaction is reduced (step S209).

Next, in step S210, the wiring alignment component compaction means 123 sets the compaction direction to Y.
The following steps S211 to S213 are performed, and then the compaction direction is set to the X direction, the wire pressing direction is set to the X direction, and the same steps are repeated. Proceed to.

Next, in step S211, the wiring arrangement component compaction means 123 calculates the shortest path in the component constraint graph in the compaction direction, and records the shortest path component numbers 32 in the component arrangement order array in order. The component number 32 recorded first in the component arrangement sequence is the component number 32 representing the board end in the compaction direction. Next, the process proceeds to step S212 (step S211).

Next, in step S212, the component numbers 32 are read in order from the component arrangement order arrangement, the processed flag is stored in the processing memory of the segment of all terminals of the component, and the component number 32 is stored in the component wiring order arrangement. And the part number 32 is used as a basic part (the part number 32 is stored in the basic part memory).

Next, the unit number 31 of the wiring recorded in the wiring reservation array (to be defined later) is read out, and both the component terminals electrically connected to both ends of the wiring unit number 31 have been processed. When the segment number 31 connected to the wiring segment number 31 by the constraint graph data 40 in the compaction direction has been processed (the processed flag is stored in the processing memory of the segment number 31), the following processing is performed. Do.

That is, the wiring unit number 31 is stored in the wiring order array, deleted from the recording of the wiring reservation array, the processed flag is stored in the processing memory of the wiring unit number 31, and the wiring unit number is stored. In a constraint graph data 40, a wire segment number 31 connected in the reverse direction of compaction is stored in a wire reservation array.

Next, returning to the beginning of step S212, the next component number 32 in the component arrangement order is processed. After processing all data in the component arrangement order array, step S213 is performed.
(Step S212).

Next, in step S213, the component number 32 and the wiring element number 31 are read out in the order recorded in the wiring order array, and the following processing is performed.

When the part number 32 is read, the position at which the part or via hole is moved by the shortest path length is calculated. In the following, FIG. 21A based on the shortest path length
The procedure will be described with reference to the component layout at the component moving position.

When the wire segment number 31 is read,
A path is searched for from the both ends of the wiring piece to the other end of each of the wiring pieces in the direction perpendicular to the compaction direction.
At this time, a route that is brought along with the element on the compaction direction side in the wiring gap is searched for as follows.

The terminal constraint graph 50 connected in the direction intersecting the wiring route is read from the component terminals belonging to the partition room through which the wiring route passes, and the difference between the shortest path lengths of the component terminals at both ends is set as the approach distance, Is calculated by subtracting the approaching distances at both ends from the interval of, and further subtracting the width of the wiring bundle therebetween as a wiring margin value. Here, if the wiring pushing direction is set to the compaction direction,
If any of the component terminals at both ends have not been processed,
It is calculated that the wiring margin value is sufficient. Also, when there is a previous route of the wiring between the terminal constraint graph data 50, it is calculated that the wiring margin is sufficient. In other cases, if the wiring margin value is less than the sum of the wiring width to be inserted and the required gap, a route is searched for using a rule that does not pass through the route. Then, from each end of the wiring to the other end, the wiring path that proceeds in the vertical direction in the compaction direction intersects with the other end at the coordinate position in the vertical direction in the compaction direction, and the path from both ends intersects Until this is done, a route is created in which a small gap that does not come into contact with a segment with a different signal name on the wiring pushing direction side is opened.

In this route search, if the route reaches a position where the route cannot proceed further, and if the position reaches a dead end that is blocked by fragments in both the compaction direction and the reverse direction, the end of the dead end is reached. Reverse the wiring route along the adjacent wiring on the opposite side of the wiring pushing direction, return to the entrance of the dead-end, find the position outside the dead-end (the opposite side of the wiring pushing direction) from the entrance, and determine the wiring route from that position. Is searched for a route that returns until it crosses, and a wiring route is searched for beyond that. However, if the wiring pushing direction is a free direction, a wiring path is provided outside the dead end in an arbitrary direction from the dead end.

In this way, the wiring route from both ends of the wiring is searched, and the intersection is calculated. Then, a path connecting the both ends to the intersection is defined as a wiring path connecting the both ends, and the wiring element number 31 is added to the terminal constraint graph data 50 connected to the component terminal of the partition room passing through the wiring path to update the data. I do. Also, the wiring element number 31 is deleted from the terminal constraint graph data 50 in which the previous path of the wiring element is recorded, and the data is updated. However, if a new wiring route cannot be obtained, the old wiring route is maintained. Next, the minimum value of the component relative movement limit length 62 of the terminal constraint graph data 50 of both ends of the updated terminal constraint graph data 50 is calculated, quantized, and the component relative movement limit recorded in the component constraint graph data 60. The length 62 is updated, and the shortest path of the updated component constraint graph data 60 is calculated and updated.

An example in which the wiring connecting the component terminals C and D in FIG. 21A is changed in the compaction direction as shown in FIG. 21B will be described. In this way, the order of the component terminals or other wiring is changed so that the wiring is moved as far as possible in the wiring pushing direction, so that the space below the component E in FIG. To create an interval. By doing so, the component relative movement distance of the component constraint graph data 60 changes, and the shortest path changes, and as shown in FIG.
The component layout with the shortest path length changes. Thus, the component layout can be compacted into a smaller area.

When the above processing has been completed, the next wiring element number 31 is read from the wiring order array, and the above processing is repeated. In this way, the process returns to step S210 after processing the wiring segment numbers 31 in all the wiring order arrangements (step S213).

Next, through the processing of steps S108 to S110 of the graphic layout compression apparatus 1000, the component and the via hole are moved in the X direction and the Y direction by the shortest path length, respectively, and the component layout is compacted in the vertical and horizontal directions (step S108). To S110).

Next, in step S111 of the graphic layout compression apparatus 1000, the wiring compaction means 10
8 creates and stores octagonal wiring limit position data 80 in which the wiring is brought together and bent along the shape of the component terminal at one end of the terminal constraint graph data 50 sandwiching the wiring. Then, the re-wiring means 109 re-wires into a free shape having an oblique line in a space within the limit position (step S111).

In this manner, the graphic layout compression apparatus 2000 can reduce the bottleneck of compaction and compact the layout into a smaller area.

The reason for this is that the wiring arrangement means 121 for eliminating the bag shape of the wiring eliminates the dead ends, thereby facilitating the search for the wiring path between the wiring gaps, and rectifying the flow of the wiring to reduce the number of via holes. This is because the wiring order is changed by the wiring alignment component compaction means 123 in a direction to reduce the wiring between components so that the component layout can be compacted in a smaller area.

A graphic layout compression apparatus 3000 according to a third embodiment of the present invention will be described in detail with reference to the drawings. FIG. 23 shows a graphic layout compression apparatus 3000.
It has a configuration of

The graphic layout compression device 3000 includes a part moving means 210 between partitions. After the component compaction unit 107 calculates the shortest path of the part constraint graph data 60, the part moving unit 210 between partition rooms improves the shortest path by moving the via hole of the shortest path in a direction to eliminate the shortest path, thereby improving the shortest path. Enables compaction of parts to the area.

Next, the overall operation of the graphic layout compression device 3000 will be described in detail with reference to FIGS. FIG. 24 is a flowchart showing the operation of the graphic layout compression device 3000. FIGS. 25 to 28 are plan views showing pictures for explaining the operation of the graphic layout compression apparatus 3000. FIG. 25A is an initial layout of a printed wiring board to be processed by the graphic layout compression apparatus 3000. FIG. 26C shows the layout of the final result.

First, the layout data conversion means 111
Corresponds to step S10 of the graphic layout compression apparatus 1000.
At 0, the segment data 30 is created from the layout data 20. Next, the substrate area is divided into partition rooms. Next, constraint graph data 40 and constraint graph order data 42 are created for each partition room (step S100).

Next, by the processing of steps S104 to S107 of the graphic layout compression apparatus 1000, a terminal for recording a component terminal (or an empty terminal) housed in a partition room and a component terminal adjacent via a partition line as a node. The constraint graph data 50 is created, and component constraint graph data 60 for recording both parts as nodes is created (steps S104 to S107).

Next, in steps S108 to S110 of the graphic layout compression apparatus 1000, the shortest path calculation means 1
05 and the component compaction means 107 to compact the component layout in the X and Y directions (steps S108 to S110).

Next, in step S302, the inter-partition-parts moving means 210 performs the following processing on the partition room (first partition room) in the compaction direction (Y direction) (the order closer to the compaction destination). .

That is, if there is no component terminal (first component terminal) to be stored in the first partition room (to store an empty terminal), steps S303 and S30 are performed.
Perform step 6. On the other hand, if the first component terminal exists,
If the position protrudes from the outer shape of the board, step S30
Steps S305 and S306 are performed if there is a first component terminal in steps S306 and S306. Thus, the partition rooms are sequentially processed.

That is, in step S303, the component is moved to the gap between the components, and in step S304, the component that protrudes from the board outline is moved into the board outline, and the components are sequentially compacted according to the board outline.

After all partition rooms have been processed, the flow advances to step S111 (step S302).

Step S303 is performed when the first partition does not store the component terminals. This is shown in FIG.
This is the case where the partition room between the parts 1 and 3 in (a) is the first partition room.

That is, a component terminal or a via hole (second component terminal: component 2 in FIG. 25A) adjacent to the first partition room on the opposite side in the compaction direction (Y direction) is extracted and the first partition is formed. Move to the room and perform step S306. Here, if the adjacent partition room also does not store the component terminals, the component terminals stored in the adjacent partition room are moved earlier.

Using the result of step S306, a position at which each component is moved in the shortest path is calculated. If the position does not satisfy the required outer shape of the board in the second direction, the second position is determined.
Undo the movement of the component terminals. Thereafter, the process returns to the original process (step S303).

Step S304 is performed when the first component terminal is not housed in the outer shape of the board. This is shown in FIG.
This is the case of the component 5 in (b).

That is, the first component terminal (the component 5 in FIG. 25) is not yet processed in the board outline (part 2).
Partition room: the partition room between the component 5 and the component 8 in FIG. 25 (b)), and the component terminal (second component terminal) already stored in the second partition room is moved and inserted. A partition line is created between one component terminal, the second partition room is divided into two, step S306 is performed, and the process returns to the original processing (step S304).

Step S305 is performed when the first component terminal housed in the first partition is housed in the outer shape of the board. This is the case of part 1 in FIG.

That is, a value is calculated by subtracting the width of the wiring bundle between the first terminal and the gap between the component terminals of the partition room adjacent to the first partition room and the first component terminal. (For example, sum of via hole diameter and required gap)
When there is the above gap, the component terminals or via holes (second component terminals) housed in the adjacent partition room on the opposite side in the compaction direction (Y direction) are inserted into the first partition room. Then, the first partition room is divided into two by moving and creating a partition line between the first component terminal and the second component terminal, and then step S306 is performed. Next, the process returns to the original process (step S305).

Next, in step S306, the terminal constraint graph data 50 is updated and created as follows, and the component constraint graph data 60 is updated. This processing will be described with reference to FIGS. (1) Component terminals (intermediate terminals: FIG. 2) stored in the partition room to which the component terminals (first moving terminals: A in FIG. 27) move.
7 is extracted.

The terminal constraint graph data 50 connecting the first moving terminal and the intermediate terminal is read, and the nodes at the other end (from F to K and B) are not adjacent to the original partition room of the first moving terminal. 27, the terminals H, I, and J are not adjacent to the partition room of the terminal A, but are not adjacent to the partition room of the terminal A in FIG. Adjacent. In this case, terminal constraint graph data 5 connecting the first moving terminal (A) and the terminals (H, I, J) as nodes.
0, a terminal constraint graph 50 connecting the first moving terminal (A) and the intermediate terminal (L), and a terminal bundle graph connecting the intermediate terminal (L) and the terminals (H, I, J). The wiring bundle added to the wiring bundle sandwiching the data 50 is recorded. However, if the wiring connected to the first moving terminal (A) is included in the wiring bundle, it is excluded from the recording. On the other hand, as for the component terminals (C, D, E) which are adjacent to the original partition room of the first moving terminal (A) but not adjacent to the destination partition room, the component terminals and the first terminal are not connected to the first partition terminal. The terminal constraint graph data 50 connecting the moving terminal (A) is deleted. Other component terminals (F, G, K, B) and first moving terminal (A)
Are also redefined and updated for the terminal constraint graph data 50 connecting. (2) An empty terminal (terminal M in FIG. 28) is set in the original partition room of the first moving terminal (A), and among the component terminals connected to the first moving terminal (A), the empty terminal (M) is a component terminal (K, B, C, D, E, F,
G) is created, and the wire bundle with the previous first moving terminal is recorded as the wire bundle with the empty terminal. Further, terminal constraint graph data 50 connecting the empty terminal and the first moving terminal after the movement is created, and it is recorded that there is no wiring sandwiched therebetween. Here, when there is a wiring connected to the first moving terminal and it is stretched by the movement of the first moving terminal, the wiring is connected from the first moving terminal to one end of the empty terminal from the other end. It is added to and recorded in the terminal constraint graph data 50 connected to the component terminal.

Next, the part relative movement limit length 62 of the new or updated terminal constraint graph data 50 is calculated in steps S104 to S107 of the graphic layout compression apparatus 1000, and the part constraint graph data 50 is calculated.
To update. Then, the updated terminal constraint graph number 51
Is recorded in the test sequence. After the above processing is applied to all new or updated terminal constraint graph data 50, the processing of steps S503 to S510 of the graphic layout compression apparatus 2000 is performed, and a bundle of wires sandwiched between the terminal constraint graphs at both ends of the same component is processed. If there is a violation of the design criteria of the width of, it will be resolved. Next, the shortest path of the component constraint graph data 60 in the X direction and the Y direction is calculated and compacted in the procedure of steps S210 and S108 to S110 of the graphic layout compression apparatus 2000. Thereafter, the process returns to the original process (step S306).

Next, in step S111 of the graphic layout compression apparatus 1000, the wiring compaction means 10
8 creates and stores octagonal wiring limit position data 80 in which the wiring is brought together and bent along the shape of the component terminal at one end of the terminal constraint graph data 50 sandwiching the wiring. Then, the rewiring means 109 rewires the wiring into a free shape having oblique lines in a space within the limit position (step S111).

Thus, the graphic layout compression apparatus 300
In the case of 0, the component layout and the wiring can be compactly packed by arranging the components sequentially in the outer shape of the board and moving the wiring together with the components.

The reason is that the part moving means 21 between partition rooms
Numeral 0 is for grasping the filling state by the component terminals of the partition room in the outer shape of the board, and moving and filling the components into the empty partition room.

A graphic layout compression apparatus 4000 according to a fourth embodiment of the present invention will be described in detail with reference to the drawings. Like the graphic layout compression apparatus 1000, the graphic layout compression apparatus 4000 includes a computer 100 that operates under program control, a display unit 101,
An operation unit 102 is provided.

The configuration of the computer 100 is as shown in FIG. 29. In addition to the configuration of the graphic layout compression apparatus 1000, the computer 100 is provided with a component movement designation means 301. The component movement designation means 301 sets the component movement target vector data 63 (FIG. 31B) for designating the movement direction of each component toward an arbitrary position in the layout.

Next, the overall operation of the graphic layout compression apparatus 4000 will be described in detail with reference to FIG. 30, FIG. 31, and FIG. FIG. 30 is a diagram layout compression apparatus 40.
It is a flowchart showing operation | movement of 00. FIG. 31 and FIG.
FIG. 2 is a plan view showing a picture for explaining the processing operation of the graphic layout compression apparatus 4000. FIG. 31A shows an initial layout of a printed wiring board to be processed by the graphic layout compression apparatus 4000 and a movement target graph of parts, and FIG. 32C shows a graphic layout compression apparatus 4000.
FIG. 7 is a plan view showing a layout in a state in which the processing of FIG.

First, the layout data conversion means 111
Corresponds to step S10 of the graphic layout compression apparatus 1000.
Based on 0, the segment data 30 is created from the layout data 20. Next, the substrate area is divided into partition rooms (FIG. 3).
1 (a)). Next, the terminal constraint graph creation means 104
The constraint graph data 40 and the constraint graph rank data 42 are created for each partition room (step S100).

[0200] Next, the component movement specifying means 301 assigns each of the components to the movement target position 63 at an arbitrary position in the layout.
The component movement target vector data 63 toward 0 and the compaction center position are set as follows. The operation command input means 110 receives an instruction from the operator by a mouse operation or a keyboard operation on the screen, and for each component, a vector extending from its initial position to the movement target position 630 is represented by component movement target vector data. 63 (FIG. 31B). Then, the compaction center position data is moved while displaying the X-axis coordinate axis and the Y-direction coordinate axis on the display screen, and the origin thereof is stored as the compaction center position data 64. Also, a newly inserted wiring is specified. This data input can also be performed by the operation command input means 110 reading a group of the component movement target vector data 63 of a plurality of components through a communication line or reading from a magnetic recording medium.

The graphic layout compression apparatus 4000 adds a fixed point named a movement target starting point as a node of the part constraint graph data 60. And the Y direction (downward) of the part
Of the component movement target vector data 63, that is, the movement target distance is defined as the length of the graph, the movement target starting point is defined as the first node, and the component number 32 in the Y direction is defined as the second node. I do. Similarly, component constraint graph data 60 in the X direction is created with the target length of the component in the X direction (left direction) as the length of the graph. By creating the part constraint graph data 60 connecting the movement target start point and the part in this way, the part can be moved in accordance with the movement target vector data 63.

Also, figure layout compression apparatus 4000
The component layout can be converged by setting the component movement target vector data 63 in which the moving directions of all the components are directed to an arbitrary layout position, or the components can be set collectively in the opposite direction. It is also possible to collectively set the component movement target vector data 63 so as to enlarge the layout (step S301).

Next, by the processing of steps S104 to S107 of the graphic layout compression apparatus 1000, a terminal for recording a component terminal (or an empty terminal) housed in a partition room and a component terminal adjacent via a partition line as a node. The constraint graph data 50 is created, and component constraint graph data 60 for recording both parts as nodes is created (steps S104 to S107).

Next, in step S408, the component compaction means 107 uses the component constraint graph data 60 connecting the starting point of the movement target and the component created earlier and the component constraint graph data 60 connecting the components, as shown in FIG. As shown in (a), compaction center position data 64 is provided for each component terminal.
The part on the right side of the X coordinate moves leftward in the X direction, and the part on the left side moves rightward in the X direction.

That is, the component is moved with the shortest path length while calculating the shortest path in the X direction toward the X coordinate of the compaction center position data 64. This is because the shortest path calculation means 105 calculates the existing shortest path of the part constraint graph data 60 in the X direction from the part of the partition room overlapping the X coordinate of the compaction center position data 64 and the movement target starting point by the compaction method by the Dijkstra method. The X-direction component constraint graph data 60 connected to the node (component terminal) is extracted. Then, a value obtained by adding the component relative movement limit length 62 of the component constraint graph data 60 to the shortest path length of the connected component is calculated, and the component constraint graph data 60 that minimizes this value is selected. Parts constraint graph data 60
And the component constraint graph data 60 is added to the shortest path. Further, the components connected by the component constraint graph data 60 are moved and arranged in the X direction with the shortest path length.

This process is repeated to calculate the shortest path of the component constraint graph data 60 in the X direction, and compact the component layout in the X direction (step S408).

Next, the processing in step S408 is
Similarly, the process is repeated in the Y direction, the shortest path of the component constraint graph data 60 in the Y direction is calculated, and the component layout is compacted in the Y direction as shown in FIG. 32B (step S410).

Next, in step S111 of the graphic layout compression apparatus 1000, the wiring compaction means 10
8 creates and stores octagonal wiring limit position data 80 in which the wiring is brought together and bent along the shape of the component terminal at one end of the terminal constraint graph data 50 sandwiching the wiring. The rewiring means 109 rewires the wiring into a free shape having diagonal lines as shown in FIG. 32C in a space within the limit position (step S11).
1).

The above processing is performed by the component movement specifying means 3
01 sets the component movement target vector data 63, and then compacts the layout by the operation of the graphic layout compression device 2000 or 3, so that components and wiring can be compacted more closely toward the center of the component layout.

Thus, the graphic layout compression device 4
000 can perform a compaction process that can move a part toward a predetermined target position and can expand or reduce the part layout.

The reason is that the graphic layout compression device 40
00, the part movement specifying means 301 for specifying the movement direction of the part by the movement target creates the part constraint graph data 60 that connects the part with the starting point of the movement and has the movement target vector data 63 as a graph length; This is for adding the component constraint graph data 60 of the components to each other and compacting the component layout with them.

Also, figure layout compression apparatus 4000
The operation command input unit 110 inputs the compaction center position data 64 of the component layout, and the component compaction unit 107 moves toward the compaction center position.
Can compact the component layout.

[0213]

The present invention has the following effects.

First, the component terminals are arranged in the partition room, and the wiring is compacted by using a data structure in which the wiring bundle width is recorded and taken into the terminal constraint graph data of the component terminals on both sides of the partition line. In addition, compaction can be performed in any form including diagonal wiring. The reason is that the distance that the component terminals housed in the adjacent partitions can move in the X and Y directions via the wiring bundle therebetween is recorded in the component constraint graph data, and based on this component constraint graph data, This is because the component layout is compacted.

Second, it is possible to reduce the bottleneck of compaction and compact the layout to a smaller area. This is because (a) by eliminating the bag shape of the wiring, that is, by eliminating the dead end, it is easy to search for the wiring path between the wiring gaps, (b) the flow of the wiring is rectified, and the via hole is reduced; This is because the order of the wirings is changed in the direction of reducing the number of wirings between them so that the component layout can be compacted into a smaller area (a), (b) and (c).

Third, by arranging the components sequentially in the outer shape of the board and moving the wiring together with the components, the component layout and the wiring can be compactly packed.
The reason for this is that the inter-partition-parts moving means grasps the state of filling by the component terminals of the partition within the outer shape of the board, and moves and fills the parts into an empty partition.

Fourth, components and wiring can be compacted more closely toward the center of the component layout. This is because the layout is compacted after the component movement specifying means sets the component movement target vector data.

Fifth, a component can be moved to a predetermined target position, and compaction processing capable of either expanding or reducing the component layout can be performed.
The reason is that the component movement specifying means for specifying the moving direction of the component by the moving target connects the component to the starting point of the movement, creates the part constraint graph data having the moving target vector data as the graph length, and This is for compacting the component layout with the component constraint graph data of the components. Also, the operation command input means inputs compaction center position data of the component layout, and the component compaction means compacts the component layout toward the compaction center position.

The present invention has been described based on the embodiments. However, the present invention is not limited to the embodiments, and it is understood that changes and improvements can be made within the ordinary knowledge of those skilled in the art. Of course.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a graphic layout compression apparatus 1000 according to a first embodiment of the present invention.

FIG. 2 is a flowchart of an operation of the graphic layout compression apparatus 1000.

FIG. 3 is a diagram showing the structure of various data of the present invention.

FIG. 4 is a diagram showing the structure of various data of the present invention.

FIG. 5 is a diagram showing the structure of various data of the present invention.

FIG. 6 is a plan view showing a picture for explaining the operation of the graphic layout compression apparatus 1000;

FIG. 7 is a plan view showing a picture for explaining the operation of the graphic layout compression apparatus 1000;

FIG. 8 is a plan view showing a picture for explaining the operation of the graphic layout compression apparatus 1000;

FIG. 9 is a diagram showing a procedure for creating a terminal constraint graph 50.

FIG. 10 is a diagram illustrating the concept of a component relative movement limit length 62;

FIG. 11 is a diagram showing a procedure for changing a partition line.

FIG. 12 is a functional block diagram of a graphic layout compression apparatus 2000 according to a second embodiment of the present invention.

FIG. 13 is a flowchart of the operation of the graphic layout compression apparatus 2000.

FIG. 14 is a flowchart of the operation of the graphic layout compression apparatus 2000.

FIG. 15 is a flowchart of the operation of the graphic layout compression apparatus 2000.

FIG. 16 is a plan view showing a picture for explaining the operation of the graphic layout compression apparatus 2000;

FIG. 17 is a plan view showing a picture for explaining the operation of the graphic layout compression apparatus 2000;

FIG. 18 is a plan view showing a picture for explaining the operation of the graphic layout compression apparatus 2000.

FIG. 19 is a plan view showing a picture for explaining the operation of the graphic layout compression apparatus 2000.

FIG. 20 is a plan view showing a picture for explaining the operation of the graphic layout compression apparatus 2000;

21 is a plan view showing a picture for explaining the operation of the graphic layout compression apparatus 2000. FIG.

FIG. 22 is a plan view showing a picture for explaining the operation of the graphic layout compression apparatus 2000.

FIG. 23 is a functional block diagram of a graphic layout compression device 3000 according to a third embodiment of the present invention.

FIG. 24 is a flowchart of the operation of the graphic layout compression device 3000;

FIG. 25 is a plan view showing a picture for explaining the operation of the graphic layout compression device 3000;

FIG. 26 is a plan view showing a picture for explaining the operation of the graphic layout compression apparatus 3000;

FIG. 27 is a plan view showing a picture for explaining the operation of the graphic layout compression device 3000;

FIG. 28 is a plan view showing a picture for explaining the operation of the graphic layout compression apparatus 3000;

FIG. 29 is a functional block diagram of a graphic layout compression device 4000 according to the fourth embodiment of the present invention.

FIG. 30 is a flowchart showing the operation of the graphic layout compression device 4000.

FIG. 31 is a plan view showing a picture for explaining the processing operation of the graphic layout compression apparatus 4000;

FIG. 32 is a plan view showing a picture for explaining the processing operation of the graphic layout compression apparatus 4000;

FIG. 33 is a diagram layout compression apparatus 5000 of the second conventional example.
3 is a functional block diagram of FIG.

FIG. 34 is a diagram for explaining before and after layout modification by the graphic layout compression device 5000;

FIG. 35 is a diagram for explaining a change in a wiring passage route according to Conventional Example 5.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 component terminal 2 wiring 3 via hole 4 polygonal conductor shape 20 layout data 30 element data 40 constraint graph data 50 terminal constraint graph data 60 component constraint graph data 80 wiring limit position data 100 computer 101 display unit 102 operation unit 103 constraint graph creation Means 104 Terminal constraint graph creation means 105 Shortest path calculation means 107 Parts compaction means 108 Wiring compaction means 109 Rewiring means 110 Operation command input means 111 Layout data conversion means 112 Partition room arrangement means 121 Wiring alignment means 122 Wiring update means 123 Wiring alignment Parts compaction means 210 Parts movement means between partitions 301 Parts movement designation means 1000, 2000, 3000, 4000, 5000
Graphic layout compression device

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-10-242285 (JP, A) JP-A-11-274310 (JP, A) Hideo Kikuchi, “Diagonal wiring compaction method for printed boards and its evaluation” , Information Processing Society of Japan Research Report (98-DA-88), May 22, 1998, Vol. 98, No. 43, p. 29-34 (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 17/50

Claims (21)

(57) [Claims] 1. A wiring, a component terminal, and a terminal arranged in a two-dimensional space.
A figure layout compression apparatus that reads layout data including at least one layer pattern having a via hole and a polygonal conductor shape and components of a printed wiring board or cells of a semiconductor, and compacts the layout. Means for creating constraint graph data having, as nodes at both ends, a combination of components terminals, via holes, semiconductor cells, wirings, and components that are adjacent to each other, and component terminals, via holes, semiconductors for each layer from the layout data. Calculate the position of a vertical or horizontal partition line that divides an area in which cells and component outlines are arranged, and have a terminal having component terminals and via holes stored in regions adjacent to both sides of the partition line as nodes at both ends. Means for calculating constraint graph data; and Calculate the component relative movement limit length at which the node at one end of the terminal constraint graph data can approach the node at the other end in the compaction direction via a wiring bundle in which the width of the wiring sandwiched between the nodes and the necessary gap are added. Means for recording the part relative movement limit length, and means for creating part constraint graph data obtained by combining terminal constraint graph data of all layers with the part number as a node, and within the part relative movement limit length. A component compaction means for moving a component terminal and a via hole at a node at the other end; and, for layout data output by the component compaction means, shaping the wiring into a wiring shape including a diagonal wiring at an interval between the component and the via hole. A graphic layout compression apparatus, comprising: a rewiring means for rewiring. 2. The graphic layout compression apparatus according to claim 1, wherein said means for creating said constraint graph data comprises:
A graphic layout compression apparatus characterized in that segments having the same signal name are treated as non-interfering with each other, and constraint graph data of a relationship connected in parallel is created from segments having other signal names. 3. The graphic layout compression apparatus according to claim 1, further comprising: displaying a via hole, a component terminal, or a semiconductor cell, and moving the individual component and the via hole in the movement target direction and the movement target distance. A graphic layout compression apparatus comprising: component movement specifying means for specifying target vector data; and means for creating component constraint graph data for recording a part number and a fixed point as nodes. 4. The graphic layout compression apparatus according to claim 1, further comprising means for designating a center position of compaction of the layout and compacting the layout toward the center position. Figure layout compression device. 5. The graphic layout compression apparatus according to claim 1, further comprising, when compacting the component layout, the component terminals in the compaction direction in order from the component in the compaction direction in accordance with the outer shape of the board. A compacting device for moving the part terminal to a side area and moving the part terminal to an empty area beyond the partition line. 6. The graphic layout compression apparatus according to claim 1, further comprising: changing a rank in a compaction direction with respect to a component terminal, a via hole, or another wire, and moving the wire in the compaction direction. And a means for compacting the component layout thereafter. 7. The graphic layout compression apparatus according to claim 1, further comprising extracting a dead path of the wiring, and changing the order of the wiring and the via hole from the order of the component terminal, the via hole, and the other wiring. A figure layout compression apparatus, comprising: means for moving and searching for a route for eliminating a dead alley. 8. A wiring, a component terminal, and a component terminal arranged in a two-dimensional space.
The layout data including at least one layer pattern having a via hole and a polygonal conductor shape, and components of a printed wiring board or cells of a semiconductor are read into an information processing apparatus,
In the graphic layout compression method for compacting the layout, constraint graph data having a combination of component terminals, via holes, semiconductor cells, wirings, and components adjacent to each other as component nodes at both ends is created from layout data for each layer surface. From the layout data, for each layer surface, calculate the position of a vertical or horizontal partition line that divides an area where component terminals, via holes, semiconductor cells, and component outlines are arranged, and calculates the positions of both sides of the partition line. Calculating the terminal constraint graph data having component terminals and via holes housed in adjacent regions as nodes at both ends; adding a width and a necessary gap of the wiring sandwiched between the nodes at both ends of the terminal constraint graph data; The node at one end of the terminal constraint graph data can approach the node at the other end in the compaction direction via the wiring bundle Calculating a component relative movement limit length; recording the component relative movement limit length; and creating component constraint graph data that combines terminal constraint graph data of all layers with the component number as a node. A component compaction stage that moves the component terminal and via hole of the other end node within the component relative movement limit length, and a rewiring that reshapes and reroutes the wiring into a wiring shape that includes diagonal wiring in the space between the component and the via hole And a method of compressing a graphic layout. 9. The graphic layout compression method according to claim 8, wherein the step of creating the constraint graph data comprises:
A graphic layout compression method characterized in that segments having the same signal name are treated as non-interfering with each other, and constraint graph data of a relation of being connected in parallel from segments having other signal names is created. 10. The graphic layout compression method according to claim 8, further comprising: displaying a via hole, a component terminal, or a semiconductor cell, and moving a target direction and a target distance of each component and the via hole. A graphic layout compression method, comprising: a part movement specifying step of specifying target vector data; and a step of creating part constraint graph data for recording a part number and a fixed point as nodes. 11. The graphic layout compression method according to claim 8, further comprising a step of designating a center position of compaction of the layout and compacting the layout toward the center position. Figure layout compression method. 12. The graphic layout compression method according to claim 8, further comprising, when compacting the component layout, the component terminals in the compaction direction in order from the component in the compaction direction in accordance with the outer shape of the board. And compressing the part layout while moving the part terminal to an empty area beyond the partition line. 13. The graphic layout compression method according to claim 8, further comprising: changing the order of the component terminals, via holes, or other wirings in the compaction direction, and moving the wirings in the compaction direction. , And then compacting the component layout. 14. The graphic layout compression method according to claim 8, further comprising extracting a dead path of the wiring, and changing the order of the wiring and the via hole from the component terminal, the via hole and the other wiring. A method for compressing a graphic layout, comprising a step of moving and searching for a route for eliminating a dead alley. 15. An information processing apparatus sends layout data including at least one layer pattern having wiring, component terminals, via holes, and a polygonal conductor shape arranged in a two-dimensional space, and components of a printed wiring board or cells of a semiconductor. On a machine-readable recording medium on which a graphic layout compression program for reading and outputting layout data subjected to compaction processing is recorded, component terminals, via holes, semiconductor cells, wiring, and component outlines are determined for each layer surface from layout data. A process of creating constraint graph data having a combination of adjacent ones as nodes at both ends, and a vertical or vertical direction for dividing an area where component terminals, via holes, semiconductor cells, and component outlines are arranged for each layer surface from the layout data. Calculate the position of the horizontal divider line, adjacent to both sides of the divider line Processing for calculating terminal constraint graph data having component terminals and via holes as nodes at both ends accommodated in a region to be stored, and the width and necessary gap of the wiring sandwiched between the nodes at both ends of the terminal constraint graph data are added. Through a wiring bundle, a process of calculating a relative movement limit length of a part at which a node at one end of the terminal constraint graph data can approach a node at the other end in a compaction direction, and recording the component relative movement limit length, and A process of creating component constraint graph data that combines terminal constraint graph data of all layers, with a node as a node, and a component compaction process of moving a component terminal and a via hole of the node at the other end within the component relative movement limit length. And causing the information processing apparatus to perform a rewiring process of shaping and rewiring the wiring into a wiring shape including a diagonal wiring in an interval between the component and the via hole. Recording medium for recording a form layout compressor. 16. The recording medium according to claim 15, wherein the processing for creating the constraint graph data treats segments having the same signal name as non-interfering with each other and connects in parallel from segments having other signal names. A recording medium on which a graphic layout compression program is recorded, which causes an information processing apparatus to create constraint graph data of a relation to be performed. 17. The recording medium according to claim 15, further comprising displaying a via hole, a component terminal or a semiconductor cell, and a moving target vector of a moving target direction and a moving target distance of each component and the via hole. A recording medium storing a graphic layout compression program for causing an information processing apparatus to execute a component movement designation process for designating data and a process for creating component constraint graph data for recording a component number and a fixed point as nodes. . 18. The recording medium according to claim 15, further comprising: designating a center position of compaction of the layout, and causing the information processing apparatus to execute a process of compacting the layout toward the center position. A recording medium having recorded thereon a graphic layout compression program. 19. The recording medium according to claim 15, further comprising: when compacting the component layout, the component terminals are arranged in the compaction direction side in order from the component in the compaction direction according to the board outline. A recording medium on which a graphic layout compression program is recorded, wherein the information processing apparatus executes a compaction process while moving the component terminal to a vacant area beyond the partition line. 20. The recording medium according to claim 15, further comprising: changing the order of the component terminals, via holes, or other wirings in the compaction direction, and searching for a route that brings the wirings in the compaction direction. A recording medium storing a graphic layout compression program for causing an information processing apparatus to execute a process of performing a component layout and a process of compacting a component layout thereafter. 21. The recording medium according to claim 15, further comprising extracting a dead path of the wiring, and moving the wiring and the via hole in the order of the component terminal, the via hole, and the other wiring. And a recording medium storing a graphic layout compression program for causing an information processing apparatus to execute a process of searching for a route for eliminating a dead alley.