JP3191393B2 - Interlayer connection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interlayer connection system in a computer-aided apparatus for producing a printed wiring pattern having a plurality of layers.

In an electric circuit composed of a printed wiring pattern composed of a plurality of layers (hereinafter, simply referred to as a pattern), the same signal line such as a power supply line or a ground wire extends over a plurality of layers. In the case of wiring by connecting the patterns on each layer by connecting paths called vias,
In recent years, as the speed of a signal transmitted on a pattern increases, it is required to provide as many vias as possible to connect patterns on different layers with as low impedance as possible.

[0003]

2. Description of the Related Art FIG. 9 is a diagram showing an example of a conventional computer assisted device, and FIG. 10 is a diagram showing an example of a via forming process in FIG.

[0004] The computer assisted device 10 shown in FIG. 9 includes a processing device 1, a main storage device 2, an external storage device 3, a keyboard 4, a mouse 5, an input / output control device 6, a display 7, a display control device 8 and a bus 9. In the external storage device 3, a database (DB) including various data related to an electric circuit designed by the computer assisted device 10 is stored.

Here, the data stored in the database (DB) is
The first layer (E) shown in FIG. ₁)
Airline (E₁₁) And the second layer (E) shown in FIG._Two)
GEO line (E_{twenty one}) And (E)_{twenty two}) And connect
It is assumed that a via (V) is generated.

[0006] In such a case, the designer must use the database (D
B) from the first layer data (D ₁ ) and the second layer data (D ₂ )
DOO extracts, 10 first layer (E ₁₎ and the second layer (E ₂₎ and overlapping the display on the display 7 as shown (c), the earthed lines and (E ₁₁₎ (E ₂₁ ) and the overlapping area (E
₁₂₁ ) and vias (V ₁ ) to (V ₄ ) in an overlapping area (E ₁₂₂ ) where the earth lines (E ₁₁ ) and (E ₂₂ ) overlap.
The product was based on a predetermined criterion (e.g., on a grid of a predetermined interval), and registers via data corresponding to the generated vias (V ₁₎ to (V ₄₎ (d ₁₎ to (d _4).

Further, a third layer having signal lines (F ₃₁ ) and (F ₃₂ ) between the first layer (E ₁ ) and the second layer (E ₂ ) as shown in FIG. When (E ₃ ) intervenes,
The generated vias (V ₁ ) to (V ₄ ) and the third layer data (D ₃ ) are overlapped and displayed on the display 7, and the vias (V ₁ ) to (V ₄ ) and the signal line (F ₃₁ ) are displayed. ) And (F ₃₂ )
Is observed if it exceeds a predetermined design standard. For example, a via (V ₄ ) is connected to the signal line (F).
When it detects a in contact with the ₃₁₎ and (F _32),
Determines that not be provided via (V _4), and ultimately decided to provide only vias to remove the vias is determined that the gap defect (V ₄₎ (V ₁₎ to (V ₃₎ Then, via data (d ₁ ) to (d ₃ ) corresponding to vias (V ₁ ) to (V ₃ ) are registered in a database (DB).

[0008]

As is apparent from the above description, in the conventional computer-aided apparatus 10, when the designer determines the setting position of the via, the related layers are overlapped on the display 7. Since all the operations are performed manually, such as displaying the position and displaying the via setting position candidates, and further confirming the gaps with other signal lines on the display 7, a great deal of labor is required for the designer. At the same time, there is a problem that the purpose of lowering the connection impedance as much as possible is overlooked due to oversight of the overlapping region or oversight of the normal via setting position due to forgetting to select a via setting position candidate.

An object of the present invention is to connect patterns on different layers with as many connection paths as possible.

[0010]

FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, reference numeral 100 denotes a computer-aided apparatus to which the present invention is applied.

Reference numeral 101 denotes an overlapping area determining means provided in the computer-aided apparatus 100 according to the present invention (claims 1 to 3). Reference numeral 102 denotes a connection position selection unit provided in the computer-aided apparatus 100 according to the present invention (claims 1 to 3).

Reference numeral 103 denotes a connection position correcting means provided in the computer-aided apparatus 100 according to the present invention (claim 2). Reference numeral 104 denotes a connection position correcting unit provided in the computer-aided apparatus 100 according to the present invention (claim 3).

[0013]

The overlapping area determining means 101 obtains an overlapping area (A) where a specified pattern (P) on a plurality of specified layers overlaps.

The connection position selecting means 102 sets a connection position (V) for connecting each pattern (P) between different layers in the overlapping area (A) determined by the overlapping area determining means 101.
Is selected according to a predetermined reference.

Therefore, according to the present invention (claim 1), it is possible to provide as many connection paths for connecting the specified patterns on a plurality of layers as possible, and the specified patterns can be formed. Connection is possible with as low an impedance as possible.

The connection position correction means 103 calculates a gap between the connection path (V) selected by the connection position selection means 102 and the existing pattern (P ₂ ), and determines a connection where the gap is smaller than a predetermined reference. The setting position of the connection path (V) is determined except for the path (V).

The connection position correction means 104 calculates a gap between the connection path (V) selected by the connection position selection means 102 and the existing pattern (P ₂ ), and sets the gap to be smaller than a predetermined reference. When the position (V) is detected, an attempt is made to modify the existing pattern (P ₂ ) so that the gap exceeds the reference, and the connection path (V) is removed except for the set position (V) where the modification was not successful. ) Set position.

Therefore, according to the present invention (claim 2), it is possible to provide as many connection paths as possible to connect designated patterns on a plurality of layers, and existing patterns exist. In this case as well, it is possible to eliminate the connection path in which the gap with the existing pattern is smaller than the reference value, and according to the present invention (claim 3), the specified patterns on a plurality of layers are connected to each other. Connection paths can be provided as abundantly as possible, and even if there are existing patterns, connection paths with gaps between existing patterns below the reference value should be corrected as much as possible. Thus, the specified patterns can be connected with as low impedance as possible.

[0019]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram illustrating a computer-aided apparatus according to an embodiment of the present invention. FIG. 3 is a diagram illustrating an example of a pattern data extraction process in FIG. 2, and FIG. FIG. 5 is a diagram showing a via generation process according to an embodiment of the present invention (claim 2), and FIG. 6 is a diagram showing a via generation process according to an embodiment of the present invention (claim 3). FIG. 7 is a diagram showing a via generation process according to an embodiment of the present invention (claim 2), and FIG. 8 is a diagram showing an example of a gap defective via relief process in FIG. In addition,
The same reference numerals indicate the same objects throughout the drawings.

FIG. 2 shows a computer assisting apparatus 10 as the computer assisting apparatus 100 in FIG. 1, and a pattern data extracting unit 11 and an overlapping area determining unit 12 as an overlapping area determining means 101 in FIG. And the connection position selecting means 102 in FIG.
A via position selection unit 13 is provided in the processing apparatus 1 as
Further, a gap failure processing unit 14 is provided in the processing apparatus 1 as the connection position correction unit 103 in FIG. 1, and further, the gap failure processing unit 15 is provided as the connection position correction unit 104 in FIG.
Are provided in the processing apparatus 1.

In FIG. 2 as well, the database (DB) in the external storage device 3 has three layers of data (D ₁ ) constituting a certain electric circuit, similarly to the database (DB) illustrated in FIG. ), (D ₂ ) and (D ₃ ) are stored, and the designer has the ground wire (E ₁₁ ) and the second layer (E ₁₁ ) on the first layer (E ₁ ) of the electric circuit. ₂ ) A via (V) is provided to connect the upper earth lines (E ₂₁ ) and (E ₂₂ ).

When the same signal line (for example, ground wire) is wired over a plurality of layers, the pattern of each layer (for example, ground wire (E ₁₁ ), (E ₂₁ ) and (E ₂₁ )) ₂₂ )] is collectively called a net.

First, one embodiment of the present invention (claim 2) will be described with reference to FIG. 2 to FIG. 5 and FIG. First, the designer specifies, for example, via the keyboard 4 from the keyboard 4, net data for specifying a net for which a via is to be generated, and via settable position data for specifying a settable position of a via (step S31 in FIG. 3).

This time, as the net data, the ground lines in the first layer (E ₁ ) and the second layer (E ₂ ) are designated, and as the via settable position data, the data shown in FIG. It is assumed that the coordinates of the intersection points of the grid formed at predetermined intervals are specified.

When the net data and the via settable position data are designated, the processing device 1 activates the pattern data extracting unit 11. Activated pattern data extraction unit 11
Is a database (D) stored in the external storage device 3.
B), the target electric circuit [three layers (E ₁ ),
(E ₂ ) and (E ₃ )], data on a printed circuit board, data on components used in an electric circuit,
Data relating to connection information constituting an electric circuit, for example, data used as a reference when designing an electric circuit such as an allowable gap size between signal lines, and data (D ₁ ) to (D ₃ ) such as designed patterns are obtained. Read (step S32).

Next, the pattern data extraction unit 11 determines the designated net [first layer (E ₁ ) and second layer (E ₂ ) from the data (D ₁ ) to (D ₃ ) read from the database (DB). pattern data belonging to the earthed line] _{a) (D 11), (D} 21) and (after extraction of D ₂₂₎ (step S33), the pattern data (D ₁₁₎ is the first layer, the pattern data (D ₂₁ ) And (D ₂₂ ) are classified into the second layer and each layer (step S34).

When the processing by the pattern data extraction unit 11 is completed, the processing apparatus 1 subsequently proceeds to the overlap area determination unit 1
Start 2 The overlap area determination unit 12 first sets a numerical value (= 2, that is, the first layer and the second layer) to the number of built-in processing target layers (H), and then sets the processing target layer number (h) and the Initially set the pattern numbers (j) (h =
1, j = 1) (FIG. 4, steps S41 and S4).
2) Select the pattern data (D _hj ) (= D ₁₁ ) (step S43).

Next, the overlap area determination unit 12 selects the pattern data (D _ik ) after the initial setting of the opponent layer number (i) and the pattern number (k) on the opponent layer (steps S44 to S46). ).

The other layer number (i) is selected from the layer next to the layer number (h) to be processed. The other layer number (i) = the layer number (h) +1 (= 2) to be processed. Initial setting is performed, and as a result, the overlapping area determination unit 12 selects the pattern data (D ₂₁ ) in step S43.

Next, the overlapping area determination unit 12 performs a logical product operation of the selected pattern data (D ₁₁ ) and (D ₂₁ ) to thereby determine the relationship between the ground lines (E ₁₁ ) and (E ₂₁ ). The overlapping area data ( _D121 ) indicating the overlapping area ( _E121 ) is obtained (step S47).

The overlapping area (E ₁₂₁ ) displayed by the obtained overlapping area data (D ₁₂₁ ) is shown in FIG. 7 (b) and the ground line (E ₁₁ ) and FIG. 7 (c). It is shown as a part of each with the earth line (E ₂₁ ).

Next, the overlapping area determination unit 12 adds 1 to the pattern number (k) on the partner layer (step S48), sets the pattern number (k) on the partner layer to 2, and then sets the pattern number on the partner layer. After confirming that (k) does not exceed the total number of patterns (K) belonging to the designated net on the other layer (i = 2) (K = 2 in this case) (step S49), repeat step S46 and thereafter. .

This time, the overlapping area determination unit 12 determines in step S
After selecting the pattern data (D _ik ) [= (D ₂₂ )] at 46, based on the pattern data (D ₁₁ ) and (D ₂₂ ) at step S 47, the ground wire (E ₁₁ ) and (E ₂₂ ) The overlap area data (D ₁₂₂ ) indicating the overlap area (E ₁₂₂ ) is obtained (step S47).

The overlap area (E ₁₂₂ ) displayed by the obtained overlap area data (D ₁₂₂ ) is shown in FIG. 7 (b) and the ground line (E ₁₁ ) and FIG. 7 (c). It is shown as a part of each with the earth line (E ₂₂ ).

Next, the overlap area determining unit 12 adds 1 to the pattern number (k) on the partner layer to set the pattern number (k) on the partner layer to 3, and then sets the pattern number (k) on the partner layer to the partner layer. Total number of patterns belonging to the specified net on the layer (K) (=
When it is confirmed that the value exceeds 2) (steps S48 and S49), all the pattern data (D ₂₁ ) belonging to the specified net [= ground wire] on the partner layer (i) (= 2).
It is determined that all the overlapping area data (D ₁₂₁ ) and (D ₁₂₂ ) with (D ₂₂ ) have been obtained, and then 1 is added to the other layer number (i), and the other layer number (i) = 3 (Step S410), when it is recognized that the partner layer number (i) exceeds the number of layers to be processed (H) (= 2) (Step S411), all the target partner layers (second It is determined that the overlapping area data has been obtained for the target layer, and then 1 is added to the target layer pattern number (j) to make the target layer pattern number (j) = 2 (step S).
412), the pattern data total number (J) belonging to the specified net (ground wire) on the first layer whose pattern number (j) on the processing target layer is specified by the processing target layer number (h) (= 1) ) (= 1) (step S 413), the pattern data belonging to the designated net on the first layer, which is the processing target layer number (h) (= 1), is one of (D ₁₁ ) And only the pattern data (D ₁₁ ) belonging to all the specified nets on the first layer specified by the processing target layer number (h) = 1 and the data belonging to the specified net data (I) (= 2)
Finished calculated overlap area data with all the pattern data belonging to the specified net on the second layer, which is designated (D ₂₁₎ and (D ₂₂₎ only) (D ₁₂₁₎ and a (D ₁₂₂₎ all Recognize that

Next, the overlapping area determination unit 12 adds 1 to the processing target layer number (h) to set the processing target layer number (h) = 2 (step S414), and then sets the processing target layer number (h) to When recognizing that the number of layers to be processed (H) (= 2) has been reached (step S415), the overlapping area between the two layers in all the layers (first and second layers) specified by the net data Data [that is, overlapping area data (D ₁₂₁ ) and (D
₁₂₂ )] has been determined, and the process of determining the overlapping area is terminated.

When the overlap area determination processing by the overlap area determination section 12 is completed, the processing apparatus 1 subsequently activates the via position selection section 13. Activated via position selection unit 13
Sets the number 2 of the built-in overlapping areas (M) to 2 (that is, the overlapping areas (E ₁₂₁ ) and (E ₁₂₂ )), and then initializes the overlapping area number (m) [(m) = 1] ( In FIG. 5, step S51), the via-settable position specified by the pattern data extraction unit 11 in step S31 included in the overlapping area data (D _kim ) (= D ₁₂₁ ) corresponding to the overlapping area number (m) = 1 is obtained. (Step S52).

The via position selecting unit 13 performs a logical product operation of the via data (d) (FIG. 7A) specified in step S31 and the overlapping area data (D ₁₂₁ ) obtained by the overlapping area determining unit 12. By executing this, the overlap area data (D ₁₂₁ ) corresponding to the overlap area (E ₁₂₁ ) shown in FIG. 7B or FIG. 7C in the via data (d) shown in FIG.
Via data (d ₁ ) and (d ₂ ) included in ₁₂₁ ) are obtained.

The via position selection unit 13 once generates vias (V ₁ ) and (V ₂ ) based on the obtained via data (d ₁ ) and (d ₂ ) (step S 53). The unit 14 is started.

The activated gap defect processing unit 14 generates the vias (V ₁ ) and (V ₂ ) generated by the via position selecting unit 13.
It is checked whether the gap between the pattern and the existing pattern satisfies the reference value specified by the design reference data extracted by the pattern data extraction unit 11 in step S32 (step S54).

The existing pattern to be examined here is a signal line provided on a third layer (E ₃ ) interposed between the first layer (E ₁ ) and the second layer (E ₂ ). (F ₃₁₎
And (F ₃₂ ), the gap failure processing unit 14 generates the vias (V ₁ ) and (V ₂ ) generated by the via position selecting unit 13.
And the shortest distances between the signal lines (F ₃₁ ) and (F ₃₂ ) are calculated, and when it is confirmed that the obtained shortest distance is sufficiently larger than the reference value of the gap, the generated vias (V ₁ ) and (V ₂ ) notifies the via position selection unit 13 that there is no via to be deleted (step S55).

Next, the via position selecting section 13 sets the overlapping area number
After adding 1 to (m) to make the overlap area number (m) = 2
(Step S56), the overlapping area number (m) is determined to be the overlapping area.
Exceeds the number of overlapping areas (M) (= 2) obtained by
After confirming that there is no overlapping area (step S57),
Duplicate area data (D_kim)
(= D₁₂₂Is repeated for step S52)
As a result, the overlapping area data (D₁₂₂Vias included in)
Via data (d_Three) And (d) _Four)
Ask.

The via position selection unit 13 once generates vias (V ₃ ) and (V ₄ ) based on the obtained via data (d ₃ ) and (d ₄ ) (step S 53). The unit 14 is started.

In the same manner as described above, the activated gap defect processing unit 14 includes the vias (V ₃ ) and (V ₄ ) generated by the via position selection unit 13 and the signal lines (F ₃₁ ) and (F ₃₂ ). Of the via (V ₃ ) and the signal line (F ₃₁ )
And the shortest distance to (F ₃₂ ) is well above the reference value,
The shortest distance between the via (V ₄ ) and the signal lines (F ₃₁ ) and (F ₃₂ ) is zero, and it is determined that the signal lines (F ₃₁ ) and (F ₃₂ ) are in contact with the via (V ₄ ). If confirmed, the via (V ₄ ) is determined to be a gap defect and is deleted, and the via position selecting unit 13 is notified of this (step S55).

Next, the via position selection unit 13 adds 1 to the overlapping area number (m) to set the overlapping area number (m) = 3 (step S56), and then sets the overlapping area number (m) to the number of overlapping areas. (M) (= 2) is confirmed (step S
57), the via position selecting unit 13 determines vias (V ₁ ), (V ₂ ) and (V ₃ ) whose gaps satisfy the reference value.

Further, the via position selecting unit 13 analyzes whether or not there is a mergeable via among the vias (V ₁ ), (V ₂ ) and (V ₃ ) generated this time (step S5).
8).

As an example of a via that can be merged, a via corresponding to the via data (d ₁ ) is generated between the first layer and the second layer, and between the second layer and the third layer. Via data (d
_If a via corresponding to ₁ ) is generated, two vias are formed between the first layer, the second layer, and the third layer via data (d
₁ ) is considered as one via generated in response to
Via data (d ₁ ) between the first, second and third layers
Into one via generated corresponding to.

As another example of vias that can be merged,
Vias corresponding to vias data (d ₁₎ is generated between the first and second layers, also via the generation corresponding to the via data (d ₁₎ also between the first and third layers In this case, the two vias are considered to be merged into one via generated between the first layer, the second layer, and the third layer in accordance with the via data (d ₁ ). One via is generated between the second and third layers corresponding to the via data (d ₁ ).

However, this time, as described above, since only the vias between the first layer and the second layer are targeted, there is no via to be integrated into one. As described above, the computer-aided apparatus 10 sets the vias (V ₁ ) and (V ₂ ) as vias for the designated net, that is, the ground wires provided on the first layer and the second layer.
And (V ₃ ) are determined and registered in the database (DB).

As is clear from the above description, according to this embodiment, the pattern data (D ₁₁ ), (D ₂₁ ) and (D ₂₂ ) belonging to the designated net are all covered by the overlapping area data. (D ₁₂₁ ) and (D ₁₂₂ ) are obtained, and the obtained overlapping area data (D ₁₂₁ ) and via data (d ₁ ), (d ₂ ) corresponding to the via settable position designated in (D ₁₂₂ ) , (D ₃ ) and (d ₄ ), and delete only the via data (d ₄ ) whose gap between the designated existing signal lines (F ₃₁ ) and (F ₃₂ ) does not satisfy the reference value, Since it is decided to generate vias in the remaining via data (d ₁ ), (d ₂ ) and (d ₃ ), possible vias can be generated without leaking.

Next, an embodiment of the present invention (claim 3) will be described.
This will be described with reference to FIGS. Also in this case, the designer designates the ground wire in the first layer (E ₁ ) and the second layer (E ₂ ) as the net data, and the predetermined interval as shown in FIG. If the coordinates of the intersection of the grid having the following are specified, the pattern data extraction unit 11 and the overlap area determination unit 1
2 are sequentially activated, and the ground line (E ₁₁ ) on the first layer (E ₁ )
And the geostrophic lines (E ₂₁ ) and (E ₂₂ ) on the second layer (E ₂ )
(E ₁₂₁ ) and (E ₁₂₂ ) are obtained (steps S31 to S34 in FIG. 3 and step S41 in FIG. 4).
To S415).

When the overlapping area determination processing is completed, the processing device 1 subsequently activates the via position selection unit 13. The activated via position selection unit 13 sets the number 2 of built-in overlapping areas (M) to a numerical value 2 [that is, the overlapping areas (E ₁₂₁ ) and (E ₁₂₂ )], and then sets the overlapping area number (m). ) Is initialized ([m) = 1] (step S61 in FIG. 6), and the overlapping area data (D _kim ) corresponding to the overlapping area number (m) = 1
(= D ₁₂₁ ), the pattern data extraction unit 11 obtains the via settable position specified in step S31 (step S62).

The via position selecting unit 13 performs an AND operation on the via data (d) (FIG. 7A) specified in step S31 and the overlapping area data (D ₁₂₁ ) obtained by the overlapping area determining unit 12. By executing this, the overlap area data (D ₁₂₁ ) corresponding to the overlap area (E ₁₂₁ ) shown in FIG. 7B or FIG. 7C in the via data (d) shown in FIG.
Via data (d ₁ ) and (d ₂ ) included in ₁₂₁ ) are obtained.

The via position selecting section 13 once generates vias (V ₁ ) and (V ₂ ) based on the obtained via data (d ₁ ) and (d ₂ ) (step S 53), and then performs a gap failure process The unit 15 is started.

The activated gap defect processing unit 15 generates the vias (V ₁ ) and (V ₂ ) generated by the via position selecting unit 13.
It is checked whether the gap between the pattern and the existing pattern satisfies the reference value specified by the design reference data extracted by the pattern data extraction unit 11 in step S32 (step S64).

This time, the existing pattern to be investigated
To the first layer (E₁) And the second layer (E _TwoBetween)
Third layer (E_Three) Provided on the signal line (F₃₁)and
(F ₃₂), The gap defect processing unit 14 selects the via position.
Vias (V₁) And (V_Two) And the signal
Line (F₃₁) And (F₃₂) And calculate the shortest distance
Make sure that the shortest distance is well above the gap reference
Then, the generated via (V₁) And (V_Two) No gap
Notify via position selector 13 that no good via exists
(Step S65).

Next, the via position selector 13 adds 1 to the overlapping area number (m) to set the overlapping area number (m) = 2 (step S611), and then determines the overlapping area number (m) as the overlapping area. After confirming that the number does not exceed the number of overlapping regions (M) (= 2) obtained by the unit 12 (step S612), the overlapping region data (D _{ki m} ) (= D ₁₂₂ ) in step S62
As a result of repeating the subsequent steps, via data (d ₃ ) and (d ₄ ) are obtained as via settable positions included in the overlapping area data (D ₁₂₂ ).

The via position selector 13 generates vias (V ₃ ) and (V ₄ ) once in the obtained via data (d ₃ ) and (d ₄ ) (step S 63). The unit 15 is started.

The activated gap defect processing unit 15 includes the vias (V ₃ ) and (V ₄ ) generated by the via position selection unit 13 and the signal lines (F ₃₁ ) and (F ₃₂ ), as described above. Of the via (V ₃ ) and the signal line (F ₃₁ )
And the shortest distance to (F ₃₂ ) is well above the reference value,
The shortest distance between the via (V ₄ ) and the signal lines (F ₃₁ ) and (F ₃₂ ) is zero, and it is determined that the signal lines (F ₃₁ ) and (F ₃₂ ) are in contact with the via (V ₄ ). After confirmation (Fig. 8 state S
T81), the gap between the via (V ₄ ) and the signal lines (F ₃₁ ) and (F ₃₂ ) is recognized as a gap defect that does not satisfy the reference value (step S65).

At this time, the gap failure processing unit 15 determines a rectangular rewiring range (D ₂₇ ) including the via data (d ₄ ) as the gap failure location (step S 66, state ST 82).
Next, the gap failure processing unit 15 temporarily deletes the pattern data (D ₃₁ ) and (D ₃₂ ) of the signal lines (F ₃₁ ) and (F ₃₂ ) existing in the rewiring range (D ₂₇ ) (step). S
67, state ST83).

Next, the gap failure processing unit 15 re-wires the re-wiring range (D ₂₇ ) from which the signal lines (F ₃₁ ) and (F ₃₂ ) have been deleted according to a known wiring procedure (step S 68, state). ST84).

In this case, for the wiring of the signal lines (F ₃₁ ) and (F ₃₂ ), a wiring path as shown in the state ST84 is obtained after securing a gap based on the design standard from the via (V ₄ ).

When the signal lines (F ₃₁ ) and (F ₃₂ ) are successfully re-wired as described above, the gap failure processing unit 14 sets the pattern data corresponding to the signal lines (F ₃₁ ) and (F ₃₂ ) after the re-wiring. After re-registering (D ₃₁ ) and (D ₃₂ ) in the database (DB) (step S610), the via position selecting unit 1
3 is notified that there is no gap-defective via in the generated vias (V ₃ ) and (V ₄ ) (step S65).

If the rewiring is unsuccessful in step S68, the via (V ₄ ) is determined to be a gap defect and is deleted, and the via position selector 13 is notified of this (step S69).

Next, the via position selection unit 13 adds 1 to the overlapping area number (m) to set the overlapping area number (m) = 3 (step S611), and then sets the overlapping area number (m) to the number of overlapping areas. When it is confirmed that (M) (= 2) has been exceeded (step S612), the via position selecting unit 13 determines the vias (V ₁ ), (V ₂ ), (V ₃ ) and (V ₃ ) whose gaps satisfy the reference value. ₄ )
To determine.

Further, the via position selecting section 13 executes the vias (V ₁ ), (V ₂ ), and (V ₃ ) generated this time in the same manner as described above.
And in (V _4), it analyzes whether mergeable vias is present (step S613).

However, also in this case, the first layer and the second layer
Because only the vias between the targets are targeted, the vias that are combined into one
Does not exist. As described above, the computer assisted device 10 is designated
Nets, that is, grounds provided on the first and second layers
Vias (V₁),
(V_Two), (V _Three) And (V_Four) And determine the database
Source (DB).

As is apparent from the above description, according to the embodiment of the present invention (claim 3), the pattern data (D ₁₁ ), (D ₂₁ ) and (D ₂₂ ) belonging to the designated net are all collected. To obtain overlapping area data (D ₁₂₁ ) and (D ₁₂₂ ), and obtain via area data (d ₁₂₁ ) and via data (d ₁₂₂ ) corresponding to a via settable position designated in (D ₁₂₂ ). ₁ ), (d ₂ ), (d
₃₎ and (after obtaining the d _4), given the existing signal lines (F ₃₁₎ and (F ₃₂₎ a gap between does not satisfy the reference value via (V ₄₎ signal lines with respect to (F ₃₁₎ And (F ₃₂ ) are re-wired, and if the re-wiring succeeds, vias (V ₁ ), (V ₂ ), (V ₃ ) and (V ₄ ) are generated including via data (d ₄ ). In order to determine, more vias (V ₁ ) than in the embodiment according to the invention (claim 2),
(V ₂ ), (V ₃ ) and (V ₄ ) can be generated.

FIGS. 2 to 8 are merely examples of the present invention, and for example, via generation is performed in the illustrated first layer (E).
_There is no limitation between the earth wire (E ₁₁ ) of ₁ ) and the earth wires (E ₂₁ ) and (E ₂₂ ) of the second layer (E ₂ ), and many other deformations are considered. However, the effect of the present invention does not change in any case. Needless to say, the computer-aided apparatus 100 to which the present invention is applied is not limited to the illustrated computer-aided apparatus 10.

[0070]

As described above, according to the present invention (claim 1), it is possible to provide as many connection paths for connecting the specified patterns on a plurality of layers as possible, and Can be connected with as low impedance as possible, and according to the present invention (claim 2), it is possible to provide as many abundant connection paths as possible to connect designated patterns on a plurality of layers. In addition, even when an existing pattern exists, it is possible to remove a connection path having a gap between the existing pattern and the reference value smaller than a reference value. Connection paths connecting the specified patterns can be provided as abundantly as possible, and even if there is an existing pattern, the connection path with the gap between the existing pattern and the reference value is smaller than the reference value. Possible It becomes possible to provide Correct far, allows connection as possible given the pattern cross at a low impedance.

[Brief description of the drawings]

FIG. 1 illustrates the principle of the present invention.

FIG. 2 is a diagram showing a computer-aided apparatus according to an embodiment of the present invention;

FIG. 3 is a diagram showing an example of a pattern data extraction process in FIG. 2;

FIG. 4 is a diagram showing an example of an overlapping area determination process in FIG. 2;

FIG. 5 is a view showing a via generation process according to an embodiment of the present invention (claim 2);

FIG. 6 is a diagram showing a via generation process according to an embodiment of the present invention (claim 3);

FIG. 7 is a diagram showing a via generation process according to an embodiment of the present invention (claim 2);

FIG. 8 is a diagram showing an example of a gap defective via relief process in FIG. 6;

FIG. 9 is a diagram showing an example of a conventional computer assisted device.

FIG. 10 is a diagram showing an example of a via creation process in FIG. 9

[Explanation of symbols]

 Reference Signs List 1 processing device 2 main storage device 3 external storage device 4 keyboard 5 mouse 6 input / output control device 7 display 8 display control device 9 bus 10, 100 computer aided device 11 pattern data extraction unit 12 overlapping area determination unit 13 via position selection unit 14 , 15 gap failure processing unit 101 overlapping area determination means 102 connection position selection means 103, 104 connection position correction means

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50 H01L 23/12 H05K 3/46

Claims (3)

(57) [Claims] 1. A computer-aided apparatus (100) for creating a printed wiring pattern comprising a plurality of layers, wherein an overlap area (A) in which a specified pattern (P) on a specified plurality of layers overlaps is determined. Decision means (1
01), and in the overlapping area (A) determined by the overlapping area determining means (101), a setting position of a connection path (V) interconnecting the patterns (P) between different layers is predetermined. And a connection position selecting means (102) for selecting according to the criterion. 2. A computer-aided apparatus (100) for creating a printed wiring pattern comprising a plurality of layers, wherein an overlapping area (A) for obtaining an overlapping area (A) where a specified pattern (P) on a specified plurality of layers overlaps. Decision means (1
01), and in the overlapping area (A) determined by the overlapping area determining means (101), a setting position of a connection path (V) interconnecting the patterns (P) between different layers is predetermined. Calculating a gap between the connection pattern selecting means (102) selected according to the reference, the connection path (V) selected by the connection position selecting means (102), and the existing pattern (P ₂ );
A connection position correcting means (103) for determining a setting position of the connection path (V) except for a connection path (V) in which the gap is smaller than a predetermined reference. 3. A computer-aided apparatus (100) for creating a printed wiring pattern comprising a plurality of layers, wherein an overlap area (A) in which a specified pattern (P) on a specified plurality of layers overlaps is determined. Decision means (1
01), and in the overlapping area (A) determined by the overlapping area determining means (101), a setting position of a connection path (V) interconnecting the patterns (P) between different layers is predetermined. Calculating a gap between the connection pattern selecting means (102) selected according to the reference, the connection path (V) selected by the connection position selecting means (102), and the existing pattern (P ₂ );
If a connection (V) is detected in which the gap is below a predetermined criterion, an attempt is made to modify the existing pattern (P ₂ ) so that the gap exceeds the criterion, and the modification has not been successful. An interlayer connection system, comprising: a connection position correcting means (104) for determining a setting position of the connection path (V) except for the connection path (V).