JP2805538B2 - Printed wiring board connection verification device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application field] The present invention relates to a CAD system for designing printed wiring boards, and in particular, verifies a dividing line divided by a through-hole clearance and verifies connection between a power supply layer and an earth layer. The present invention relates to a printed wiring board connection verification device that performs the above.

[Related Art] In designing a printed wiring board, it is sometimes necessary to supply two or more different types of power sources to the same layer.

For example, as shown in FIG. 4 (a), when + 5V and + 12V power are supplied to the same layer, a part group 41 having a + 5V series is used.
And a part group 42 having a + 12V series need to be designed in an independent copper foil area. Therefore, as shown in FIG. 4 (b), partition lines 43a, 43b, and 43c are provided in the inner layer of the copper foil layer, and the area surrounded by the partition lines 43a, 43b, and 43c is
A series of component groups are arranged, and it is verified whether or not a desired circuit power supply pin is connected to these component groups without any excess or shortage.

An example of such a connection verification device is disclosed in
One disclosed in Japanese Patent No. 311575 is known. In the technique disclosed in this document, a partition line of a power supply layer or an earth layer is input from a digitizer, vectorization of the partition line is performed, then the intersection of the vectors is calculated, and the shape of the copper foil region having the calculated intersection as a vertex is calculated. Recognize first. Then, the connection verification is performed by comparing the logical power information of the component pins connected to the copper foil area with the actually supplied power information.

However, the conventional connection verification device has a drawback that when a copper foil region is divided by a through-hole clearance as shown in FIG. 5, this cannot be recognized. That is, the through-hole clearance 52 that divides the copper foil region 51 into a part of the innumerable through-hole clearances existing in the copper foil region 51 constituting the power supply layer or the earth layer, as shown in FIG. If present between 43c, the copper foil area 51 will have a through hole clearance
The part is divided by the 52, and a separated copper foil region 53 is formed.

The conventional connection verification device cannot recognize such a divided copper foil region 53, and there has been a problem that a defect is detected for the first time in a manufacturing inspection process of a printed wiring board.

The present invention has been made in order to solve the above-described problems. Even if a copper foil region of a power supply layer or an earth layer generated by a partition line is divided by a clearance, this is correctly detected and a desired pin is provided on a component. It is an object of the present invention to provide a printed wiring board connection verification device capable of verifying in advance that a power supply or a ground is not supplied.

[Means for Solving the Problems] The present invention relates to a printed wiring board connection verification device that detects overlap of through-hole clearances and recognizes division of a copper foil region. A vector generating means for converting the through hole clearance having an overlap with the copper foil region into a vector while converting the vector into a vector, and dividing each vector at an intersection to remove the overlap, and a closed figure having a continuous vector group as an outline. And a shape calculating means for calculating a value as a divided region of the copper foil.

[Operation] As described above, in the present invention, a vector generating means for converting the outline of a target copper foil region into a vector and converting a through-hole clearance overlapping with the copper foil region into a vector, And a shape calculating means for calculating a closed figure having a continuous vector group as a contour as a divided region of the copper foil, so that the through-hole clearance is vectorized and closed. In the process of calculating a figure as a divided area of the copper foil, it is possible to exclude a through-hole clearance that does not contribute to the division, and the calculated divided copper foil area can be graphed, and data close to the actual shape is obtained. High-precision connection of the power supply layer and the earth layer, for example, in the division area divided by the through-hole clearance as well as the partition line Verification can be mechanized.

Embodiment FIG. 2 is a block diagram showing a configuration of a connection verification device 2 according to the present invention and an input / output device connected thereto. The pattern data of the power supply layer or the earth layer is input from the digitizer 1 to the connection verification device 2.

The logical power supply and arrangement data of the parts are stored in the memory 3
And is read from the memory 3 and input to the connection verification device 2. The output from the connection verification device 2 is output to the display device 5 and the printing device 6.

The pattern data of the power supply layer or the earth layer input from the digitizer 1 is sent to the pattern data storage unit 22 via the input unit 21 and is temporarily stored therein. The pattern data stored in the storage unit 22 can be displayed on the display device 5 via the display unit 25.

On the other hand, the logical power supply and the placement data of the parts input from the memory 3 are compared with the comparison part via the part logic / placement input part 26.
Sent to 27. Here, the pattern data stored in the pattern data storage unit 22 is compared with the result recognized by the region recognition unit 24 that recognizes the copper foil region of the power supply layer or the ground layer.

The verification result from the comparison unit 27 is output to the printing device 6 via the verification result output unit 28. Regarding the operation of the connection verification device 2, since the part other than the area recognition unit 24 is disclosed in detail in the above-mentioned Japanese Patent Application Laid-Open No. 63-311575, the description of this part will be omitted.

Next, FIG. 1 shows an example of the area recognizing unit 24 for realizing the features of the present invention. FIG. 1 is a block diagram showing an example of a detailed configuration of the area recognizing unit 24. The data converting unit 241 connected to the pattern data storing unit 22 includes a vector memory 242 for storing the converted partition line vector data. , An intersection detection unit 243 that detects intersections of vector data, an overlap detection unit 244 that detects overlap of vectors, and an area creation processing unit 24 that creates outline data of a copper foil area from vector data.
5, a vector buffer 246 for storing vector data of one copper foil area, a clearance memory 248 for taking out and storing a through hole clearance from the pattern data storage unit 22, and a contour and a through of the copper foil area created by the area creation processing unit 245. Contour overlap detection unit 249 that detects overlap of hole clearances, grouping processing unit 2410 that detects graphical overlap between through-hole clearances, clearance data conversion unit 2411 that converts grouped through-hole clearances into vector data, partition An area division recognizing unit 2412 for recognizing a shape in which the copper foil area created from the line is divided by the through-hole clearance, and an area storing unit 247 for storing the recognized copper foil area.

The pattern data of the partition line stored in the pattern data storage unit 22 is converted into vector data by the data conversion unit 241 and, as shown in FIG.
The procedure for creating the copper foil region outline 62 is described in
Since it is described in Japanese Patent No. 1575, its description is omitted, and the procedure for calculating the shape of the copper foil region divided into the through-hole clearance will be described in detail with reference to the flowchart shown in FIG.

First, the through hole clearance 59 of the power supply layer is input from the pattern data storage unit 22, and the clearance memory 248
(Step 301). Next, contour overlap detector 2
At 49, it is checked whether or not the through hole clearance of the clearance memory 248 overlaps with the outline vector 60 of the copper foil area calculated by the area creation processing unit 245 (step
302).

FIG. 7 is a view for explaining an example of this method of implementation.
As shown in FIG. 7A, whether or not the through-hole clearance 59 overlaps with the copper foil area contour vector 60 is determined by determining the radius 61 of the through-hole clearance 59 and the through-hole as shown in FIG. Compare with the shortest distance 62 from the center of the clearance to the contour vector 60, the shortest distance 62 is the radius
If it is shorter than 61, it is determined that there is an overlap, and FIG. 7 (c)
The overlap flag 63 of the clearance memory 248 is set (step 303).

 Next, the process proceeds to a grouping process (step 304).

This grouping processing is performed by the grouping processing unit 2410, and FIG. 8 shows an outline of the processing. First, a unique initial value of 1, 2,..., N is given to the group number 64 in the clearance memory 248 as shown in FIG. 8 (b), and then a through-hole as shown in FIG. 8 (c). A combination in which the center distance 65 of the clearance is smaller than the sum of the radii 61 is found, and the larger value of the group number 64 is updated with the smaller value. The grouping is completed by performing this in a chain for all the through-hole clearances.

Next, the process proceeds to a through-hole clearance vectorization process (step 306).

This vectorization processing includes, among the through-hole clearances stored in the clearance memory 248, only the through-hole clearances belonging to the same group as the one in which the overlap flag 63 with the outline vector of the copper foil area is set, and the clearance data conversion unit This is executed by converting into a vector at 2411 and storing it in the vector memory 242 (steps 305 and 306).

FIG. 9A shows a rule when vectorizing the through-hole clearance 59, and shows that one through-hole clearance 59 is converted into a clockwise vector group. FIG. 9B shows the result of vectorizing all the through-hole clearances 59 belonging to the same group.

Thus, the process of selecting one of the innumerable through-hole clearances in the power supply layer or the earth layer that is involved in dividing the copper foil area calculated from the partition line is completed.

Next, a process of calculating the shape of the copper foil region divided by the selected through-hole clearance will be described.

First, through-hole clearance vector data,
The contour vector created by the area creation processing unit 245 is stored in the vector memory 242, and the intersection of the two is detected by the intersection detection unit 243.

Next, as shown in FIG. 10A, the vector is divided at the intersection. If there is a vector that overlaps in the same direction, only one vector is left as shown in FIG. 10B and the others are deleted.

FIG. 10C shows vector data obtained as a result of the above-described division and overlap deletion processing. As a result, the intersection division and the overlap deletion processing are completed (step 309), the obtained vector data is sequentially taken out and stored in the vector buffer 246, and the area data is created from the data in the vector buffer 246. An area shape calculation process is performed by storing the shape of the divided copper foil area as area data in the area data storage unit 247 (step 308).

 The detailed procedure will be described below.

First, as shown in FIG. 11A, one arbitrary vector 71 is fetched from the vector memory 242 and moved to an empty vector buffer. Next, a vector having a start point that matches the end point of the first vector 71 that has moved and a vector that is first found when the area around the end point of the first vector is searched clockwise is used as a second vector. Move from 242 to the vector buffer 246.

In the case shown in the figure, 72 to 74 are selected as the second vector candidates, and 73 is selected as the second vector. Similarly, a third vector is extracted from the second vector 73 and moved to the vector buffer 246.

In this way, the processing is repeated in a chain, and if the end point of the vector just retrieved from the vector memory 242 matches any one of the start points of the vectors already moved to the vector buffer 246, the start point to the end point of the moved vector A closed figure having a series of vector groups up to the outline as a contour is stored in the area storage unit 247. If the connected vector cannot be found before forming the closed figure, the vector buffer 246 is emptied and the vector memory 2 is cleared.
Extracts any vector from 42 and returns a vector buffer
Start over from step 246.

In addition, even when a closed figure can be formed and stored in the area storage unit 247, the process returns to a series of processes for emptying the vector buffer 246 and extracting an arbitrary vector.

In this way, the processing is repeated until the vector data is empty from the vector memory
As shown in the figure, the shape of the copper foil region divided by the through-hole clearance can be detected.

The following procedure is the same as that of the conventional verification apparatus, and compares the logical power supply position information of the component pins with the calculated shape of the copper foil region to verify the connection of the power supply layer and the ground layer.

[Effects of the Invention] As described above in detail based on the embodiments, according to the present invention, the outline of the target copper foil region is converted into a vector, and the through hole having the overlap with the copper foil region is provided. Vector generation means for converting a clearance into a vector, and shape calculation means for dividing each vector at an intersection to eliminate overlap and calculating a closed figure having a continuous vector group as an outline as a copper foil divided area are provided. Therefore, in the process of vectorizing the through-hole clearance and calculating the closed figure as a copper foil divided area, it is possible to exclude the through-hole clearance that does not contribute to the division and to calculate the calculated divided copper foil area as a figure. Data close to the actual shape can be obtained, and in addition to the partition line, in the divided area divided by the through-hole clearance, For example, it is possible to mechanize the connection verification of the power supply layer and the ground layer with high accuracy. Therefore, a remarkable effect can be expected in shortening the design time of the printed wiring board and reducing the occurrence of defects.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a detailed configuration of an area recognition unit of a connection verification device according to the present invention. FIG. 2 is a block diagram showing a schematic configuration of a printed wiring board connection verification device to which the present invention is applied. FIG. 3 is a flowchart for explaining a procedure for calculating a shape of a copper foil area divided by a through-hole clearance, FIG. 4 is an explanatory view for explaining a procedure for separating different power supply layer areas by partition lines, and FIG. FIG. 6 is an explanatory view for explaining that a copper foil area is divided by a through-hole clearance, FIG. 6 is an explanatory view for explaining formation of a copper foil area outline by a partition line, and FIG. FIG. 8 is an explanatory diagram for explaining a step of detecting overlap of FIG. 9, FIG. 8 is an explanatory diagram for explaining a through-hole clearance grouping process, and FIG.
FIG. 9 and FIG. 9B are explanatory diagrams for explaining the vectorization process.
FIGS. 10A, 10B, and 10C are explanatory diagrams for explaining intersection division and overlap deletion processing, and FIGS. 11A and 11B are explanatory diagrams for explaining region shape calculation processing. In the figure, 1... Digitizer, 2... Connection verification device, 3... Component logical power supply and arrangement data storage memory, 22... Pattern data storage unit, 24.
27 ... Comparison unit, 241 ... Data conversion unit, 242 ... Vector memory, 243 ... Intersection detection unit, 244 ... Overlap detection unit, 24
5 ... Area creation processing unit, 246 ... Vector buffer, 247
…… Area storage unit, 248 …… Clearance memory, 249 ……
Contour overlap detection unit, 2410 ... Grouping processing unit, 2411 ...
... Clearance data converter, 2412 ... Area division recognition unit.

Claims (1)

(57) [Claims] An apparatus for verifying connection of a printed wiring board, which detects overlap of through hole clearances and recognizes division of a copper foil area, converts an outline of a target copper foil area into a vector, Vector generation means that converts through-hole clearances that have overlaps with vectors into vectors, and divides each vector at intersections to remove overlaps and calculate a closed figure with a continuous vector group as a contour as a copper foil divided area A connection verification device for a printed wiring board, comprising: