JPS61166094A - Manufacture of electronic circuit package - Google Patents
Manufacture of electronic circuit packageInfo
- Publication number
- JPS61166094A JPS61166094A JP564785A JP564785A JPS61166094A JP S61166094 A JPS61166094 A JP S61166094A JP 564785 A JP564785 A JP 564785A JP 564785 A JP564785 A JP 564785A JP S61166094 A JPS61166094 A JP S61166094A
- Authority
- JP
- Japan
- Prior art keywords
- electronic circuit
- circuit package
- electronic
- pads
- manufacture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電子回路パッケージの製造に関し、特に導電
ペーストにより回路を形成する印刷配線板の製造と、同
配線板に電子部品を搭載接合する電子回路パッケージの
製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the production of electronic circuit packages, and particularly to the production of printed wiring boards on which circuits are formed using conductive paste, and the mounting and bonding of electronic components on the printed wiring boards. The present invention relates to a method of manufacturing an electronic circuit package.
従来、この種の電子回路パッケージを構成する樹脂製の
絶縁板１上に導体回路２とノくラド３を全加熱硬化させ
念後、パッド３上にはんだ６全印刷し、更にその上に電
子部品４のリードを載置し、その後加熱して接合する方
法で作られている。尚、本印刷配線板に電子部品４を搭
載した後、リードとパッド３を接合する方法は、従来ク
リームはんだによるリフロー法等のはんだ付方法がとら
れている。また、５は赤外線ヒータである０〔解決すべ
き問題点〕
上述した従来の印刷板の作成並びに電子部品４のリード
の接合は各々別工程となっているため、導体回路２の硬
化加熱とけんだ６のリフロー加熱という加熱工程が重複
しているという工程上の欠点がある。更に、電子部品４
のリードの接合にはんだ６という接合機能のみを受けも
つ材料を使用〔問題点を解決するための手段〕
本発明の電子回路パッケージの製造方法は、回路を形成
する導電ペーストに本来の導電性に加え、パッドとリー
ド接合が十分な機能で且つ、搭載部品の熱劣化温度以下
の加熱硬化条件を持つ素材を選び、スクリーン印刷後直
に部品搭載を行い更Ｋ［Ｋ加熱処理を行うことにある。Conventionally, the conductor circuit 2 and the solder pad 3 are completely heated and cured on the resin insulating plate 1 constituting this type of electronic circuit package, and then the solder 6 is completely printed on the pad 3, and then the electronic circuit is printed on the pad 3. It is made by placing the leads of component 4 and then heating and joining them. After the electronic components 4 are mounted on the printed wiring board, the leads and pads 3 are conventionally joined by a soldering method such as a reflow method using cream solder. In addition, 5 is an infrared heater.0 [Problems to be solved] Since the above-mentioned conventional printing plate production and the bonding of the leads of the electronic component 4 are separate processes, the curing and heating of the conductor circuit 2 and the bonding of the leads are performed separately. There is a disadvantage in the process that the heating process of reflow heating of 6 is duplicated. Furthermore, electronic components 4
A method for manufacturing an electronic circuit package according to the present invention uses solder 6, a material that has only a bonding function, for bonding the leads of the circuit. In addition, we select a material that has sufficient functionality for bonding pads and leads, and has heat-curing conditions below the thermal deterioration temperature of the mounted components, and then mounts the components immediately after screen printing and performs K heat treatment. .
そのために、本発明は、絶縁体上に導電ペーストにて回
路及びパッドを形成した後、回路導体の硬化処理以前に
電子部品の搭載を行い、その後に回路導体の硬化処理と
同時に電子部品のリード部とパッドの接合を行う電子回
路パッケージの製造方法としている。To this end, the present invention forms circuits and pads on an insulator using conductive paste, then mounts electronic components before hardening the circuit conductor, and then simultaneously hardens the circuit conductor and leads the electronic components. This is a method of manufacturing an electronic circuit package in which the parts and pads are bonded.
次に本発明について図面を参照して説明する０第１図は
本発明の実施例の縦断面図である。全く回路導体のない
エポキシ素材の絶縁板１上にスクリーン印刷で回路導体
２とパッド３を形成し、加熱硬化以前罠電子部品４とし
てのリード付のブラシ）ＩＣをパッド３上に搭載する。Next, the present invention will be described with reference to the drawings. FIG. 1 is a longitudinal sectional view of an embodiment of the present invention. A circuit conductor 2 and a pad 3 are formed by screen printing on an insulating plate 1 made of an epoxy material having no circuit conductor at all, and an IC (brush with a lead as an electronic component 4) is mounted on the pad 3 before being heated and hardened.
更忙、赤外練合を同時に行うものである。This is a process where you can do both work and infrared training at the same time.
本実施例の要点は、導体ペーストのチクロトロビツク指
数が比較的大きく導体やパッドの厚さが太き（出来るも
ので且つ、硬化条件が比較的低温。The main points of this embodiment are that the conductor paste has a relatively large cychrotrovitsk index, the conductors and pads have a large thickness, and the curing conditions are relatively low.
短時間で導電性が得やすいものであることである。It is easy to obtain conductivity in a short time.
以下に導電ペーストの諸データを示す。Various data of the conductive paste are shown below.
ｌ）材 質 銅−エポキシ樹脂系２） チク
ロトロピツク指数 ４〜６１１／九１００３）比抵抗
１０−２Ω／１２１このような方法により
、電子回路パッケージを形成することにより、工程の簡
素化がなされ、且つ接合のためのみに用いていたはんだ
の使用をせずに済むこととなるものである。l) Material: Copper-epoxy resin system 2) Cychrotropic index: 4-611/9 1003) Specific resistance: 10-2Ω/121 By forming an electronic circuit package using such a method, the process can be simplified, and This eliminates the need to use solder, which was used only for bonding.
以上説明したように、本発明は絶縁体上に導電ペースト
にて回路及びパッドを形成した後、回路導体の硬化処理
以前に電子部品の搭載を行い、その後回路導体の硬化処
理と同時に電子部品のリード部とパッドの接合を行うこ
ととしたため、電子回路パッケージの製造を最短工種で
行うことが出来る効果があるとともに従来性われてきた
クリームはんだの印刷とりフロ一工程を省略出来るとい
う効果がある。As explained above, the present invention forms circuits and pads on an insulator using conductive paste, then mounts electronic components before hardening the circuit conductor, and then mounts the electronic components at the same time as the hardening of the circuit conductor. Since the lead portion and the pad are bonded, there is an effect that the electronic circuit package can be manufactured in the shortest amount of time, and the conventional step of printing and removing cream solder can be omitted.
第１図（イ）〜（ホ）は、本発明の電子回路パッケージ
製造方法の工程を示す縦断面図、
そして、第２図（イ）〜（ト）は従来の製造方法の縦断
面図である。
１・・・絶縁板 ２・・・回路導体３・・・
パッド部 ４・・・リード付電子部品５・・
・赤外線ヒーター ６・・・ハンダ第 １ 図Figures 1 (a) to (e) are vertical cross-sectional views showing the steps of the electronic circuit package manufacturing method of the present invention, and Figures 2 (a) to (g) are vertical cross-sectional views of the conventional manufacturing method. be. 1... Insulating plate 2... Circuit conductor 3...
Pad part 4...Electronic component with lead 5...
・Infrared heater 6...Solder Figure 1
Claims (1)
後、回路導体の硬化処理以前に電子部品の搭載を行い、
その後回路導体の硬化処理と同時に電子部品のリード部
とパッドの接合を行う電子回路パッケージの製造方法。After forming circuits and pads on the insulator using conductive paste, electronic components are mounted before curing the circuit conductor.
A method for manufacturing an electronic circuit package in which the lead portions and pads of electronic components are then bonded together at the same time as the circuit conductor is cured.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP564785A JPS61166094A (en) | 1985-01-18 | 1985-01-18 | Manufacture of electronic circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP564785A JPS61166094A (en) | 1985-01-18 | 1985-01-18 | Manufacture of electronic circuit package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61166094A true JPS61166094A (en) | 1986-07-26 |
Family
ID=11616922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP564785A Pending JPS61166094A (en) | 1985-01-18 | 1985-01-18 | Manufacture of electronic circuit package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61166094A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020095340A1 (en) * | 2018-11-05 | 2020-05-14 | 株式会社Ｆｕｊｉ | Circuit forming method |
-
1985
- 1985-01-18 JP JP564785A patent/JPS61166094A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020095340A1 (en) * | 2018-11-05 | 2020-05-14 | 株式会社Ｆｕｊｉ | Circuit forming method |
| JPWO2020095340A1 (en) * | 2018-11-05 | 2021-09-02 | 株式会社Ｆｕｊｉ | Circuit formation method |
| US11570900B2 (en) | 2018-11-05 | 2023-01-31 | Fuji Corporation | Circuit forming method |
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