JPH118459A - Mounting structure for surface-mounted component on printed wiring board - Google Patents
Mounting structure for surface-mounted component on printed wiring boardInfo
- Publication number
- JPH118459A JPH118459A JP9158858A JP15885897A JPH118459A JP H118459 A JPH118459 A JP H118459A JP 9158858 A JP9158858 A JP 9158858A JP 15885897 A JP15885897 A JP 15885897A JP H118459 A JPH118459 A JP H118459A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- mounted component
- thermal expansion
- surface mount
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
- H05K3/4676—Single layer compositions
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、プリント配線板
に実装される表面実装部品のはんだ付け寿命を向上させ
る表面実装部品のプリント配線板への実装構造に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of a surface-mounted component on a printed wiring board for improving the soldering life of the surface-mounted component mounted on the printed wiring board.
【０００２】[0002]
【従来の技術】電子機器の小型化・高性能化にともなっ
て、プリント回路板の実装技術においてもプリント配線
板に実装される電子部品の小型化やプリント配線板の小
型化、さらに、電子部品やプリント配線板の高配線率化
が図られている。また、高密度化を実現するために、セ
ラミックなどの熱膨張係数の低い材料で形成された電子
部品も普及してきている。2. Description of the Related Art With the miniaturization and high performance of electronic equipment, in the mounting technology of printed circuit boards, miniaturization of electronic components mounted on printed wiring boards, miniaturization of printed wiring boards, and furthermore, electronic components And higher wiring ratio of printed wiring boards. In addition, electronic components formed of a material having a low coefficient of thermal expansion, such as ceramics, have been widely used in order to realize high density.
【０００３】図４は従来技術の図を示すものである。同
図（ａ）において、表面実装部品６１は、例えばＢＧＡ
（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）パッケージやＣＳ
Ｐ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）等がある。
前記の表面実装部品６１は、下面に格子上に配置された
電極６２を形成している。一方、プリント配線板５１
は、前述の電極６２に対向するフットプリント５２を所
定の間隔で形成されている。FIG. 4 shows a diagram of the prior art. In FIG. 1A, a surface mount component 61 is, for example, a BGA.
(Ball Grid Array) Package and CS
P (Chip Size Package) and the like.
The surface mounting component 61 has electrodes 62 arranged on a lattice on the lower surface. On the other hand, the printed wiring board 51
Has footprints 52 facing the electrodes 62 at predetermined intervals.
【０００４】なお、前述の表面実装部品６１は、熱膨張
係数が７ｐｐｍ程度のセラミックで形成されることが多
い。また、前述のプリント配線板５１は、熱膨張係数が
１５ｐｐｍ程度のガラスエポキシ樹脂で積層されること
が多い。[0004] The above-mentioned surface mount component 61 is often formed of ceramic having a thermal expansion coefficient of about 7 ppm. The printed wiring board 51 described above is often laminated with a glass epoxy resin having a thermal expansion coefficient of about 15 ppm.
【０００５】表面実装部品６１の電気的接続のためのは
んだ付けは、予め表面実装部品６１の電極６２に図示し
ないはんだボールを備える。一方、プリント配線板５１
のフットプリント５２にはクリームはんだを印刷してお
く。その後、表面実装部品６１をプリント配線板５１の
所定の位置に搭載して、リフロー加熱を行うことではん
だ付け部６５を形成する。なお、一般に採用されている
リフローの雰囲気温度は２３０゜Ｃ程度である。[0005] Soldering for electrical connection of the surface mount component 61 is provided with a solder ball (not shown) on the electrode 62 of the surface mount component 61 in advance. On the other hand, the printed wiring board 51
Cream solder is printed on the footprint 52. After that, the surface mount component 61 is mounted at a predetermined position on the printed wiring board 51, and reflow heating is performed to form the soldered portion 65. The ambient temperature of the generally employed reflow is about 230 ° C.
【０００６】同図（ｂ）は、高温による熱ストレス（膨
張）を示し、フットプリント５２と電極６２との相対的
な熱膨張の差は、プリント配線板５１が表面実装部品６
１に比較して熱膨張係数が大きいために、フットプリン
ト５２の間隔は電極６２の間隔に比較して拡大する。こ
のため、はんだ付け部６５はフットプリント５２と電極
６２との間で歪な形状となる。FIG. 1B shows the thermal stress (expansion) due to high temperature. The difference in the relative thermal expansion between the footprint 52 and the electrode 62 is determined by the fact that the printed wiring board 51
Since the coefficient of thermal expansion is larger than 1, the interval between the footprints 52 is larger than the interval between the electrodes 62. Therefore, the soldered portion 65 has a distorted shape between the footprint 52 and the electrode 62.
【０００７】同図（ｃ）は、低温による熱ストレス（収
縮）を示し、フットプリント５２と電極６２との相対的
な熱膨張の差は、前述と同様にプリント配線板５１が表
面実装部品６１に比較して熱膨張係数が大きいために、
フットプリント５２の間隔は電極６２の間隔に比較して
縮小する。このため、はんだ付け部６５はフットプリン
ト５２と電極６２との間で歪な形状となる。FIG. 2C shows thermal stress (shrinkage) due to low temperature, and the difference in relative thermal expansion between the footprint 52 and the electrode 62 is determined by the printed wiring board 51 and the surface-mounted component 61 in the same manner as described above. Because the thermal expansion coefficient is large compared to
The space between the footprints 52 is smaller than the space between the electrodes 62. Therefore, the soldered portion 65 has a distorted shape between the footprint 52 and the electrode 62.
【０００８】同図（ｄ）は、はんだ付け部において前述
の熱ストレスによる電極部の部分破断を説明するもの
で、フットプリント５２と電極６２との相対的な熱膨張
の差は、はんだ付け部６５にフットプリント５２と電極
６２との間で歪な形状となることは前述の通りである。
これにより、はんだ付け部に応力が集中することで、は
んだ付け部６５は電極６２との間において部分破断を誘
発させることがある。FIG. 1 (d) explains the partial breakage of the electrode portion due to the above-mentioned thermal stress in the soldered portion. The difference in the relative thermal expansion between the footprint 52 and the electrode 62 is shown in FIG. As described above, a distorted shape is formed between the footprint 52 and the electrode 62 at 65.
As a result, stress concentrates on the soldered portion, so that the soldered portion 65 may induce partial breakage with the electrode 62.
【０００９】[0009]
【発明が解決しようとする課題】前記のごとく、従来の
技術による表面実装部品のプリント配線板への実装構造
では次のような問題点がある。As described above, the mounting structure of a surface mount component on a printed wiring board according to the prior art has the following problems.
【００１０】１）表面実装部品の電極やリード部と、プ
リント配線板のフットプリントとの相対的な熱膨張の差
によって、表面実装部品のはんだ付け部に応力が集中す
る。1) Stress is concentrated on the soldered portion of the surface mount component due to the difference in the relative thermal expansion between the electrodes and leads of the surface mount component and the footprint of the printed wiring board.
【００１１】[0011]
【課題を解決するための手段】前記の問題点を解決する
ために、この発明では次のような手段を取る。In order to solve the above problems, the present invention takes the following measures.
【００１２】１）表面実装部品のプリント配線板への実
装構造において、表面実装部品とプリント配線板との熱
膨張の差を縮小させる。1) In a structure for mounting a surface mount component on a printed wiring board, a difference in thermal expansion between the surface mount component and the printed wiring board is reduced.
【００１３】上記の手段を取ることにより、表面実装部
品のはんだ付け部に加わる応力を緩和するように働く。By taking the above measures, it works to reduce the stress applied to the soldered portion of the surface mount component.
【００１４】２）表面実装部品のプリント配線板への実
装構造において、表面実装部品を接着剤でプリント配線
板に固着する。2) In the mounting structure of the surface mounted component on the printed wiring board, the surface mounted component is fixed to the printed wiring board with an adhesive.
【００１５】上記の手段を取ることにより、表面実装部
品のはんだ付け部に加わる応力を分散するように働く。[0015] By taking the above measures, it acts to disperse the stress applied to the soldered portion of the surface mount component.
【００１６】[0016]
【発明の実施の形態】この発明は、次に示したような実
施の形態をとる。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention adopts the following embodiments.
【００１７】図１および図２に示すごとく、表面実装部
品のプリント配線板への実装構造において、表面実装部
品１１の熱膨張係数に対応するプリント配線板１を備え
る。As shown in FIGS. 1 and 2, a printed wiring board 1 corresponding to the coefficient of thermal expansion of a surface mounted component 11 is provided in a structure for mounting a surface mounted component on a printed wiring board.
【００１８】さらに、図１に示すごとく、前記プリント
配線板１は、低弾性樹脂層３で積層することが好まし
い。Further, as shown in FIG. 1, the printed wiring board 1 is preferably laminated with a low elastic resin layer 3.
【００１９】さらに、図２に示すごとく、前記プリント
配線板１は、セラミック層５で積層することが好まし
い。Further, as shown in FIG. 2, the printed wiring board 1 is preferably laminated with a ceramic layer 5.
【００２０】また、図３に示すごとく、表面実装部品の
プリント配線板への実装構造において、表面実装部品１
１の周囲または表面実装部品１１とプリント配線板１０
との間に接着剤２０を充填することが好ましい。Further, as shown in FIG. 3, in the mounting structure of the surface mount component on the printed wiring board, the surface mount component 1
1 or surface mount component 11 and printed wiring board 10
It is preferable to fill the adhesive 20 between them.
【００２１】上記の実施の形態をとることにより、以下
に示す作用が働く。By taking the above-described embodiment, the following operation works.
【００２２】図１に示す実施の形態では、表面実装部品
とプリント配線板との熱膨張係数の差を小さくすること
で、表面実装部品とプリント配線板との相対的な熱膨張
の差は縮小される。これによって、表面実装部品のはん
だ付け部に加わる応力が緩和されて、表面実装部品のは
んだ付け寿命を向上する。In the embodiment shown in FIG. 1, the difference in the thermal expansion coefficient between the surface-mounted component and the printed wiring board is reduced, so that the difference in the relative thermal expansion between the surface-mounted component and the printed wiring board is reduced. Is done. This alleviates the stress applied to the soldered portion of the surface mount component, and improves the soldering life of the surface mount component.
【００２３】さらに、図２に示す実施の形態では、セラ
ミックで形成された表面実装部品の実装においては、熱
膨張係数を同等にすることで、表面実装部品のはんだ付
け部に加わる応力が緩和されて、表面実装部品のはんだ
付け寿命を更に向上する。Further, in the embodiment shown in FIG. 2, when mounting a surface-mounted component made of ceramic, the stress applied to the soldered portion of the surface-mounted component is reduced by making the thermal expansion coefficients equal. Thus, the soldering life of the surface mount component is further improved.
【００２４】また、図３に示す実施の形態では、表面実
装部品のはんだ付け部に加わる応力を分散することで、
表面実装部品のはんだ付け寿命を向上する。In the embodiment shown in FIG. 3, the stress applied to the soldered portion of the surface mount component is dispersed,
Improves the soldering life of surface mount components.
【００２５】[0025]
【実施例】この発明による代表的な実施例を図１ないし
図３によって説明する。なお、同じ箇所は同一の符号を
付して有り、詳細な説明を省略することがある。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A typical embodiment according to the present invention will be described with reference to FIGS. Note that the same portions are denoted by the same reference numerals, and detailed description may be omitted.
【００２６】図１は本発明の実施例の図（その１）であ
る。FIG. 1 is a diagram (part 1) of an embodiment of the present invention.
【００２７】同図（ａ）はプリント配線板を示してい
る。同図において、プリント配線板１は、低弾性樹脂層
３で積層して形成する。低弾性樹脂層３は、例えば熱膨
張係数が１１ｐｐｍ程度の樹脂で形成することが好まし
い。FIG. 2A shows a printed wiring board. In the figure, a printed wiring board 1 is formed by laminating a low elastic resin layer 3. The low elastic resin layer 3 is preferably formed of, for example, a resin having a thermal expansion coefficient of about 11 ppm.
【００２８】なお、低弾性樹脂層３の間には金属箔４を
設けることができる。この金属箔４は、銅などの部材か
らなる例えば内層パターンを形成する。また、プリント
配線板１の表面にはフットプリント２を形成する。フッ
トプリント２は、後述する表面実装部品１１の電極１２
に対向して所定の間隔で形成されている。A metal foil 4 can be provided between the low elastic resin layers 3. The metal foil 4 forms, for example, an inner layer pattern made of a member such as copper. A footprint 2 is formed on the surface of the printed wiring board 1. The footprint 2 includes an electrode 12 of a surface mount component 11 described later.
And are formed at a predetermined interval.
【００２９】同図（ｂ）は表面実装部品を搭載した状態
を示している。同図において、表面実装部品１１は、例
えば熱膨張係数が７ｐｐｍ程度のセラミックで形成され
たＢＧＡパッケージやＣＳＰ等である。FIG. 2B shows a state where the surface mount components are mounted. In the figure, a surface mount component 11 is, for example, a BGA package or a CSP formed of ceramic having a thermal expansion coefficient of about 7 ppm.
【００３０】表面実装部品１１の電気的接続のためのは
んだ付けは、前述の図４（ａ）と同様に、予め表面実装
部品１１の電極１２に図示しないはんだボールを備え
る。一方、プリント配線板１のフットプリント２にはク
リームはんだを印刷しておく。その後、表面実装部品１
１をプリント配線板１の所定の位置に搭載して、リフロ
ー加熱を行うことではんだ付け部１５を形成する。な
お、一般に採用されているリフローの雰囲気温度は２３
０゜Ｃ程度である。The soldering for electrical connection of the surface mount component 11 is provided with a solder ball (not shown) in advance on the electrode 12 of the surface mount component 11, as in FIG. On the other hand, cream solder is printed on the footprint 2 of the printed wiring board 1. Then, the surface mount component 1
1 is mounted on a predetermined position of the printed wiring board 1 and reflow heating is performed to form a soldered portion 15. The reflow atmosphere temperature generally employed is 23.
It is about 0 ° C.
【００３１】高温または低温による熱ストレスが加わっ
た状態においては、フットプリント２と電極１２との相
対的な熱膨張の差は、プリント配線板１が表面実装部品
１１に比較して熱膨張係数が若干大きい。このためフッ
トプリント２の間隔は電極１２の間隔に比較して高温に
おいては拡大し、低温においては縮小する。In a state where a thermal stress due to a high or low temperature is applied, the difference in the relative thermal expansion between the footprint 2 and the electrode 12 is determined by the fact that the printed wiring board 1 has a thermal expansion coefficient that is smaller than that of the surface mount component 11. Slightly larger. For this reason, the interval between the footprints 2 increases at a high temperature and decreases at a low temperature as compared with the interval between the electrodes 12.
【００３２】しかし、フットプリント２と電極１２との
相対的な熱膨張の差は僅かであり、はんだ付け部１５は
フットプリント２と電極１２との間で歪な形状となるこ
とはない。However, the difference in the relative thermal expansion between the footprint 2 and the electrode 12 is small, and the soldered portion 15 does not have a distorted shape between the footprint 2 and the electrode 12.
【００３３】図２は本発明の実施例の図（その２）であ
る。FIG. 2 is a diagram (part 2) of the embodiment of the present invention.
【００３４】同図（ａ）はプリント配線板を示してい
る。同図において、前述の図１（ａ）との違いは、プリ
ント配線板１を例えば熱膨張係数が７ｐｐｍ程度のセラ
ミック層５で積層して形成する点にある。FIG. 2A shows a printed wiring board. 1A, the difference from FIG. 1A is that the printed wiring board 1 is formed by laminating a ceramic layer 5 having a thermal expansion coefficient of, for example, about 7 ppm.
【００３５】同図（ｂ）は表面実装部品を搭載した状態
を示している。同図において、表面実装部品１１は、例
えば熱膨張係数が７ｐｐｍ程度のセラミックで形成され
たＢＧＡパッケージやＣＳＰ等である。FIG. 3B shows a state where the surface mount components are mounted. In the figure, a surface mount component 11 is, for example, a BGA package or a CSP formed of ceramic having a thermal expansion coefficient of about 7 ppm.
【００３６】表面実装部品１１の電気的接続のためのは
んだ付けは、前述の図１（ｂ）と同様であり詳細な説明
を省略する。The soldering for the electrical connection of the surface mount component 11 is the same as that shown in FIG. 1B, and the detailed description is omitted.
【００３７】高温または低温による熱ストレスが加わっ
た状態において、プリント配線板１は表面実装部品１１
と同等の熱膨張係数を有する。このため、温度変化に関
係なくフットプリント２と電極１２との相対的な熱膨張
の差はなくなるので、はんだ付け部１５はフットプリン
ト２と電極１２との間で歪な形状となることはない。In a state where heat stress due to high or low temperature is applied, the printed wiring board 1 is
Has the same thermal expansion coefficient as Therefore, there is no difference in the relative thermal expansion between the footprint 2 and the electrode 12 irrespective of the temperature change, so that the soldered portion 15 does not have a distorted shape between the footprint 2 and the electrode 12. .
【００３８】図３は本発明の実施例の図（その３）であ
る。同図は表面実装部品に所定のリフロー加熱によるは
んだ付けを行った後に、接着剤を充填する１例について
示すものである。FIG. 3 is a diagram (part 3) of the embodiment of the present invention. FIG. 1 shows an example in which the surface mounting component is soldered by predetermined reflow heating and then filled with an adhesive.
【００３９】同図（ａ）において、表面実装部品１１の
周囲に接着剤２０を充填する例を示す。同図において、
接着剤２０は、例えばアクリル／エポキシ樹脂からなる
熱硬化性樹脂を用いる。なお、接着剤２０を充填した
後、例えば雰囲気温度を１００゜Ｃとし、３０分間程度
温度を保持することで接着剤２０を硬化させる。FIG. 3A shows an example in which the adhesive 20 is filled around the surface mount component 11. In the figure,
As the adhesive 20, a thermosetting resin made of, for example, an acrylic / epoxy resin is used. After the adhesive 20 is filled, the adhesive 20 is cured by, for example, setting the ambient temperature to 100 ° C. and maintaining the temperature for about 30 minutes.
【００４０】なお、表面実装部品１１は、例えば熱膨張
係数が７ｐｐｍ程度のセラミックで形成されたＢＧＡパ
ッケージやＣＳＰ等である。プリント配線板１０は、例
えば熱膨張係数が１５ｐｐｍ程度のガラスエポキシ樹脂
で積層されている。The surface mount component 11 is, for example, a BGA package or CSP made of ceramic having a thermal expansion coefficient of about 7 ppm. The printed wiring board 10 is laminated with, for example, a glass epoxy resin having a thermal expansion coefficient of about 15 ppm.
【００４１】同図（ｂ）において、前述の図３（ａ）と
の違いは、表面実装部品１１とプリント配線板１０との
間に接着剤２０を充填する点にある。なお、接着剤２０
を充填する際は、プリント配線板１０を傾けてから接着
剤２０を流しこむことが好ましい。FIG. 3B differs from FIG. 3A in that an adhesive 20 is filled between the surface-mounted component 11 and the printed wiring board 10. The adhesive 20
When filling, the adhesive 20 is preferably poured after the printed wiring board 10 is tilted.
【００４２】同図（ｃ）において、前述の図３（ａ）お
よび図３（ｂ）との違いは、フラットパッケージ形の表
面実装部品１１とプリント配線板１０との間に接着剤２
０を充填するものである。なお、表面実装部品１１の周
囲に接着剤２０を充填することもできる。3 (c), the difference between FIG. 3 (a) and FIG. 3 (b) is that the adhesive 2 is placed between the flat package type surface mount component 11 and the printed wiring board 10.
0 is filled. Note that the adhesive 20 can be filled around the surface mount component 11.
【００４３】図３に示す構成では、同図（ａ）および同
図（ｂ）においては、表面実装部品１１に形成した電極
１２と、はんだ付け部１５との間に加わる応力を分散す
ることができる。In the configuration shown in FIG. 3, in FIGS. 3A and 3B, the stress applied between the electrode 12 formed on the surface mount component 11 and the soldered portion 15 can be dispersed. it can.
【００４４】また、同図（ｃ）においては、表面実装部
品１１に形成したリード部１３と、はんだ付け部１５と
の間に加わる応力を分散することができる。なお、同図
（ｃ）においては、横手方向にリード部１３を形成した
フラットパッケージ形の表面実装部品１１において特に
有効である。In FIG. 4C, the stress applied between the lead portion 13 formed on the surface mount component 11 and the soldering portion 15 can be dispersed. In FIG. 3C, the present invention is particularly effective for a flat package type surface mount component 11 having a lead portion 13 formed in the lateral direction.
【００４５】[0045]
【発明の効果】以上説明したように本発明によれば、次
に示すような効果がある。As described above, according to the present invention, the following effects can be obtained.
【００４６】表面実装部品のプリント配線板への実装構
造において、表面実装部品の熱膨張係数に対応するプリ
ント配線板を備えるので、表面実装部品とプリント配線
板との熱膨張係数の差を小さくすることで、表面実装部
品とプリント配線板との相対的な熱膨張の差は縮小され
る。これによって、表面実装部品のはんだ付け部に加わ
る応力が緩和されて、表面実装部品のはんだ付け寿命を
向上させることができる。Since the printed wiring board corresponding to the coefficient of thermal expansion of the surface mounted component is provided in the mounting structure of the surface mounted component on the printed wiring board, the difference in the thermal expansion coefficient between the surface mounted component and the printed wiring board is reduced. Thus, the difference in the relative thermal expansion between the surface mount component and the printed wiring board is reduced. As a result, the stress applied to the soldered portion of the surface mounted component is reduced, and the soldering life of the surface mounted component can be improved.
【００４７】さらに、前記プリント配線板は、セラミッ
ク層で積層するので、セラミックで形成された表面実装
部品の実装においては、熱膨張係数を同等にすること
で、表面実装部品のはんだ付け部に加わる応力が緩和さ
れて、表面実装部品のはんだ付け寿命を更に向上させる
ことができる。Further, since the printed wiring board is laminated with a ceramic layer, when mounting a surface-mounted component made of ceramic, the thermal expansion coefficient is made equal to be added to a soldering portion of the surface-mounted component. The stress is relieved, and the soldering life of the surface mount component can be further improved.
【００４８】また、表面実装部品のプリント配線板への
実装構造において、表面実装部品の周囲または表面実装
部品とプリント配線板との間に接着剤を充填するので、
表面実装部品のはんだ付け部に加わる応力を分散するこ
とで、表面実装部品のはんだ付け寿命を向上させること
ができる。In the mounting structure of the surface-mounted component on the printed wiring board, the adhesive is filled around the surface-mounted component or between the surface-mounted component and the printed wiring board.
By dispersing the stress applied to the soldered portion of the surface mount component, the soldering life of the surface mount component can be improved.
【図１】本発明の実施例の図（その１）である。FIG. 1 is a diagram (part 1) of an embodiment of the present invention.
【図２】本発明の実施例の図（その２）である。FIG. 2 is a diagram (part 2) of the embodiment of the present invention.
【図３】本発明の実施例の図（その３）である。FIG. 3 is a diagram (part 3) of the embodiment of the present invention;
【図４】従来技術の図である。FIG. 4 is a diagram of the prior art.
１：プリント配線板 ３：低弾性樹脂層 ５：セラミック層 １０：プリント配線板 １１：表面実装部品 ２０：接着剤 1: Printed wiring board 3: Low elastic resin layer 5: Ceramic layer 10: Printed wiring board 11: Surface mount component 20: Adhesive
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０５Ｋ 3/46 Ｈ０１Ｌ 23/12 Ｎ Ｊ ──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. 6 Identification code FI H05K 3/46 H01L 23/12 NJ
Claims (4)
造において、表面実装部品（１１）の熱膨張係数に対応
するプリント配線板（１）を備える、ことを特徴とする
表面実装部品のプリント配線板への実装構造。1. A printed circuit board mounted on a printed wiring board, comprising: a printed wiring board (1) corresponding to a coefficient of thermal expansion of the surface mounted component (11). Mounting structure on the wiring board.
層（３）で積層する、ことを特徴とする請求項１に記載
の表面実装部品のプリント配線板への実装構造。2. The mounting structure according to claim 1, wherein the printed wiring board is laminated with a low elastic resin layer.
層（５）で積層する、ことを特徴とする請求項１に記載
の表面実装部品のプリント配線板への実装構造。3. The mounting structure according to claim 1, wherein said printed wiring board is laminated with a ceramic layer.
造において、表面実装部品（１１）の周囲または表面実
装部品（１１）とプリント配線板（１０）との間に接着
剤（２０）を充填する、ことを特徴とする表面実装部品
のプリント配線板への実装構造。4. In a mounting structure of a surface-mounted component on a printed wiring board, an adhesive (20) is provided around the surface-mounted component (11) or between the surface-mounted component (11) and the printed wiring board (10). Filling, mounting structure of surface mount components to printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9158858A JPH118459A (en) | 1997-06-16 | 1997-06-16 | Mounting structure for surface-mounted component on printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9158858A JPH118459A (en) | 1997-06-16 | 1997-06-16 | Mounting structure for surface-mounted component on printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH118459A true JPH118459A (en) | 1999-01-12 |
Family
ID=15680948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9158858A Pending JPH118459A (en) | 1997-06-16 | 1997-06-16 | Mounting structure for surface-mounted component on printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH118459A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1126752A2 (en) * | 2000-02-16 | 2001-08-22 | The Boeing Company | Chip scale packaging on CTE matched printed wiring boards |
| US7514781B2 (en) | 2005-11-25 | 2009-04-07 | Denso Corporation | Circuit substrate and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5321771A (en) * | 1976-08-11 | 1978-02-28 | Sharp Kk | Electronic parts mounting structure |
| JPH08107261A (en) * | 1994-10-03 | 1996-04-23 | Sumitomo Kinzoku Ceramics:Kk | Mutual connecting structure and method of electric circuit device |
| JPH08195414A (en) * | 1995-01-12 | 1996-07-30 | Toshiba Corp | Semiconductor device |
| JPH09153521A (en) * | 1995-11-30 | 1997-06-10 | Toshiba Corp | Semiconductor device |
-
1997
- 1997-06-16 JP JP9158858A patent/JPH118459A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5321771A (en) * | 1976-08-11 | 1978-02-28 | Sharp Kk | Electronic parts mounting structure |
| JPH08107261A (en) * | 1994-10-03 | 1996-04-23 | Sumitomo Kinzoku Ceramics:Kk | Mutual connecting structure and method of electric circuit device |
| JPH08195414A (en) * | 1995-01-12 | 1996-07-30 | Toshiba Corp | Semiconductor device |
| JPH09153521A (en) * | 1995-11-30 | 1997-06-10 | Toshiba Corp | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1126752A2 (en) * | 2000-02-16 | 2001-08-22 | The Boeing Company | Chip scale packaging on CTE matched printed wiring boards |
| EP1126752A3 (en) * | 2000-02-16 | 2003-05-02 | The Boeing Company | Chip scale packaging on CTE matched printed wiring boards |
| US6757968B2 (en) | 2000-02-16 | 2004-07-06 | The Boeing Company | Chip scale packaging on CTE matched printed wiring boards |
| US7514781B2 (en) | 2005-11-25 | 2009-04-07 | Denso Corporation | Circuit substrate and manufacturing method thereof |
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| A02 | Decision of refusal |
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