JP4086123B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP4086123B2
JP4086123B2 JP23263598A JP23263598A JP4086123B2 JP 4086123 B2 JP4086123 B2 JP 4086123B2 JP 23263598 A JP23263598 A JP 23263598A JP 23263598 A JP23263598 A JP 23263598A JP 4086123 B2 JP4086123 B2 JP 4086123B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
insulating substrate
resin
semiconductor device
connection terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP23263598A
Other languages
Japanese (ja)
Other versions
JPH11297752A (en
Inventor
和孝 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP23263598A priority Critical patent/JP4086123B2/en
Priority to US09/196,884 priority patent/US6204564B1/en
Priority to TW087119257A priority patent/TW434646B/en
Priority to KR10-1998-0050017A priority patent/KR100357757B1/en
Publication of JPH11297752A publication Critical patent/JPH11297752A/en
Application granted granted Critical
Publication of JP4086123B2 publication Critical patent/JP4086123B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29399—Coating material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Compositions Of Macromolecular Compounds (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本願発明は、所定の実装対象物と半導体チップの間に介在する樹脂接着剤によって、上記実装対象物に対して上記半導体チップが機械的に接続された半導体チップの実装構造、およびこの実装構造を有するとともに絶縁性基板上に半導体チップが実装された半導体装置に関するものである。
【０００２】
【従来の技術】
従来より、絶縁性基板上に半導体チップが実装された構造を有する半導体装置としては、図１０に示したようなものがある。同図に示した半導体装置１は、いわゆるＢＧＡ（Ball Grid Array ）と称される形態のものである。上記半導体装置１では、上記絶縁性基板２の表面側に複数の接続端子部２１が形成されているとともに、上記半導体チップの主面３ａ側に複数の電極部３０が形成されており、互いに対向配置された各接続端子部２１と各電極部３０との間が電気的に接続されている。そして、半導体チップ３と絶縁性基板２とは樹脂接着剤４を介して機械的に接続されている。また、上記絶縁性基板２には、図面上には明確に表れていないが各接続端子部２１と繋がる複数の貫通孔２０が格子状に配列形成されており、これらの貫通孔２０を介して各接続端子部２１が絶縁性基板２の裏面側に形成された複数の外部端子部９と導通している。これらの外部端子部９は、ハンダによってそれぞれボール状に形成されており、貫通孔２０の配置に対応して格子状に配列形成された恰好とされている。
【０００３】
上記のように構成された半導体装置１は、たとえば適宜の回路基板にその他の電子部品とともに実装されて所望の用途に使用される。半導体装置１では、絶縁性基板２の裏面側にボール状のハンダによって外部端子部９が形成されていることから、回路基板へ上記半導体装置１を実装する際には、回路基板上に半導体装置１を載置した状態で外部端子部９としてのボール状のハンダを再溶融させる必要がある。通常、ハンダの再溶融は、たとえば雰囲気温度が２００℃ないし３００℃程度にまで加熱された加熱炉内に半導体装置１が載置された回路基板を搬入することによって行われ、上記半導体装置１も２００℃ないし３００℃程度に加熱される。
【０００４】
【発明が解決しようとする課題】
上記半導体装置１では、半導体チップ３と絶縁性基板２とが樹脂接着剤４によって機械的に接続されているが、通常、樹脂接着剤４内には多少の水分が含まれており、また内部に気泡が形成されていることが多い。このため、上記半導体装置１が加熱された場合には、水分が体積膨張し、また気泡が成長してしまい、半導体チップ３と絶縁性基板２との間に応力として作用してしまう。このような応力は、半導体チップ３に作用して半導体チップ３に直接的にダメージを与える。そればかりか、半導体チップ３と絶縁性基板２とを引き離す力として作用し、半導体チップ３の電極部３０と絶縁性基板１の接続端子部２１との間が断線してしまうことがある。
【０００５】
ところで、半導体チップ３の多機能化にともない半導体チップ３の電極部３０の数が増加の傾向にある一方で、半導体チップ３それ自体は小型化の傾向にある。このため、絶縁性基板２に半導体チップ３が実装された構成の半導体装置１では、小型化を達成すべく絶縁性基板２のサイズを半導体チップ３の近づけるとともに、絶縁性基板２の表面側に形成される配線（接続用端子部２１）を微細化する必要がある。ところが、ＢＧＡとして構成された半導体装置１では、外部端子部９はボール状ハンダとして構成されており、ハンダが溶融した場合においても隣接するボール状ハンダどうしが接触しないように、一定間隔隔ててボール状ハンダ（外部端子９）を形成する必要がある。このため、形成すべき外部端子部９の数が多くなれば、絶縁性基板２を小さくするにも限界がある。また、絶縁性基板２は、半導体チップ３が実装されたキャリアテープから基板となるべき領域を切り離すことによって形成されることから、切断時に半導体チップ３にダメージを与えないように絶縁性基板２の平面視面積を半導体チップ３のそれよりも１周り大きくなるように切断するのが通常である。
【０００６】
このような事情から、図１０に示した半導体装置１のように、平面視において絶縁性基板２の周縁部２３が半導体チップ３からはみ出した恰好とされている。このため、半導体装置１を取り扱い際などに絶縁性基板２がはみ出した部分２３に外力が作用し、半導体チップ３から絶縁性基板２が剥離されてしまうといった不具合が生じる。また、上記半導体チップ３では、半導体チップ３がベアチップの状態で絶縁性基板２に実装されていることから、半導体チップ３に直接外力が作用して半導体チップ３が欠けてしまうことがある。
【０００７】
本願発明は、このような事情のもとで考え出されたものであって、半導体チップと絶縁性基板などの実装対象物との間の接合状態を良好に維持し、半導体チップを有効に保護するようにすることをその課題としている。
【０００８】
【発明の開示】
上記の課題を解決するため、本願発明では、次の技術的手段を講じている。
【０００９】
すなわち、本願発明によって提供される半導体装置は、主面に複数の電極部が形成された半導体チップと、複数の接続端子部が上面に形成された絶縁性基板とが、上記半導体チップの上記主面と上記絶縁性基板の上記接続端子部が形成された上面との間に介在させた樹脂接着剤によって電気的および機械的に接続された半導体装置であって、上記絶縁性基板は、上記半導体チップの周囲から延出する周縁部を有している一方、上記半導体チップの周側面は、多孔性を有する保護樹脂によって囲まれているとともに、この保護樹脂は、上記半導体チップの周側面と、上記樹脂接着剤の周囲と、上記絶縁性基板の上記周縁部の 上面とに密着状態で固着され、かつ、上記半導体チップの上記主面と反対側の面における周縁部のみに乗り上げており、上記樹脂接着剤は、絶縁性を有する樹脂成分中に導電成分を分散させた構造を有しているとともに、上記絶縁性基板に形成された複数の接続端子部および上記半導体チップの主面に形成された複数の電極部のうちの少なくとも一方がバンプ状とされており、互いに対向配置された上記各接続端子部と上記各電極部との間に上記導電成分が介在して上記絶縁性基板と上記半導体チップとが電気的に接続されているとともに、上記樹脂成分によって上記絶縁性基板と上記半導体チップとが機械的に接続されていることを特徴としている。
【００１０】
【００１１】
【００１２】
【００１３】
上記構成においては、上記半導体チップと上記絶縁性基板との接続部分（樹脂接着剤）の周りを保護樹脂によって囲んでいるので、上記接続部分（樹脂接着剤内）に不純物が侵入してしまうことが回避されている。また、半導体チップの周側面を保護樹脂によって囲めば、半導体チップの周側面が保護されて半導体チップの外力に対する抵抗力が大きくなされている。そして、上記保護樹脂として、たとえば多孔質性を有するフェノール系の熱硬化性樹脂を含んだものが採用されるため、上記樹脂接着剤の周りを保護樹脂によって囲むことによって上記樹脂接着剤の通気性が損なわれることもない。
【００１４】
また、上記保護樹脂が上記半導体チップの上面（主面と反対側の面）の周縁部に乗り上げている。このようにすれば、半導体チップの上部における角部が保護樹脂によって覆われて保護されることになる。これにより、ベアチップの状態で半導体チップが上記実装対象物に実装されていたとしても、取り扱いの際に外力が作用しても半導体チップが欠けてしまたりすることが回避される。
【００１５】
【００１６】
【００１７】
【００１８】
さらに、上記構成では、上記絶縁性基板に対する半導体チップの実装に、いわゆる異方性導電接着剤が採用されている。このため、上記半導体チップと上記絶縁性基板とを電気的に接続する工程と機械的に接続する工程とを別工程とすることなく、電気的接続および機械的接続を１つの工程において行うことができる。
【００１９】
【００２０】
【００２１】
【００２２】
好ましい実施の形態においては、上記絶縁性基板には、上記接続端子部の数に応じた複数の貫通孔が格子状に配列形成されており、その下面にこれらの貫通孔を介して各接続端子部と導通するボール状の外部端子部が複数の形成されている。すなわち、いわゆるＢＧＡと称される半導体装置において、本願発明の構造を採用することもできる。
【００２３】
ＢＧＡでは、ハンダ端子部を再溶融させることによって回路基板などに半導体装置が実装されるため、この実装に際して上記樹脂接着剤も２００℃ないし３００℃程度にまで加熱される。上記半導体装置では、樹脂接着剤として多孔質性の樹脂を含んだものが使用されていることから、樹脂接着剤内の水分が体積膨張したり、あるいは気泡が成長したとしても、これらが樹脂接着剤内に残存して半導体チップや絶縁性基板に応力が作用することもない。このように、加熱により樹脂接着剤内に生じる応力によって半導体チップ自体がタメージを受け、あるいは半導体チップから絶縁性基板を剥離するような力が作用することもない。
【００２４】
ところで、半導体チップの多機能化および小型化にともない絶縁性基板に形成される配線が微細化の傾向にあり、また製造上の都合からことから、特にＢＧＡでは半導体チップよりも絶縁性基板の方が平面視面積が大きくなされるのは上述の通りである。すなわち、平面視において、半導体チップから絶縁性基板の周縁端がはみ出してしまうため、絶縁性基板が剥離するなどの不具合が生じる。これに対して本願発明の半導体装置では、上記半導体チップと上記絶縁性基板との接続部分（樹脂接着剤）の周りおよび上記半導体チップの周側面を多孔質性の樹脂を含んだ保護樹脂によって囲むような構成としているため、半導体チップから絶縁性基板の周縁端がはみ出した領域も保護樹脂によって封止され、上記はみ出し部分が半導体チップと保護樹脂を介して一体化されることとなる。このため、絶縁性基板の周縁端に外力が作用しにくくなり、これにより半導体チップから絶縁性基板が剥離してしまうことが回避される。
【００２５】
本願発明のその他の特徴および利点は、添付図面を参照して以下に行う詳細な説明によって、より明らかとなろう。
【００２６】
【発明の実施の形態】
以下、本願発明の好ましい実施の形態を添付図面を参照して説明する。図１は、本願発明に係る半導体装置の一例を示す全体斜視図、図２は、上記半導体装置を裏面側からみた全体斜視図、図３は、図１のIII −III 線に沿う断面図である。なお、これらの図において、従来例を説明するために参照した図面に表されていた要素、部材および部分などと同等なものには同一の符号を付してある。また、本実施形態では、いわゆるＢＧＡ（ボールグリッドアレイ）として構成された半導体装置について説明する。
【００２７】
図１ないし図３に示したように、上記半導体装置１は、半導体チップ３が絶縁性基板２上に実装され、いわゆる異方性導電接着剤４を介して上記半導体チップ３と絶縁性基板２とが機械的かつ電気的に接続された構成とされている。そして、上記半導体チップ３の周側面３ｃが保護樹脂５によって囲まれているとともに、上記絶縁性基板２の裏面側から突出して複数の外部端子部９が格子状に配列形成されている。
【００２８】
上記半導体チップ３は、ＩＣチップやＬＳＩチップなどのベアチップであり、主面３ａ側に複数の電極部３０が形成されている。これらの電極部３０は、上記半導体チップ３に一体的に造り込まれた端子パッド３０ａ上に金メッキを施すなどしてバンプ３０ｂが形成され、全体として突出状とされている。
【００２９】
上記絶縁性基板２は、たとえばポリイミド樹脂製であり、図２および図３に良く表れているように平面視矩形状とされているとともに、平面視面積が上記半導体チップ３よりも大きくなされている。このため、半導体チップ３を絶縁性基板２上に実装した状態では、絶縁性基板２の周縁部が上記半導体チップ３からはみ出した恰好とされている。また、上記絶縁性基板２には、複数の貫通孔２０が格子状に配列形成されているとともに、その上面にはさらに上記半導体チップ３の各電極部３０のそれぞれと導通する複数の接続用端子部２１が形成されている。各接続用端子部２１は、基端部が上記各電極部３０と対向しているとともに、先端部はそれぞれが対応する貫通孔２０にまで延びて各貫通孔２０の上部開口面を閉塞している。すなわち、上記絶縁性基板２の裏面側からは、各貫通孔２０を介して各接続用端子部２１の先端部が臨んでいる。そして、図３に良く表れているように上記各貫通孔２０を埋めるようにして、かつ各接続用端子部２１に接触するようにして上記各外部端子部９がそれぞれボール状に形成されている。
【００３０】
上記異方性導電接着剤４は、図３に良く表れているように熱硬化性の樹脂成分４０内にボール状とされた導電成分４１が分散した構成とされている。そして、上記半導体チップ３と上記絶縁性基板２とは、上記樹脂成分によって機械的に接続されているとともに、上記導電成分４１によって電気的に接続されている。上記樹脂成分４０は、たとえば多孔質性の樹脂としてのフェノール系樹脂を含んでおり、多孔質性の樹脂のみによって構成してもよく、また他の樹脂を含んでいてもよい。なお、本願発明でいうフェノール系樹脂には、フェノール樹脂の他、フェノール類を原料とするエポキシ樹脂などが含まれる。上記導電成分４１は、上記半導体チップ３の各電極部３０と上記絶縁性基板２の各接続用端子部２１の基端部との間に介在して各電極部３０と各接続用端子部２１とを電気的に接続している。上記導電成分としては、たとえば樹脂ボールの表面にニッケルメッキや金メッキを施すなどして導電性を付与したものが好適に採用されるが、金属ボールを導電成分４１としてもよい。
【００３１】
上記保護樹脂５は、上記絶縁性基板２の周縁部２３の上面を封止するとともに、上記半導体チップ３の周りを覆い、さらに上記半導体チップ３の上面３ｂにまで乗り上げている。すなわち、上記半導体チップ３と上記絶縁性基板２との接続部分（異方性樹脂接着剤４）の周り、および上記半導体チップ３の周側面３ｃを囲んでおり、上記絶縁性基板２の周縁部２３が半導体チップ３と保護樹脂５を介して一体化されている。なお、上記保護樹脂５としては、上記異方性導電接着剤４の樹脂成分４０と同様に、たとえば多孔質性の樹脂としてのフェノール系樹脂を含んだものが好適に採用される。
【００３２】
このように、上記半導体装置１では、半導体チップ３の周側面３ｃおよび上面３ｂにおける周縁部が上記保護樹脂５によって直接的に保護されている。このため、上記半導体装置１の取り扱い時に上記半導体チップ３に外力が作用したとしても、半導体チップ３へのダメージが小さくなるようになされている。また、上記絶縁性基板２の周縁部２３が上記保護樹脂によって上記半導体チップ３と一体化されていることから、絶縁性基板２の周縁部２３に直接的に外力が作用しにくいようになされている。これにより、絶縁性基板２の周端部２３に外力が作用して半導体チップ３から絶縁性基板２が剥離してしまうことが回避される。
【００３３】
次に、上記半導体装置１の製造方法について、図４ないし図９を参照しつつ説明するが、便宜上、上記半導体装置１の製造に使用されるキャリアテープ２Ａについて図４を参照しつつ先に説明する。
【００３４】
上記キャリアテープ２Ａは、図４に示すように全体として長手状とされており、同図に仮想線で囲んだ半導体チップ３が実装される矩形領域２５が長手方向に連続して複数設けられている。このキャリアテープ２Ａとしては、ポリイミド樹脂などお絶縁素材よって短冊状あるいは帯状に形成されたものが好適に使用される。各矩形領域２５には、複数の貫通孔２０が格子状にそれぞれ配列形成されているとともに、その上面には複数の接続用端子部２１がそれぞれ形成されている。これらの接続用端子部２１は、たとえば上記キャリアテープ２Ａの表面に銅などの金属膜を形成し、あるいは金属箔を貼着した後にエッチング処理することによって形成され、また予めパターン形成した金属箔を貼着して形成してもよい。上記各接続用端子部２１は、その先端部が各貫通孔２０の上部開口面を閉塞するとともに、基端部が半導体チップ３に形成された電極部３０に対応して形成されている。また、上記キャリアテープ２Ａの幅方向の両端部には、一定ピッチ毎に係止用穴２４が連続して形成されており、これらの係止用穴２４を利用して上記キャリアテープ２Ａを適宜の支持台などに載置した状態で搬送されるようになされている。なお、各接続用端子部２１の基端部を露出させるようにして上記各矩形領域２５を絶縁性の保護膜（図示略）によって覆ってもよい。
【００３５】
上記キャリアテープ２Ａの矩形領域２５には、図４および図５に良く表れているように上記矩形領域２５の平面視面積に略対応したシート状の異方性導電接着剤４が載置され、この異方性導電接着剤４上には、電極部３０を上記接続用端子部２１の基端部に対向させるようにして半導体チップ３が載置される。なお、異方性導電接着剤４としては、樹脂成分４０が粘液状とされたものを使用してもよい。
【００３６】
そして、上記異方性導電接着剤４を加熱するとともに、半導体チップ３をキャリアテープ２Ａに圧し付けることによって上記半導体チップ３が上記キャリアテープ２Ａに実装されて図６に示した状態とされる。上記異方性導電接着剤４の樹脂成分４０は、熱硬化性樹脂であることから、これを加熱した場合には樹脂成分４１が軟化させられる。この状態で、半導体チップ３をキャリアテープ２Ａに圧し付けた場合には、半導体チップ３の各電極部３０とキャリアテープ２Ａの各接続用端子部２１の間の樹脂成分４０が圧し退けられ、各電極部３０と各接続用端子部２１の間に導電成分４１が選択的に介在させられる。これにより、各電極部３０と各接続用端子部２１との間が電気的に接続される。なお、上記半導体チップ３を上記キャリアテープ２Ａに圧し付ける際に、超音波を付与してもよい。この場合には、各電極部３０と各接続用端子部２１との間に介在する導電成分４１が、各電極部３０および各接続用端子部２１のそれぞれと合金化し、機械的に強固で良好な電気的接続状態が得られる。さらに加熱を続ければ、一旦軟化した樹脂成分が硬化し、これにより半導体チップ３とキャリアテープ２Ａとが機械的に接続される。
【００３７】
続いて、図７に示したように、熱硬化性の保護樹脂５によって半導体チップ３とキャリアテープ２Ａの接続部分（異方性導電接着剤４）の周り、および上記半導体チップ３の周側面３ｃを囲む。この保護樹脂５としては、粘液状とされたものが好適に使用されるが、上記した異方性導電接着剤４を保護樹脂として使用してもよく、また別の樹脂を使用してもよい。もちろん、上記異方性導電接着剤４の樹脂成分を硬化させる前に上記保護樹脂５によって半導体チップ３の周りを囲んでもよい。この場合には、上記異方性導電接着剤４と同様の工程において上記保護樹脂５が硬化させられる。
【００３８】
次に、図８に示したように、上記キャリアテープ２Ａの表裏を反転させて、上記キャリアテープ２Ａの矩形領域２５に形成された各貫通孔２０に対応させてキャリアテープ２Ａの裏面側に複数の外部端子部９を格子状に配列形成する。具体的には、ハンダボール９０をハンダフラックス（図示略）とともに各貫通孔２０内に挿入し、ハンダボールを加熱して溶融させた後にこれを冷却固化することによって図９に示したようなボール状の外部端子部９がそれぞれ形成される。
【００３９】
このようにして各処理が終了した場合には、上記保護樹脂５の端縁の近傍において切断して絶縁性基板２となるべき領域を上記キャリアテープ２Ａから切り離すことによって図１ないし図３に示したような半導体装置１が得られる。
【００４０】
上記半導体装置１は、たとえば他の電子部品とともに所定の配線が形成された回路基板（図示略）上に実装されて使用される。上記半導体装置１の回路基板への実装は、上記半導体装置１の各外部端子部９を回路基板に形成された端子部に対応させて載置した後に、これを加熱炉に搬入するなどして外部端子部９（ボール状ハンダ）を再溶融させることによって実装される。このとき、外部端子部９が２００℃ないし３００℃程度にまで加熱されるが、上記異方性接着剤４も同程度の温度にまで加熱される。この際、異方性接着剤４に含まれる水分が体積膨張し、また気泡が成長してしまって異方性接着剤４内に応力が発生してしまうことが懸念される。
【００４１】
しかしながら、本実施形態では、上記異方性接着剤４の樹脂成分４０として多孔質性の樹脂を含むものが用いられており、また異方性接着剤４を囲む保護樹脂５として多孔質性の樹脂を含むものが用いられている。すなわち、異方性接着剤４および保護樹脂５としては通気性に優れる樹脂が採用されている。このため、加熱によって半導体装置１の異方性接着剤４内の水分が体積膨張し、また気泡が成長しようとしても、これらが上記異方性接着剤４の外部に排出され、さらに保護樹脂５の外部に排出されることとなる。したがって、本実施形態の半導体装置１では、上記半導体装置１を回路基板に実装する際に半導体装置１（異方性導電接着剤４）を加熱したとしても、異方性接着剤４内に応力が発生することはなく、この応力によって半導体チップ３がダメージを受けることもなく、また半導体チップ３から絶縁性基板２を引き離すような力が作用することもない。
【００４２】
なお、本実施形態においては、接着剤として樹脂成分４０内に導電成分４１が分散された異方性導電接着剤が採用されていたが、樹脂成分のみによって構成された接着剤を採用することもできる。この場合には、半導体チップ３の電極部３０と絶縁性基板２の接続用端子部２１の間の電気的な接続は、たとえばハンダなどの導電ペーストによって行われる。
【００４３】
【００４４】
【図面の簡単な説明】
【図１】 本願発明に係る半導体装置の一例を示す全体斜視図である。
【図２】 上記半導体装置を裏面側からみた全体斜視図である。
【図３】 図１のIII −III 線に沿う断面図である。
【図４】 上記半導体装置の製造に用いられるキャリアテープの一例を表す要部斜視図である。
【図５】 上記半導体装置の製造方法を説明するための断面図である。
【図６】 上記半導体装置の製造方法を説明するための断面図である。
【図７】 上記半導体装置の製造方法を説明するための断面図である。
【図８】 上記半導体装置の製造方法を説明するための要部を拡大した断面図である。
【図９】 上記半導体装置の製造方法を説明するための要部を拡大した断面図である。
【図１０】 従来の半導体装置を説明するための断面図である。
【符号の説明】
１ 半導体装置
２ 絶縁性基板
３ 半導体チップ
３ｃ 周側面（半導体チップの）
４ 異方性導電接着剤（樹脂性接着剤としての）
５ 保護樹脂
９ 外部端子部
２０ 貫通孔（絶縁性基板の）
２１ 接続用端子部（絶縁性基板の）
３０ 電極部（半導体チップの）
４０ 樹脂成分（異方性導電接着剤の）
４１ 導電成分（異方性導電接着剤の）[0001]
BACKGROUND OF THE INVENTION
The present invention provides a semiconductor chip mounting structure in which the semiconductor chip is mechanically connected to the mounting target by a resin adhesive interposed between the predetermined mounting target and the semiconductor chip, and the mounting structure. And a semiconductor device having a semiconductor chip mounted on an insulating substrate.
[0002]
[Prior art]
Conventionally, a semiconductor device having a structure in which a semiconductor chip is mounted on an insulating substrate is as shown in FIG. The semiconductor device 1 shown in the figure has a form called a so-called BGA (Ball Grid Array). In the semiconductor device 1, a plurality of connection terminal portions 21 are formed on the surface side of the insulating substrate 2, and a plurality of electrode portions 30 are formed on the main surface 3 a side of the semiconductor chip. The connection terminal portions 21 and the electrode portions 30 that are arranged are electrically connected. The semiconductor chip 3 and the insulating substrate 2 are mechanically connected via a resin adhesive 4. The insulating substrate 2 has a plurality of through holes 20 that are connected to the connection terminal portions 21 but are not clearly shown in the drawing, and are arranged in a lattice pattern. Each connection terminal portion 21 is electrically connected to a plurality of external terminal portions 9 formed on the back surface side of the insulating substrate 2. These external terminal portions 9 are each formed in a ball shape by solder and are preferably arranged in a lattice shape corresponding to the arrangement of the through holes 20.
[0003]
The semiconductor device 1 configured as described above is mounted on an appropriate circuit board together with other electronic components, for example, and used for a desired application. In the semiconductor device 1, since the external terminal portion 9 is formed by ball-shaped solder on the back side of the insulating substrate 2, the semiconductor device 1 is mounted on the circuit board when the semiconductor device 1 is mounted on the circuit board. It is necessary to remelt the ball-shaped solder as the external terminal portion 9 in a state where 1 is placed. Usually, the remelting of the solder is performed by, for example, carrying the circuit board on which the semiconductor device 1 is placed in a heating furnace heated to an atmospheric temperature of about 200 ° C. to 300 ° C. Heated to about 200 ° C to 300 ° C.
[0004]
[Problems to be solved by the invention]
In the semiconductor device 1, the semiconductor chip 3 and the insulating substrate 2 are mechanically connected by the resin adhesive 4. Usually, the resin adhesive 4 contains some moisture, In many cases, bubbles are formed. For this reason, when the semiconductor device 1 is heated, the moisture expands in volume and bubbles grow, acting as stress between the semiconductor chip 3 and the insulating substrate 2. Such stress acts on the semiconductor chip 3 and directly damages the semiconductor chip 3. In addition, it acts as a force for separating the semiconductor chip 3 and the insulating substrate 2, and the electrode part 30 of the semiconductor chip 3 and the connection terminal part 21 of the insulating substrate 1 may be disconnected.
[0005]
By the way, while the number of electrode parts 30 of the semiconductor chip 3 tends to increase as the number of functions of the semiconductor chip 3 increases, the semiconductor chip 3 itself tends to be downsized. For this reason, in the semiconductor device 1 having the configuration in which the semiconductor chip 3 is mounted on the insulating substrate 2, the size of the insulating substrate 2 is made closer to the semiconductor chip 3 in order to achieve miniaturization, and on the surface side of the insulating substrate 2. It is necessary to miniaturize the wiring (connection terminal portion 21) to be formed. However, in the semiconductor device 1 configured as a BGA, the external terminal portion 9 is configured as a ball-shaped solder, and even when the solder is melted, the balls are spaced at regular intervals so that adjacent ball-shaped solders do not contact each other. It is necessary to form a solder (external terminal 9). For this reason, if the number of external terminal portions 9 to be formed increases, there is a limit to reducing the insulating substrate 2. Further, since the insulating substrate 2 is formed by separating the region to be the substrate from the carrier tape on which the semiconductor chip 3 is mounted, the insulating substrate 2 is protected so as not to damage the semiconductor chip 3 at the time of cutting. It is usual to cut the planar view area so as to be one larger than that of the semiconductor chip 3.
[0006]
Under such circumstances, the peripheral portion 23 of the insulating substrate 2 protrudes from the semiconductor chip 3 in plan view as in the semiconductor device 1 shown in FIG. For this reason, when the semiconductor device 1 is handled, an external force acts on the portion 23 where the insulating substrate 2 protrudes, causing a problem that the insulating substrate 2 is peeled off from the semiconductor chip 3. In the semiconductor chip 3, since the semiconductor chip 3 is mounted on the insulating substrate 2 in a bare chip state, the semiconductor chip 3 may be lost due to an external force acting directly on the semiconductor chip 3.
[0007]
The present invention has been conceived under such circumstances, and maintains a good bonding state between a semiconductor chip and an object to be mounted such as an insulating substrate, and effectively protects the semiconductor chip. The challenge is to do so.
[0008]
DISCLOSURE OF THE INVENTION
In order to solve the above problems, the present invention takes the following technical means.
[0009]
That is, the semiconductor device is herein onset Ming Thus provided, a semiconductor chip portion a plurality of electrodes are formed on the main surface, part a plurality of connecting terminals is an insulating substrate formed on the upper surface of the semiconductor chip A semiconductor device electrically and mechanically connected by a resin adhesive interposed between the main surface and the upper surface of the insulating substrate on which the connection terminal portion is formed , the insulating substrate comprising: While having the peripheral part extended from the circumference | surroundings of the said semiconductor chip, while the surrounding side surface of the said semiconductor chip is surrounded by the protective resin which has porosity, this protective resin is the surrounding side surface of the said semiconductor chip. And fixed to the periphery of the resin adhesive and the upper surface of the peripheral portion of the insulating substrate in close contact with each other, and rides only on the peripheral portion on the surface opposite to the main surface of the semiconductor chip. , The resin adhesive has a structure in which a conductive component is dispersed in an insulating resin component, and is formed on a plurality of connection terminal portions formed on the insulating substrate and the main surface of the semiconductor chip. At least one of the plurality of electrode portions formed in a bump shape, and the conductive substrate is interposed between the connection terminal portions and the electrode portions arranged to face each other, and the insulating substrate The semiconductor chip is electrically connected, and the insulating substrate and the semiconductor chip are mechanically connected by the resin component .
[0010]
[0011]
[0012]
[0013]
In the above arrangement, since Dale surrounds around the semiconductor chip and the connecting portion between the insulating substrate (resin adhesive) by a protective resin, the impurities invades to the connection portion (the resin adhesive) Has been avoided. Further, if the peripheral side surface of the semiconductor chip is surrounded by a protective resin, the peripheral side surface of the semiconductor chip is protected, and the resistance force to the external force of the semiconductor chip is increased. Since the protective resin includes, for example, a phenolic thermosetting resin having porosity, the resin adhesive is surrounded by the protective resin so that the air permeability of the resin adhesive is increased. Will not be damaged.
[0014]
Further, the protective resin rides on the peripheral edge portion of the upper surface (surface opposite to the main surface) of the semiconductor chip. If it does in this way, the corner | angular part in the upper part of a semiconductor chip will be covered and protected by protective resin. Thereby, even if the semiconductor chip is mounted on the mounting target in a bare chip state, the semiconductor chip can be prevented from being chipped even when an external force is applied during handling.
[0015]
[0016]
[0017]
[0018]
Further, in the above configuration , a so-called anisotropic conductive adhesive is used for mounting the semiconductor chip on the insulating substrate . For this reason, the electrical connection and the mechanical connection can be performed in one step without separateing the step of electrically connecting the semiconductor chip and the insulating substrate and the step of mechanically connecting them. I can .
[0019]
[0020]
[0021]
[0022]
In a preferred embodiment, the insulating substrate has a plurality of through-holes arranged in a grid according to the number of the connection terminal portions, and each connection terminal is formed on the lower surface of the insulating substrate via the through-holes. A plurality of ball-shaped external terminal portions that are electrically connected to the portion are formed. That is, in the semiconductor device called a so-called BGA, can be adopted the structure of the present invention.
[0023]
In BGA, since the semiconductor device is mounted on a circuit board or the like by remelting the solder terminal portion, the resin adhesive is also heated to about 200 ° C. to 300 ° C. during the mounting. In the semiconductor device described above, since a resin adhesive containing a porous resin is used, even if moisture in the resin adhesive expands in volume or bubbles grow, these are resin bonded. The stress does not act on the semiconductor chip or the insulating substrate remaining in the agent. In this manner, the semiconductor chip itself is not damaged by the stress generated in the resin adhesive by heating, or a force that peels the insulating substrate from the semiconductor chip does not act.
[0024]
By the way, the wiring formed on the insulating substrate tends to be miniaturized due to the multi-function and miniaturization of the semiconductor chip, and for the convenience of manufacturing, the insulating substrate is more preferable than the semiconductor chip particularly in BGA. As described above, the plane view area is increased. That is, in the plan view, the peripheral edge of the insulating substrate protrudes from the semiconductor chip, which causes problems such as peeling of the insulating substrate. In the semiconductor device of the present invention, on the other hand, by the upper Symbol semiconductor chip and the insulating substrate and the connecting portion protecting resin containing porous resin around and circumferential side surfaces of the semiconductor chip (resin adhesive) Since it is configured to surround, the region where the peripheral edge of the insulating substrate protrudes from the semiconductor chip is also sealed with the protective resin, and the protruding portion is integrated with the semiconductor chip via the protective resin. . For this reason, it is difficult for an external force to act on the peripheral edge of the insulating substrate, thereby preventing the insulating substrate from being peeled off from the semiconductor chip.
[0025]
Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. 1 is an overall perspective view showing an example of a semiconductor device according to the present invention, FIG. 2 is an overall perspective view of the semiconductor device viewed from the back side, and FIG. 3 is a sectional view taken along line III-III in FIG. is there. In these drawings, elements, members, parts, and the like equivalent to those shown in the drawings referred to for explaining the conventional example are denoted by the same reference numerals. In the present embodiment, a semiconductor device configured as a so-called BGA (ball grid array) will be described.
[0027]
As shown in FIGS. 1 to 3, in the semiconductor device 1, the semiconductor chip 3 is mounted on an insulating substrate 2, and the semiconductor chip 3 and the insulating substrate 2 are interposed via a so-called anisotropic conductive adhesive 4. Are mechanically and electrically connected. A peripheral side surface 3c of the semiconductor chip 3 is surrounded by a protective resin 5, and a plurality of external terminal portions 9 are arranged in a grid pattern so as to protrude from the back side of the insulating substrate 2.
[0028]
The semiconductor chip 3 is a bare chip such as an IC chip or an LSI chip, and a plurality of electrode portions 30 are formed on the main surface 3a side. These electrode portions 30 have bumps 30b formed on the terminal pads 30a integrally formed on the semiconductor chip 3 by, for example, gold plating, and have a protruding shape as a whole.
[0029]
The insulating substrate 2 is made of, for example, polyimide resin, and has a rectangular shape in plan view as shown well in FIGS. 2 and 3 and has a larger area in plan view than the semiconductor chip 3. . For this reason, in a state where the semiconductor chip 3 is mounted on the insulating substrate 2, it is considered that the peripheral portion of the insulating substrate 2 protrudes from the semiconductor chip 3. The insulating substrate 2 has a plurality of through holes 20 arranged in a lattice pattern, and a plurality of connection terminals that are electrically connected to the electrode portions 30 of the semiconductor chip 3 on the upper surface thereof. A portion 21 is formed. Each connection terminal portion 21 has a base end portion facing each of the electrode portions 30 and a distal end portion extending to the corresponding through hole 20 to block the upper opening surface of each through hole 20. Yes. That is, from the back surface side of the insulating substrate 2, the front end portions of the connection terminal portions 21 face each other through the through holes 20. As shown in FIG. 3, the external terminal portions 9 are formed in a ball shape so as to fill the through holes 20 and to be in contact with the connection terminal portions 21. .
[0030]
The anisotropic conductive adhesive 4 is configured such that a ball-shaped conductive component 41 is dispersed in a thermosetting resin component 40 as shown in FIG. The semiconductor chip 3 and the insulating substrate 2 are mechanically connected by the resin component and electrically connected by the conductive component 41. The resin component 40 includes, for example, a phenolic resin as a porous resin, and may be composed of only a porous resin, or may include other resins. The phenolic resin referred to in the present invention includes, in addition to phenolic resins, epoxy resins made from phenols. The conductive component 41 is interposed between each electrode portion 30 of the semiconductor chip 3 and the base end portion of each connection terminal portion 21 of the insulating substrate 2, and each electrode portion 30 and each connection terminal portion 21. And are electrically connected. As the conductive component, for example, a conductive ball imparted with nickel plating or gold plating on the surface of the resin ball is preferably employed, but a metal ball may be used as the conductive component 41.
[0031]
The protective resin 5 seals the upper surface of the peripheral portion 23 of the insulating substrate 2, covers the periphery of the semiconductor chip 3, and climbs up to the upper surface 3 b of the semiconductor chip 3. That is, it surrounds the connection portion (anisotropic resin adhesive 4) between the semiconductor chip 3 and the insulating substrate 2 and the peripheral side surface 3c of the semiconductor chip 3, and the peripheral portion of the insulating substrate 2 23 is integrated with the semiconductor chip 3 via the protective resin 5. As the protective resin 5, for example, a resin containing a phenolic resin as a porous resin is preferably employed, as in the resin component 40 of the anisotropic conductive adhesive 4.
[0032]
As described above, in the semiconductor device 1, the peripheral portions of the peripheral side surface 3 c and the top surface 3 b of the semiconductor chip 3 are directly protected by the protective resin 5. For this reason, even if an external force acts on the semiconductor chip 3 when the semiconductor device 1 is handled, damage to the semiconductor chip 3 is reduced. Further, since the peripheral portion 23 of the insulating substrate 2 is integrated with the semiconductor chip 3 by the protective resin, it is difficult for external force to act directly on the peripheral portion 23 of the insulating substrate 2. Yes. Thereby, it is avoided that the external substrate acts on the peripheral end portion 23 of the insulating substrate 2 and the insulating substrate 2 is peeled off from the semiconductor chip 3.
[0033]
Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS. 4 to 9. For convenience, the carrier tape 2A used for manufacturing the semiconductor device 1 will be described first with reference to FIG. To do.
[0034]
As shown in FIG. 4, the carrier tape 2A has a longitudinal shape as a whole, and a plurality of rectangular regions 25 in which the semiconductor chip 3 surrounded by a virtual line is mounted are provided continuously in the longitudinal direction. Yes. As the carrier tape 2A, a tape or strip formed of an insulating material such as polyimide resin is preferably used. In each rectangular region 25, a plurality of through holes 20 are arranged in a grid pattern, and a plurality of connection terminal portions 21 are formed on the top surface thereof. These connection terminal portions 21 are formed, for example, by forming a metal film such as copper on the surface of the carrier tape 2A, or by attaching a metal foil and then performing an etching process. You may stick and form. Each of the connection terminal portions 21 has a distal end portion that closes an upper opening surface of each through-hole 20, and a proximal end portion that is formed corresponding to the electrode portion 30 formed on the semiconductor chip 3. In addition, locking holes 24 are continuously formed at constant pitches at both ends in the width direction of the carrier tape 2A, and the carrier tape 2A is appropriately attached using these locking holes 24. It is designed to be transported in a state of being placed on a support stand or the like. The rectangular regions 25 may be covered with an insulating protective film (not shown) so that the base end portions of the connection terminal portions 21 are exposed.
[0035]
In the rectangular area 25 of the carrier tape 2A, as shown in FIG. 4 and FIG. 5, a sheet-like anisotropic conductive adhesive 4 substantially corresponding to the planar view area of the rectangular area 25 is placed. On the anisotropic conductive adhesive 4, the semiconductor chip 3 is placed so that the electrode portion 30 faces the base end portion of the connection terminal portion 21. In addition, as the anisotropic conductive adhesive 4, you may use what the resin component 40 was made viscous.
[0036]
And while heating the said anisotropic conductive adhesive 4, the semiconductor chip 3 is mounted in the said carrier tape 2A by pressing the semiconductor chip 3 to the carrier tape 2A, and it will be in the state shown in FIG. Since the resin component 40 of the anisotropic conductive adhesive 4 is a thermosetting resin, the resin component 41 is softened when heated. In this state, when the semiconductor chip 3 is pressed against the carrier tape 2A, the resin component 40 between each electrode portion 30 of the semiconductor chip 3 and each connection terminal portion 21 of the carrier tape 2A is pressed and moved away. A conductive component 41 is selectively interposed between the electrode portion 30 and each connection terminal portion 21. Thereby, each electrode part 30 and each connection terminal part 21 are electrically connected. Note that ultrasonic waves may be applied when the semiconductor chip 3 is pressed against the carrier tape 2A. In this case, the conductive component 41 interposed between each electrode portion 30 and each connection terminal portion 21 is alloyed with each electrode portion 30 and each connection terminal portion 21 to be mechanically strong and good. An electrical connection state can be obtained. If the heating is further continued, the softened resin component is cured, whereby the semiconductor chip 3 and the carrier tape 2A are mechanically connected.
[0037]
Subsequently, as shown in FIG. 7, the thermosetting protective resin 5 surrounds the connection portion (anisotropic conductive adhesive 4) between the semiconductor chip 3 and the carrier tape 2A, and the peripheral side surface 3c of the semiconductor chip 3. Enclose. As the protective resin 5, a viscous liquid is preferably used, but the anisotropic conductive adhesive 4 described above may be used as the protective resin, or another resin may be used. . Of course, the semiconductor chip 3 may be surrounded by the protective resin 5 before the resin component of the anisotropic conductive adhesive 4 is cured. In this case, the protective resin 5 is cured in the same process as the anisotropic conductive adhesive 4.
[0038]
Next, as shown in FIG. 8, the front and back of the carrier tape 2A are reversed, and a plurality of pieces are formed on the back side of the carrier tape 2A so as to correspond to the through holes 20 formed in the rectangular region 25 of the carrier tape 2A. The external terminal portions 9 are arranged in a grid pattern. Specifically, a ball as shown in FIG. 9 is formed by inserting a solder ball 90 into each through hole 20 together with a solder flux (not shown), heating and melting the solder ball, and then cooling and solidifying it. Each of the external terminal portions 9 is formed.
[0039]
When each processing is completed in this way, the region to be the insulating substrate 2 is cut in the vicinity of the edge of the protective resin 5 and separated from the carrier tape 2A, as shown in FIGS. A semiconductor device 1 as described above is obtained.
[0040]
The semiconductor device 1 is used by being mounted on a circuit board (not shown) on which predetermined wiring is formed together with other electronic components, for example. The semiconductor device 1 is mounted on the circuit board by placing each external terminal portion 9 of the semiconductor device 1 in correspondence with the terminal portion formed on the circuit board and then carrying it into a heating furnace. The external terminal portion 9 (ball solder) is mounted by remelting. At this time, the external terminal portion 9 is heated to about 200 ° C. to 300 ° C., but the anisotropic adhesive 4 is also heated to a similar temperature. At this time, there is a concern that the moisture contained in the anisotropic adhesive 4 expands in volume, and the bubbles grow and stress is generated in the anisotropic adhesive 4.
[0041]
However, in the present embodiment, the resin component 40 of the anisotropic adhesive 4 includes a porous resin, and the protective resin 5 surrounding the anisotropic adhesive 4 is porous. A resin containing resin is used. That is, as the anisotropic adhesive 4 and the protective resin 5, a resin having excellent air permeability is employed. For this reason, even if the moisture in the anisotropic adhesive 4 of the semiconductor device 1 expands in volume due to heating and bubbles are to grow, these are discharged to the outside of the anisotropic adhesive 4 and further the protective resin 5 Will be discharged to the outside. Therefore, in the semiconductor device 1 of the present embodiment, even when the semiconductor device 1 (anisotropic conductive adhesive 4) is heated when the semiconductor device 1 is mounted on the circuit board, stress is generated in the anisotropic adhesive 4. The semiconductor chip 3 is not damaged by this stress, and a force that separates the insulating substrate 2 from the semiconductor chip 3 does not act.
[0042]
In the present embodiment, the anisotropic conductive adhesive in which the conductive component 41 is dispersed in the resin component 40 is used as the adhesive. However, an adhesive composed only of the resin component may be used. it can. In this case, the electrical connection between the electrode portion 30 of the semiconductor chip 3 and the connection terminal portion 21 of the insulating substrate 2 is performed by a conductive paste such as solder.
[0043]
[0044]
[Brief description of the drawings]
FIG. 1 is an overall perspective view showing an example of a semiconductor device according to the present invention.
FIG. 2 is an overall perspective view of the semiconductor device as viewed from the back side.
3 is a cross-sectional view taken along line III-III in FIG.
FIG. 4 is a main part perspective view showing an example of a carrier tape used for manufacturing the semiconductor device.
FIG. 5 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device.
FIG. 6 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device.
FIG. 7 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device.
FIG. 8 is an enlarged cross-sectional view of a main part for explaining the method of manufacturing the semiconductor device.
FIG. 9 is an enlarged cross-sectional view of a main part for explaining the method of manufacturing the semiconductor device.
FIG. 10 is a cross-sectional view for explaining a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Insulating substrate 3 Semiconductor chip 3c Peripheral side surface (of semiconductor chip)
4 Anisotropic conductive adhesive (as resinous adhesive)
5 Protective resin 9 External terminal 20 Through hole (of insulating substrate)
21 Terminal for connection (of insulating substrate)
30 Electrode (semiconductor chip)
40 Resin component (of anisotropic conductive adhesive)
41 Conductive component (of anisotropic conductive adhesive)

Claims (3)

主面に複数の電極部が形成された半導体チップと、複数の接続端子部が上面に形成された絶縁性基板とが、上記半導体チップの上記主面と上記絶縁性基板の上記接続端子部が形成された上面との間に介在させた樹脂接着剤によって電気的および機械的に接続された半導体装置であって、
上記絶縁性基板は、上記半導体チップの周囲から延出する周縁部を有している一方、
上記半導体チップの周側面は、多孔性を有する保護樹脂によって囲まれているとともに、この保護樹脂は、上記半導体チップの周側面と、上記樹脂接着剤の周囲と、上記絶縁性基板の上記周縁部の上面とに密着状態で固着され、かつ、上記半導体チップの上記主面と反対側の面における周縁部のみに乗り上げており、
上記樹脂接着剤は、絶縁性を有する樹脂成分中に導電成分を分散させた構造を有しているとともに、上記絶縁性基板に形成された複数の接続端子部および上記半導体チップの主面に形成された複数の電極部のうちの少なくとも一方がバンプ状とされており、互いに対向配置された上記各接続端子部と上記各電極部との間に上記導電成分が介在して上記絶縁性基板と上記半導体チップとが電気的に接続されているとともに、上記樹脂成分によって上記絶縁性基板と上記半導体チップとが機械的に接続されていることを特徴とする、半導体装置。 A semiconductor chip having a plurality of electrode portions formed on the main surface, and an insulating substrate having a plurality of connection terminal portions formed on the top surface, the main surface of the semiconductor chip and the connection terminal portions of the insulating substrate being A semiconductor device electrically and mechanically connected by a resin adhesive interposed between the formed upper surface ,
The insulating substrate has a peripheral edge extending from the periphery of the semiconductor chip,
The peripheral side surface of the semiconductor chip is surrounded by a porous protective resin, and the protective resin includes the peripheral side surface of the semiconductor chip, the periphery of the resin adhesive, and the peripheral portion of the insulating substrate. And sticks to the upper surface of the semiconductor chip, and runs only on the peripheral edge of the surface opposite to the main surface of the semiconductor chip,
The resin adhesive has a structure in which a conductive component is dispersed in an insulating resin component, and is formed on a plurality of connection terminal portions formed on the insulating substrate and the main surface of the semiconductor chip. At least one of the plurality of electrode portions formed in a bump shape, and the conductive substrate is interposed between the connection terminal portions and the electrode portions arranged to face each other, and the insulating substrate together with the semiconductor chip are electrically connected, and the insulating substrate and the semiconductor chip is characterized in that it is mechanically connected by the resin component, the semiconductor device. 上記絶縁性基板は、ポリイミド樹脂によってフィルム状に形成されている、請求項１に記載の半導体装置。The semiconductor device according to claim 1 , wherein the insulating substrate is formed in a film shape from a polyimide resin. 上記絶縁性基板には、上記接続端子部の数に応じた複数の貫通孔が格子状に配列形成されており、その下面に各貫通孔を介して各接続端子部とそれぞれ導通するボール状の外部端子部が複数形成されている、請求項１または２に記載の半導体装置。In the insulating substrate, a plurality of through holes corresponding to the number of the connection terminal portions are arranged in a grid pattern, and the bottom surface of each of the connection terminals is connected to each connection terminal portion via each through hole. external terminal portions are made multiple form, the semiconductor device according to claim 1 or 2.
JP23263598A 1997-11-21 1998-08-19 Semiconductor device Expired - Lifetime JP4086123B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP23263598A JP4086123B2 (en) 1998-02-10 1998-08-19 Semiconductor device
US09/196,884 US6204564B1 (en) 1997-11-21 1998-11-20 Semiconductor device and method for making the same
TW087119257A TW434646B (en) 1997-11-21 1998-11-20 Semiconductor device and method for making the same
KR10-1998-0050017A KR100357757B1 (en) 1997-11-21 1998-11-20 Semiconductor device and its manufacturing method

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2815698 1998-02-10
JP10-28156 1998-02-10
JP23263598A JP4086123B2 (en) 1998-02-10 1998-08-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH11297752A JPH11297752A (en) 1999-10-29
JP4086123B2 true JP4086123B2 (en) 2008-05-14

Family

ID=26366202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23263598A Expired - Lifetime JP4086123B2 (en) 1997-11-21 1998-08-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4086123B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4477202B2 (en) 2000-07-12 2010-06-09 ローム株式会社 Semiconductor device and manufacturing method thereof
KR100679816B1 (en) * 2001-01-03 2007-02-07 앰코 테크놀로지 코리아 주식회사 Semiconductor package
AU2003265209A1 (en) * 2003-09-03 2005-03-16 Infineon Technologies Ag Methods for packaging integrated circuits, and integrated circuit packages produced by the method
JP2005101125A (en) * 2003-09-24 2005-04-14 Seiko Epson Corp Semiconductor device, method of manufacturing same, circuit board, and electronic equipment
JP5039427B2 (en) * 2007-05-08 2012-10-03 株式会社ブリヂストン Mounting method of flexible driver IC and flexible driver IC
US8659169B2 (en) * 2010-09-27 2014-02-25 Xilinx, Inc. Corner structure for IC die
JP6484983B2 (en) * 2014-09-30 2019-03-20 日亜化学工業株式会社 Light emitting device and manufacturing method thereof

Also Published As

Publication number Publication date
JPH11297752A (en) 1999-10-29

Similar Documents

Publication Publication Date Title
US6734557B2 (en) Semiconductor device
KR0141067B1 (en) Electronic package with a thermally conductive support member having a thin circuitized substrate
KR100636770B1 (en) Semiconductor device and method for manufacturing the same
US7285446B2 (en) Mounting structure of semiconductor chip, semiconductor device and method of making the semiconductor device
US5773884A (en) Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
KR100231276B1 (en) Semiconductor package structure and its manufacturing method
WO2000070677A1 (en) Semiconductor device, method of manufacture thereof, circuit board, and electronic device
JP2001298115A (en) Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipment
US7473852B2 (en) Printed-circuit board and circuit unit incorporating the circuit board
JP3565090B2 (en) Method for manufacturing semiconductor device
JP4086123B2 (en) Semiconductor device
JP3460559B2 (en) Semiconductor device and its manufacturing method, circuit board, and electronic equipment
KR19990062839A (en) Semiconductor device and manufacturing method thereof, film carrier tape, circuit board and electronic device
US20160007463A1 (en) Electronic device module and method of manufacturing the same
US6426554B1 (en) Semiconductor device
JPH09326450A (en) Semiconductor device and its manufacture
JP2002026071A (en) Semiconductor device and its manufacturing method, circuit board, and electronic equipment
US6291893B1 (en) Power semiconductor device for “flip-chip” connections
US6229222B1 (en) Semiconductor device and method of fabricating the same
KR100246367B1 (en) Semiconductor package and manufacturing method
JP3509532B2 (en) Semiconductor device substrate, semiconductor device, method of manufacturing the same, and electronic device
JP4805362B2 (en) Manufacturing method of semiconductor device
JP2000133743A (en) Semiconductor chip mounting structure and semiconductor device having the same
JP2822987B2 (en) Electronic circuit package assembly and method of manufacturing the same
JP3680398B2 (en) Printed wiring board

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20041013

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20041026

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041222

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20050215

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050415

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20050421

A912 Removal of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20050520

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071227

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080213

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110228

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120229

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130228

Year of fee payment: 5