JPS61163424U - - Google Patents
Info
- Publication number
- JPS61163424U JPS61163424U JP4753685U JP4753685U JPS61163424U JP S61163424 U JPS61163424 U JP S61163424U JP 4753685 U JP4753685 U JP 4753685U JP 4753685 U JP4753685 U JP 4753685U JP S61163424 U JPS61163424 U JP S61163424U
- Authority
- JP
- Japan
- Prior art keywords
- field effect
- effect transistor
- bias resistor
- thermistor
- showing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
第1図はこの考案の一実施例によるFET増幅
器の要部を示す電気回路図、第2図は第1図に示
した回路の実際の部品配置を示す部分平面図、第
3図は従来のFET増幅器の要部を示す電気回路
図、第4図は第3図に示した回路の実際の部品配
置を示す部分平面図、第5図はサーミスタの温度
対抵抗値特性を示す線図、第6図は抵抗とサーミ
スタとの並列回路の温度対抵抗値特性を示す線数
である。
1はFET、2はバイアス抵抗、3aおよび3
bはコンデンサ、4aおよび4bは高周波チヨー
クコイル、5はサーミスタ。なお、図中、同一符
号は同一または相当部分を示す。
Fig. 1 is an electric circuit diagram showing the main parts of an FET amplifier according to an embodiment of this invention, Fig. 2 is a partial plan view showing the actual component arrangement of the circuit shown in Fig. 1, and Fig. 3 is a conventional circuit diagram. Fig. 4 is a partial plan view showing the actual component arrangement of the circuit shown in Fig. 3; Fig. 5 is a diagram showing the temperature vs. resistance value characteristics of the thermistor; Figure 6 shows the number of lines showing the temperature versus resistance value characteristic of a parallel circuit of a resistor and a thermistor. 1 is FET, 2 is bias resistor, 3a and 3
b is a capacitor, 4a and 4b are high frequency choke coils, and 5 is a thermistor. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
るとともに、この電界効果トランジスタのソース
電極とグラウンドとの間にバイアス抵抗が介挿さ
れてなる電界効果トランジスタ増幅器において、
上記バイアス抵抗と並列にサーミスタを接続した
ことを特徴とする電界効果トランジスタ増幅器。 In a field effect transistor amplifier in which the gate electrode of the field effect transistor is grounded and a bias resistor is inserted between the source electrode of the field effect transistor and the ground,
A field effect transistor amplifier characterized in that a thermistor is connected in parallel with the bias resistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4753685U JPS61163424U (en) | 1985-03-29 | 1985-03-29 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4753685U JPS61163424U (en) | 1985-03-29 | 1985-03-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61163424U true JPS61163424U (en) | 1986-10-09 |
Family
ID=30562954
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4753685U Pending JPS61163424U (en) | 1985-03-29 | 1985-03-29 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61163424U (en) |
-
1985
- 1985-03-29 JP JP4753685U patent/JPS61163424U/ja active Pending
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