JPS6455726U - - Google Patents
Info
- Publication number
- JPS6455726U JPS6455726U JP14998587U JP14998587U JPS6455726U JP S6455726 U JPS6455726 U JP S6455726U JP 14998587 U JP14998587 U JP 14998587U JP 14998587 U JP14998587 U JP 14998587U JP S6455726 U JPS6455726 U JP S6455726U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- control transistor
- field effect
- effect transistor
- added
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
第１図はこの考案の一実施例を示す図、第２図
は従来のアクテイブバイアス回路を示す図であり
、１は電界効果トランジスタ、２は制御用トラン
ジスタ、３はプラス電圧端子、４はバイパスコン
デンサ、５は抵抗、６，７はチヨーク回路、８〜
１３は抵抗、１４はマイナス電圧端子、１５，１
６は抵抗、１７は接続端子、１８はサーミスタで
ある。なお、各図中、同一符号は同一または相当
部分を示す。
Fig. 1 is a diagram showing an embodiment of this invention, and Fig. 2 is a diagram showing a conventional active bias circuit, where 1 is a field effect transistor, 2 is a control transistor, 3 is a positive voltage terminal, and 4 is a bypass circuit. Capacitor, 5 is resistor, 6, 7 is chain circuit, 8~
13 is a resistor, 14 is a negative voltage terminal, 15,1
6 is a resistor, 17 is a connection terminal, and 18 is a thermistor. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (1)
、上記電界効果トランジスタに直流バイアス電圧
、電流を供給する制御用トランジスタと、上記制
御用トランジスタに直流バイアス電圧、電流を供
給するためのプラス電圧端子及びマイナス電圧端
子とからなるアクテイブバイアス回路において、
制御用トランジスタのエミツタ端子と電界効果ト
ランジスタのドレイン端子間にチヨーク回路を付
加するとともに、制御用トランジスタのコレクタ
端子とマイナス電圧端子間に２個の抵抗を直列接
続し、かつ上記２個の抵抗接続端子と電界効果ト
ランジスタのゲート端子間に保護抵抗及びチヨー
ク回路を接続し、かつ制御用トランジスタのベー
ス端子と接地間に抵抗を、制御用トランジスタの
ベース端子とプラス電圧端子間にサーミスタを付
加したことを特徴とするアクテイブバイアス回路
。 A field effect transistor whose source terminal is grounded, a control transistor that supplies a DC bias voltage and current to the field effect transistor, and a positive voltage terminal and a negative voltage terminal that supply DC bias voltage and current to the control transistor. In an active bias circuit consisting of
A chain circuit is added between the emitter terminal of the control transistor and the drain terminal of the field effect transistor, and two resistors are connected in series between the collector terminal of the control transistor and the negative voltage terminal, and the above two resistors are connected. A protective resistor and a chi-yoke circuit are connected between the terminal and the gate terminal of the field effect transistor, and a resistor is added between the base terminal of the control transistor and the ground, and a thermistor is added between the base terminal of the control transistor and the positive voltage terminal. An active bias circuit featuring
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14998587U JPS6455726U (en) | 1987-09-30 | 1987-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14998587U JPS6455726U (en) | 1987-09-30 | 1987-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6455726U true JPS6455726U (en) | 1989-04-06 |
Family
ID=31422715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14998587U Pending JPS6455726U (en) | 1987-09-30 | 1987-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6455726U (en) |
-
1987
- 1987-09-30 JP JP14998587U patent/JPS6455726U/ja active Pending
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