JPS62105619U - - Google Patents
Info
- Publication number
- JPS62105619U JPS62105619U JP19668685U JP19668685U JPS62105619U JP S62105619 U JPS62105619 U JP S62105619U JP 19668685 U JP19668685 U JP 19668685U JP 19668685 U JP19668685 U JP 19668685U JP S62105619 U JPS62105619 U JP S62105619U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- reference voltage
- resistors
- resistor
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第１図は、本考案の一実施例を示す回路図、及
び第２図は従来のＡＬＣ回路を示す回路図である
。
３……録音増幅器、４……比較回路、１１……
基準電圧発生回路、１６，１７，２０，２３……
トランジスタ、１８，１９，２１，２２……抵抗
。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional ALC circuit. 3... Recording amplifier, 4 ... Comparison circuit, 11 ...
Reference voltage generation circuit, 16, 17, 20, 23...
Transistor, 18, 19, 21, 22...resistance.
Claims (1)
により前記出力信号のレベルを検出し、前記増幅
器の入力信号の減衰を行つて前記出力信号のレベ
ルを一定に保つ自動レベル制御回路において、ベ
ース及びエミツタが互いに共通接続された第１及
び第２トランジスタと、該第１及び第２トランジ
スタの共通ベースとアースとの間に接続された第
１抵抗と、ベースが前記第１トランジスタのコレ
クタにエミツタが第２抵抗を介して前記共通ベー
スに接続された第３トランジスタと、電源と前記
第３トランジスタのベースとの間に直列接続され
た第３及び第４抵抗と、ベースが前記第３及び第
４抵抗の接続点にエミツタが前記第２トランジス
タのコレクタに接続された第４トランジスタとか
ら成る基準電圧発生回路を設け、前記第４トラン
ジスタのエミツタ電圧を前記基準電圧とするとと
もに、前記第１抵抗を調整することにより前記基
準電圧を変化させる様にしたことを特徴とする自
動レベル制御回路。 The automatic level control circuit detects the level of the output signal by comparing the output signal of the amplifier with a reference voltage, and attenuates the input signal of the amplifier to keep the level of the output signal constant. a first resistor connected between the common bases of the first and second transistors and ground; a first resistor having a base connected to the collector of the first transistor and an emitter connected to the ground; a third transistor connected to the common base through two resistors; third and fourth resistors connected in series between a power supply and the base of the third transistor; and bases connected to the third and fourth resistors. A reference voltage generation circuit comprising a fourth transistor whose emitter is connected to the collector of the second transistor is provided at a connection point of the transistor, and the emitter voltage of the fourth transistor is set to the reference voltage, and the first resistor is adjusted. An automatic level control circuit characterized in that the reference voltage is changed by changing the reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19668685U JPH0354430Y2 (en) | 1985-12-20 | 1985-12-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19668685U JPH0354430Y2 (en) | 1985-12-20 | 1985-12-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62105619U true JPS62105619U (en) | 1987-07-06 |
| JPH0354430Y2 JPH0354430Y2 (en) | 1991-12-02 |
Family
ID=31155735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19668685U Expired JPH0354430Y2 (en) | 1985-12-20 | 1985-12-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0354430Y2 (en) |
-
1985
- 1985-12-20 JP JP19668685U patent/JPH0354430Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0354430Y2 (en) | 1991-12-02 |