JPS6059610U - Oscillator DC bias circuit - Google Patents
Oscillator DC bias circuitInfo
- Publication number
- JPS6059610U JPS6059610U JP15036083U JP15036083U JPS6059610U JP S6059610 U JPS6059610 U JP S6059610U JP 15036083 U JP15036083 U JP 15036083U JP 15036083 U JP15036083 U JP 15036083U JP S6059610 U JPS6059610 U JP S6059610U
- Authority
- JP
- Japan
- Prior art keywords
- bias circuit
- oscillator
- gate
- ground
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のセルフバイアス回路図、第２図は本考案
の一実施例の直流バイアス回路図、第３図は本考案の直
流バイアス回路を用いた発振回路図、第４図は第３図に
示す発振回路の温度特性線図である。
１・・・電源電圧入力端子、２・・・ＦＥＴ、３・・・
ドレイン電極、４・・・ソース電極、５・・・ゲート電
極、６・・・抵抗、７・・・ダイオード、８・・・バリ
スタ、９・・・抵抗、１０・・・電源電圧入力端子、１
１・・・同調電圧入力端子、１２，１３，１４・・・リ
アクタンス回路、１５・・・容量、１６・・・バラクタ
ダイオード。Figure 1 is a conventional self-bias circuit diagram, Figure 2 is a DC bias circuit diagram of an embodiment of the present invention, Figure 3 is an oscillation circuit diagram using the DC bias circuit of the present invention, and Figure 4 is a diagram of an oscillation circuit using the DC bias circuit of the present invention. FIG. 3 is a temperature characteristic diagram of the oscillation circuit shown in the figure. 1...Power supply voltage input terminal, 2...FET, 3...
Drain electrode, 4... Source electrode, 5... Gate electrode, 6... Resistor, 7... Diode, 8... Varistor, 9... Resistor, 10... Power supply voltage input terminal, 1
1... Tuning voltage input terminal, 12, 13, 14... Reactance circuit, 15... Capacity, 16... Varactor diode.
Claims (1)
し、ゲートとアース間に少なくとも１個のバリスタを接
続し、ソースとゲート間に抵抗を接続して構成したこと
を特徴とする発振器の直流バイアス回路。A DC bias for an oscillator characterized in that a plurality of diodes are connected between the source and the ground of an FET, at least one varistor is connected between the gate and the ground, and a resistor is connected between the source and the gate. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15036083U JPS6059610U (en) | 1983-09-30 | 1983-09-30 | Oscillator DC bias circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15036083U JPS6059610U (en) | 1983-09-30 | 1983-09-30 | Oscillator DC bias circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6059610U true JPS6059610U (en) | 1985-04-25 |
Family
ID=30333512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15036083U Pending JPS6059610U (en) | 1983-09-30 | 1983-09-30 | Oscillator DC bias circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6059610U (en) |
-
1983
- 1983-09-30 JP JP15036083U patent/JPS6059610U/en active Pending
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